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authorBing Zhao <bzhao@marvell.com>2011-11-16 20:40:35 -0800
committerJohn W. Linville <linville@tuxdriver.com>2011-11-17 15:45:19 -0500
commite3bea1c8751d297c197949db01aa1e7adbc1104d (patch)
tree188650f4f4a1fc57106d92215e7dcc40106f9198 /drivers/net/wireless/mwifiex/cfp.c
parent7adb92faa852589ad60ebd5ff94fc53c0882ebd5 (diff)
mwifiex: add support for Marvell sd8797 device
This patch supports Marvell chipset 88W8797 (Avastar) with SDIO interface. The corresponding firmware image file is located at: "mrvl/sd8797_uapsta.bin" Signed-off-by: Bing Zhao <bzhao@marvell.com> Signed-off-by: Tristan Xu <xurf@marvell.com> Signed-off-by: Amitkumar Karwar <akarwar@marvell.com> Signed-off-by: Kiran Divekar <dkiran@marvell.com> Signed-off-by: Frank Huang <frankh@marvell.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/mwifiex/cfp.c')
-rw-r--r--drivers/net/wireless/mwifiex/cfp.c38
1 files changed, 26 insertions, 12 deletions
diff --git a/drivers/net/wireless/mwifiex/cfp.c b/drivers/net/wireless/mwifiex/cfp.c
index f2e6de03805..1782a77f15d 100644
--- a/drivers/net/wireless/mwifiex/cfp.c
+++ b/drivers/net/wireless/mwifiex/cfp.c
@@ -75,18 +75,32 @@ static u8 supported_rates_n[N_SUPPORTED_RATES] = { 0x02, 0x04, 0 };
* This function maps an index in supported rates table into
* the corresponding data rate.
*/
-u32 mwifiex_index_to_data_rate(u8 index, u8 ht_info)
+u32 mwifiex_index_to_data_rate(struct mwifiex_private *priv, u8 index,
+ u8 ht_info)
{
- u16 mcs_rate[4][8] = {
- {0x1b, 0x36, 0x51, 0x6c, 0xa2, 0xd8, 0xf3, 0x10e}
- , /* LG 40M */
- {0x1e, 0x3c, 0x5a, 0x78, 0xb4, 0xf0, 0x10e, 0x12c}
- , /* SG 40M */
- {0x0d, 0x1a, 0x27, 0x34, 0x4e, 0x68, 0x75, 0x82}
- , /* LG 20M */
- {0x0e, 0x1c, 0x2b, 0x39, 0x56, 0x73, 0x82, 0x90}
- }; /* SG 20M */
-
+ /*
+ * For every mcs_rate line, the first 8 bytes are for stream 1x1,
+ * and all 16 bytes are for stream 2x2.
+ */
+ u16 mcs_rate[4][16] = {
+ /* LGI 40M */
+ { 0x1b, 0x36, 0x51, 0x6c, 0xa2, 0xd8, 0xf3, 0x10e,
+ 0x36, 0x6c, 0xa2, 0xd8, 0x144, 0x1b0, 0x1e6, 0x21c },
+
+ /* SGI 40M */
+ { 0x1e, 0x3c, 0x5a, 0x78, 0xb4, 0xf0, 0x10e, 0x12c,
+ 0x3c, 0x78, 0xb4, 0xf0, 0x168, 0x1e0, 0x21c, 0x258 },
+
+ /* LGI 20M */
+ { 0x0d, 0x1a, 0x27, 0x34, 0x4e, 0x68, 0x75, 0x82,
+ 0x1a, 0x34, 0x4e, 0x68, 0x9c, 0xd0, 0xea, 0x104 },
+
+ /* SGI 20M */
+ { 0x0e, 0x1c, 0x2b, 0x39, 0x56, 0x73, 0x82, 0x90,
+ 0x1c, 0x39, 0x56, 0x73, 0xad, 0xe7, 0x104, 0x120 }
+ };
+ u32 mcs_num_supp =
+ (priv->adapter->hw_dev_mcs_support == HT_STREAM_2X2) ? 16 : 8;
u32 rate;
if (ht_info & BIT(0)) {
@@ -95,7 +109,7 @@ u32 mwifiex_index_to_data_rate(u8 index, u8 ht_info)
rate = 0x0D; /* MCS 32 SGI rate */
else
rate = 0x0C; /* MCS 32 LGI rate */
- } else if (index < 8) {
+ } else if (index < mcs_num_supp) {
if (ht_info & BIT(1)) {
if (ht_info & BIT(2))
/* SGI, 40M */