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authorArik Nemtsov <arik@wizery.com>2012-05-29 12:40:50 +0300
committerLuciano Coelho <coelho@ti.com>2012-06-08 09:42:09 +0300
commitd61c6b5550c759728e702e68c8423a23a6991fc3 (patch)
tree1e733d927e1ded7a11b620191a18f48f19905d7d /drivers/net/wireless/ti/wl18xx/conf.h
parent8dd8e53c6f0a5116b988445484b1d68d8e22ced9 (diff)
wl18xx: align wl18xx_conf_phy with FW variant and remove it
wl18xx_conf_phy represents part of the FW native wl18xx_mac_and_phy_params structure. Remove it and replace the phy part of the wl18xx conf with the FW bound structure. This allows us to set/override all members. Increment the wlconf version to ensure compatibility with the new structure Signed-off-by: Arik Nemtsov <arik@wizery.com> Signed-off-by: Luciano Coelho <coelho@ti.com>
Diffstat (limited to 'drivers/net/wireless/ti/wl18xx/conf.h')
-rw-r--r--drivers/net/wireless/ti/wl18xx/conf.h37
1 files changed, 33 insertions, 4 deletions
diff --git a/drivers/net/wireless/ti/wl18xx/conf.h b/drivers/net/wireless/ti/wl18xx/conf.h
index 130546aa970..fac0b7e87e7 100644
--- a/drivers/net/wireless/ti/wl18xx/conf.h
+++ b/drivers/net/wireless/ti/wl18xx/conf.h
@@ -23,41 +23,70 @@
#define __WL18XX_CONF_H__
#define WL18XX_CONF_MAGIC 0x10e100ca
-#define WL18XX_CONF_VERSION (WLCORE_CONF_VERSION | 0x0001)
+#define WL18XX_CONF_VERSION (WLCORE_CONF_VERSION | 0x0002)
#define WL18XX_CONF_MASK 0x0000ffff
#define WL18XX_CONF_SIZE (WLCORE_CONF_SIZE + \
sizeof(struct wl18xx_priv_conf))
-struct wl18xx_conf_phy {
+#define NUM_OF_CHANNELS_11_ABG 150
+#define NUM_OF_CHANNELS_11_P 7
+#define WL18XX_NUM_OF_SUB_BANDS 9
+#define SRF_TABLE_LEN 16
+#define PIN_MUXING_SIZE 2
+
+struct wl18xx_mac_and_phy_params {
u8 phy_standalone;
u8 rdl;
u8 enable_clpc;
u8 enable_tx_low_pwr_on_siso_rdl;
u8 auto_detect;
u8 dedicated_fem;
+
u8 low_band_component;
+
+ /* Bit 0: One Hot, Bit 1: Control Enable, Bit 2: 1.8V, Bit 3: 3V */
u8 low_band_component_type;
+
u8 high_band_component;
+
+ /* Bit 0: One Hot, Bit 1: Control Enable, Bit 2: 1.8V, Bit 3: 3V */
u8 high_band_component_type;
+ u8 number_of_assembled_ant2_4;
+ u8 number_of_assembled_ant5;
+ u8 pin_muxing_platform_options[PIN_MUXING_SIZE];
+ u8 external_pa_dc2dc;
u8 tcxo_ldo_voltage;
u8 xtal_itrim_val;
u8 srf_state;
+ u8 srf1[SRF_TABLE_LEN];
+ u8 srf2[SRF_TABLE_LEN];
+ u8 srf3[SRF_TABLE_LEN];
u8 io_configuration;
u8 sdio_configuration;
u8 settings;
u8 rx_profile;
+ u8 per_chan_pwr_limit_arr_11abg[NUM_OF_CHANNELS_11_ABG];
+ u8 pwr_limit_reference_11_abg;
+ u8 per_chan_pwr_limit_arr_11p[NUM_OF_CHANNELS_11_P];
+ u8 pwr_limit_reference_11p;
+ u8 per_sub_band_tx_trace_loss[WL18XX_NUM_OF_SUB_BANDS];
+ u8 per_sub_band_rx_trace_loss[WL18XX_NUM_OF_SUB_BANDS];
u8 primary_clock_setting_time;
u8 clock_valid_on_wake_up;
u8 secondary_clock_setting_time;
- u8 pwr_limit_reference_11_abg;
+ u8 board_type;
+ /* enable point saturation */
u8 psat;
+ /* low/medium/high Tx power in dBm */
s8 low_power_val;
s8 med_power_val;
s8 high_power_val;
+ u8 padding[1];
} __packed;
struct wl18xx_priv_conf {
- struct wl18xx_conf_phy phy;
+ /* this structure is copied wholesale to FW */
+ struct wl18xx_mac_and_phy_params phy;
} __packed;
#endif /* __WL18XX_CONF_H__ */