diff options
| author | Jon Mason <jon.mason@intel.com> | 2012-09-28 11:38:48 -0700 |
|---|---|---|
| committer | Jon Mason <jon.mason@intel.com> | 2013-09-03 14:48:53 -0700 |
| commit | be4dac0fcacd7d62e0b4f7ff51a7032e197b62af (patch) | |
| tree | 447d6181ed4ff4e8f029374371b2af8e3229bf8e /drivers/ntb/ntb_hw.h | |
| parent | 113bf1c9f1e035129f8631b032669d6ab36a14dd (diff) | |
NTB: Update Device IDs
Add support for new Intel NTB devices on upcoming Xeon hardware. Since
the Xeon hardware design is already in place in the driver, all that is
needed are the new device ids.
Remove the device IDs for NTB devs running in Transparent Bridge mode,
as this driver is not being used for those devices.
Rename the device IDs for NTB devs running in NTB-RP mode to better
identify their usage model. "PS" to denote the Primary Side of NTB, and
"SS" to denote the secondary side. The primary side is the interface
exposed to the local system, and the secondary side is the interface
exposed to the remote system.
Signed-off-by: Jon Mason <jon.mason@intel.com>
Diffstat (limited to 'drivers/ntb/ntb_hw.h')
| -rw-r--r-- | drivers/ntb/ntb_hw.h | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/ntb/ntb_hw.h b/drivers/ntb/ntb_hw.h index 3a15d492593..591d4ff5d88 100644 --- a/drivers/ntb/ntb_hw.h +++ b/drivers/ntb/ntb_hw.h @@ -47,12 +47,17 @@ */ #define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725 -#define PCI_DEVICE_ID_INTEL_NTB_CLASSIC_JSF 0x3726 -#define PCI_DEVICE_ID_INTEL_NTB_RP_JSF 0x3727 -#define PCI_DEVICE_ID_INTEL_NTB_RP_SNB 0x3C08 +#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726 +#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727 #define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D -#define PCI_DEVICE_ID_INTEL_NTB_CLASSIC_SNB 0x3C0E -#define PCI_DEVICE_ID_INTEL_NTB_2ND_SNB 0x3C0F +#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E +#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F +#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D +#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E +#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F +#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D +#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E +#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F #define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E #define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1) |