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authorYu Zhao <yu.zhao@intel.com>2009-06-13 15:52:15 +0800
committerJesse Barnes <jbarnes@virtuousgeek.org>2009-06-16 14:30:16 -0700
commitc12ff1df5f114484e3d8abd028769a624cc3399f (patch)
tree410cb0adf85a52772d5acf6621b421c33b44820a /drivers/pci/pci.c
parentf85876ba82281f15bc4da11e41b94243a8b2b5b4 (diff)
PCI: support Secondary Bus Reset
PCI-to-PCI Bridge 1.2 specifies that the Secondary Bus Reset bit can force the assertion of RST# on the secondary interface, which can be used to reset all devices including subordinates under this bus. This can be used to reset a function if this function is the only device under this bus. Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci/pci.c')
-rw-r--r--drivers/pci/pci.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 2e58acc66a8..c56a4a0355a 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -2162,6 +2162,33 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
return 0;
}
+static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
+{
+ u16 ctrl;
+ struct pci_dev *pdev;
+
+ if (dev->subordinate)
+ return -ENOTTY;
+
+ list_for_each_entry(pdev, &dev->bus->devices, bus_list)
+ if (pdev != dev)
+ return -ENOTTY;
+
+ if (probe)
+ return 0;
+
+ pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
+ ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
+ pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
+ msleep(100);
+
+ ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
+ pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
+ msleep(100);
+
+ return 0;
+}
+
static int pci_dev_reset(struct pci_dev *dev, int probe)
{
int rc;
@@ -2183,6 +2210,10 @@ static int pci_dev_reset(struct pci_dev *dev, int probe)
goto done;
rc = pci_pm_reset(dev, probe);
+ if (rc != -ENOTTY)
+ goto done;
+
+ rc = pci_parent_bus_reset(dev, probe);
done:
if (!probe) {
up(&dev->dev.sem);