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authorHuang, Xiong <xiong@qca.qualcomm.com>2012-04-25 20:27:14 +0000
committerDavid S. Miller <davem@davemloft.net>2012-04-26 05:03:32 -0400
commitce5b972bc840d024289c73a096d61cfdf57eff2e (patch)
tree6d51dab262288aa3ac1d33b8cfce5e224d4112b0 /drivers/pps
parent7c6c44f064adf11628c8815cab02f3bdf95ef8bc (diff)
atl1c: update PHY reset related routine
Many magic data are re-configured for PHY during its reset operation based on chip type to get better compability and stability. REG_PHY_CTRL register may be configured by BIOS before enter OS. so, the driver can't directly write to it without any Read-Op. this change also affect suspend and phy_disable routines. PHY debug ports and extension registers are refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/pps')
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