diff options
| author | Stephen M. Cameron <scameron@beardog.cce.hp.com> | 2012-05-01 11:42:30 -0500 |
|---|---|---|
| committer | James Bottomley <JBottomley@Parallels.com> | 2012-05-10 09:11:43 +0100 |
| commit | 2c17d2da8c9ef2c5be5077d3995041791e38094d (patch) | |
| tree | a305edafa6170096b2cffc1100a38fbb33d7a28c /drivers/scsi/hpsa.h | |
| parent | 21b8e4ef0357041854819d0f97bf1052ab4763e6 (diff) | |
[SCSI] hpsa: do not read from controller unnecessarily in completion code
MSI/MSI-X interrupts can't race the DMA completion they are communicating
so no need to read from controller to flush the DMA to the host if
MSI or MSI-X interrupts are being used.
Signed-off-by: Stephen M. Cameron <scameron@beardog.cce.hp.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi/hpsa.h')
| -rw-r--r-- | drivers/scsi/hpsa.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/scsi/hpsa.h b/drivers/scsi/hpsa.h index 7b28d54fa87..48f78123d1e 100644 --- a/drivers/scsi/hpsa.h +++ b/drivers/scsi/hpsa.h @@ -258,12 +258,12 @@ static unsigned long SA5_performant_completed(struct ctlr_info *h) { unsigned long register_value = FIFO_EMPTY; - /* flush the controller write of the reply queue by reading - * outbound doorbell status register. - */ - register_value = readl(h->vaddr + SA5_OUTDB_STATUS); /* msi auto clears the interrupt pending bit. */ if (!(h->msi_vector || h->msix_vector)) { + /* flush the controller write of the reply queue by reading + * outbound doorbell status register. + */ + register_value = readl(h->vaddr + SA5_OUTDB_STATUS); writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); /* Do a read in order to flush the write to the controller * (as per spec.) |