diff options
| author | Andrew Vasquez <andrew.vasquez@qlogic.com> | 2005-11-08 14:37:48 -0800 |
|---|---|---|
| committer | James Bottomley <jejb@mulgrave.(none)> | 2005-11-09 16:19:23 -0500 |
| commit | 335a1cc976ffbb58491a9b6dc58955349e3f0388 (patch) | |
| tree | 8a5fd35e3cbd278bccd34b241ef5c99d6ea477a6 /drivers/scsi/qla2xxx/qla_init.c | |
| parent | 8d5708f3b5ea0765af92a79ebc4144c91718e695 (diff) | |
[SCSI] qla2xxx: Correct ISP24xx soft-reset handling.
A driver must wait 100us before attempting an MMIO operation
to the RISC after a soft-reset has been initiated. A
similar delay was needed with earlier ISPs.
Note: a PCI config-space read is used to flush the MMIO
write to the ISP, since the ISP's state machines are unable
to respond to any MMIO read during the reset process.
Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi/qla2xxx/qla_init.c')
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_init.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c index 8fb084b706e..2d720121a0d 100644 --- a/drivers/scsi/qla2xxx/qla_init.c +++ b/drivers/scsi/qla2xxx/qla_init.c @@ -567,6 +567,7 @@ qla24xx_reset_risc(scsi_qla_host_t *ha) unsigned long flags = 0; struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; uint32_t cnt, d2; + uint16_t wd; spin_lock_irqsave(&ha->hardware_lock, flags); @@ -581,10 +582,10 @@ qla24xx_reset_risc(scsi_qla_host_t *ha) WRT_REG_DWORD(®->ctrl_status, CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); - RD_REG_DWORD(®->ctrl_status); + pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); + udelay(100); /* Wait for firmware to complete NVRAM accesses. */ - udelay(5); d2 = (uint32_t) RD_REG_WORD(®->mailbox0); for (cnt = 10000 ; cnt && d2; cnt--) { udelay(5); @@ -592,7 +593,7 @@ qla24xx_reset_risc(scsi_qla_host_t *ha) barrier(); } - udelay(20); + /* Wait for soft-reset to complete. */ d2 = RD_REG_DWORD(®->ctrl_status); for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) { udelay(5); |