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authorArun Easi <arun.easi@qlogic.com>2012-08-22 14:21:16 -0400
committerJames Bottomley <JBottomley@Parallels.com>2012-09-24 12:10:50 +0400
commitfafbda9f9cdeb3d29d8cb50ac029f704f52fac49 (patch)
tree53ddf9d94a3b9e81938d61670c2b5bd150714093 /drivers/scsi/qla2xxx
parent711aa7f722821405125b2a3c6a3e6a3f275952bd (diff)
[SCSI] qla2xxx: Use #defines instead of hardcoded values for intr status.
Signed-off-by: Arun Easi <arun.easi@qlogic.com> Signed-off-by: Chad Dupuis <chad.dupuis@qlogic.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat (limited to 'drivers/scsi/qla2xxx')
-rw-r--r--drivers/scsi/qla2xxx/qla_def.h11
-rw-r--r--drivers/scsi/qla2xxx/qla_isr.c36
2 files changed, 29 insertions, 18 deletions
diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
index ff891929303..c4e77d7bb08 100644
--- a/drivers/scsi/qla2xxx/qla_def.h
+++ b/drivers/scsi/qla2xxx/qla_def.h
@@ -675,6 +675,17 @@ typedef struct {
/* 83XX FCoE specific */
#define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
+/* Interrupt type codes */
+#define INTR_ROM_MB_SUCCESS 0x1
+#define INTR_ROM_MB_FAILED 0x2
+#define INTR_MB_SUCCESS 0x10
+#define INTR_MB_FAILED 0x11
+#define INTR_ASYNC_EVENT 0x12
+#define INTR_RSP_QUE_UPDATE 0x13
+#define INTR_RSP_QUE_UPDATE_83XX 0x14
+#define INTR_ATIO_QUE_UPDATE 0x1C
+#define INTR_ATIO_RSP_QUE_UPDATE 0x1D
+
/* ISP mailbox loopback echo diagnostic error code */
#define MBS_LB_RESET 0x17
/*
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c
index 686099267dd..a551827d3ed 100644
--- a/drivers/scsi/qla2xxx/qla_isr.c
+++ b/drivers/scsi/qla2xxx/qla_isr.c
@@ -2522,29 +2522,29 @@ qla24xx_intr_handler(int irq, void *dev_id)
break;
switch (stat & 0xff) {
- case 0x1:
- case 0x2:
- case 0x10:
- case 0x11:
+ case INTR_ROM_MB_SUCCESS:
+ case INTR_ROM_MB_FAILED:
+ case INTR_MB_SUCCESS:
+ case INTR_MB_FAILED:
qla24xx_mbx_completion(vha, MSW(stat));
status |= MBX_INTERRUPT;
break;
- case 0x12:
+ case INTR_ASYNC_EVENT:
mb[0] = MSW(stat);
mb[1] = RD_REG_WORD(&reg->mailbox1);
mb[2] = RD_REG_WORD(&reg->mailbox2);
mb[3] = RD_REG_WORD(&reg->mailbox3);
qla2x00_async_event(vha, rsp, mb);
break;
- case 0x13:
- case 0x14:
+ case INTR_RSP_QUE_UPDATE:
+ case INTR_RSP_QUE_UPDATE_83XX:
qla24xx_process_response_queue(vha, rsp);
break;
- case 0x1C: /* ATIO queue updated */
+ case INTR_ATIO_QUE_UPDATE:
qlt_24xx_process_atio_queue(vha);
break;
- case 0x1D: /* ATIO and response queues updated */
+ case INTR_ATIO_RSP_QUE_UPDATE:
qlt_24xx_process_atio_queue(vha);
qla24xx_process_response_queue(vha, rsp);
break;
@@ -2673,29 +2673,29 @@ qla24xx_msix_default(int irq, void *dev_id)
break;
switch (stat & 0xff) {
- case 0x1:
- case 0x2:
- case 0x10:
- case 0x11:
+ case INTR_ROM_MB_SUCCESS:
+ case INTR_ROM_MB_FAILED:
+ case INTR_MB_SUCCESS:
+ case INTR_MB_FAILED:
qla24xx_mbx_completion(vha, MSW(stat));
status |= MBX_INTERRUPT;
break;
- case 0x12:
+ case INTR_ASYNC_EVENT:
mb[0] = MSW(stat);
mb[1] = RD_REG_WORD(&reg->mailbox1);
mb[2] = RD_REG_WORD(&reg->mailbox2);
mb[3] = RD_REG_WORD(&reg->mailbox3);
qla2x00_async_event(vha, rsp, mb);
break;
- case 0x13:
- case 0x14:
+ case INTR_RSP_QUE_UPDATE:
+ case INTR_RSP_QUE_UPDATE_83XX:
qla24xx_process_response_queue(vha, rsp);
break;
- case 0x1C: /* ATIO queue updated */
+ case INTR_ATIO_QUE_UPDATE:
qlt_24xx_process_atio_queue(vha);
break;
- case 0x1D: /* ATIO and response queues updated */
+ case INTR_ATIO_RSP_QUE_UPDATE:
qlt_24xx_process_atio_queue(vha);
qla24xx_process_response_queue(vha, rsp);
break;