diff options
author | Jason Wang <jason77.wang@gmail.com> | 2010-10-19 18:03:27 +0800 |
---|---|---|
committer | Grant Likely <grant.likely@secretlab.ca> | 2010-10-20 10:30:53 -0600 |
commit | e1993ed6420afd4421336d75e73641f75da87a7f (patch) | |
tree | c511d2aabbf7107620123954757df7bf7264c404 /drivers/spi/dw_spi_mmio.c | |
parent | db181a8ee158fd0ccea2e2670c4f2d36af2814a0 (diff) |
spi/omap2_mcspi: disable channel after TX_ONLY transfer in PIO mode
In the TX_ONLY transfer, the SPI controller also receives data
simultaneously and saves them in the rx register. After the TX_ONLY
transfer, the rx register will hold the random data received during
the last tx transaction.
If the direct following transfer is RX_ONLY, this random data has the
possibility to affect this transfer like this:
When the SPI controller is changed from TX_ONLY to RX_ONLY,
the random data makes the rx register full immediately and
triggers a dummy write automatically(in SPI RX_ONLY transfers,
we need a dummy write to trigger the first transaction).
So the first data received in the RX_ONLY transfer will be that
random data instead of something meaningful.
We can avoid this by inserting a Disable/Re-enable toggle of the
channel after the TX_ONLY transfer, since it purges the rx register.
Signed-off-by: Jason Wang <jason77.wang@gmail.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/spi/dw_spi_mmio.c')
0 files changed, 0 insertions, 0 deletions