diff options
| author | Sathya Perla <sathyap@serverengines.com> | 2008-11-11 10:57:37 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2009-01-06 13:52:15 -0800 |
| commit | 7f4252318da8d750e7cf6848687d77732b2af8f5 (patch) | |
| tree | f028a7ed51bee9711ae4576be134d41f76e86dba /drivers/staging/benet/ep.h | |
| parent | 2774de17ba65130165a2cbca92e5a685581f7916 (diff) | |
Staging: benet: patch to remove subdirectories
Here's a patch tp remove the subdirectories in staging/benet (1st item in
staging/benet/TODO).
Signed-off-by: Sathya Perla <sathyap@serverengines.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/benet/ep.h')
| -rw-r--r-- | drivers/staging/benet/ep.h | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/drivers/staging/benet/ep.h b/drivers/staging/benet/ep.h new file mode 100644 index 00000000000..72fcf64a9ff --- /dev/null +++ b/drivers/staging/benet/ep.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2005 - 2008 ServerEngines + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. The full GNU General + * Public License is included in this distribution in the file called COPYING. + * + * Contact Information: + * linux-drivers@serverengines.com + * + * ServerEngines + * 209 N. Fair Oaks Ave + * Sunnyvale, CA 94085 + */ +/* + * Autogenerated by srcgen version: 0127 + */ +#ifndef __ep_amap_h__ +#define __ep_amap_h__ + +/* General Control and Status Register. */ +struct BE_EP_CONTROL_CSR_AMAP { + u8 m0_RxPbuf; /* DWORD 0 */ + u8 m1_RxPbuf; /* DWORD 0 */ + u8 m2_RxPbuf; /* DWORD 0 */ + u8 ff_en; /* DWORD 0 */ + u8 rsvd0[27]; /* DWORD 0 */ + u8 CPU_reset; /* DWORD 0 */ +} __packed; +struct EP_CONTROL_CSR_AMAP { + u32 dw[1]; +}; + +/* Semaphore Register. */ +struct BE_EP_SEMAPHORE_CSR_AMAP { + u8 value[32]; /* DWORD 0 */ +} __packed; +struct EP_SEMAPHORE_CSR_AMAP { + u32 dw[1]; +}; + +/* Embedded Processor Specific Registers. */ +struct BE_EP_CSRMAP_AMAP { + struct BE_EP_CONTROL_CSR_AMAP ep_control; + u8 rsvd0[32]; /* DWORD 1 */ + u8 rsvd1[32]; /* DWORD 2 */ + u8 rsvd2[32]; /* DWORD 3 */ + u8 rsvd3[32]; /* DWORD 4 */ + u8 rsvd4[32]; /* DWORD 5 */ + u8 rsvd5[8][128]; /* DWORD 6 */ + u8 rsvd6[32]; /* DWORD 38 */ + u8 rsvd7[32]; /* DWORD 39 */ + u8 rsvd8[32]; /* DWORD 40 */ + u8 rsvd9[32]; /* DWORD 41 */ + u8 rsvd10[32]; /* DWORD 42 */ + struct BE_EP_SEMAPHORE_CSR_AMAP ep_semaphore; + u8 rsvd11[32]; /* DWORD 44 */ + u8 rsvd12[19][32]; /* DWORD 45 */ +} __packed; +struct EP_CSRMAP_AMAP { + u32 dw[64]; +}; + +#endif /* __ep_amap_h__ */ |