diff options
author | Alan Cox <alan@linux.intel.com> | 2009-08-27 11:01:22 +0100 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2009-09-15 12:02:28 -0700 |
commit | e5cf1b75f5675c3169d638f914d1212a5b9071fa (patch) | |
tree | 1158c1e0809f10e1b11a212b209bc36b6bc2d7a0 /drivers/staging/et131x/et1310_address_map.h | |
parent | df482a0916a0ad7473687745e363475e8ce9cd5a (diff) |
Staging: et131x: clean up MMC_SRAM_
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/et131x/et1310_address_map.h')
-rw-r--r-- | drivers/staging/et131x/et1310_address_map.h | 34 |
1 files changed, 8 insertions, 26 deletions
diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index 3f87d3fef78..5abaee918a0 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -2264,7 +2264,7 @@ typedef struct _MAC_STAT_t { /* Location: */ /* START OF MMC REGISTER ADDRESS MAP */ /* - * structure for Main Memory Controller Control reg in mmc address map. + * Main Memory Controller Control reg in mmc address map. * located at address 0x7000 */ @@ -2277,31 +2277,13 @@ typedef struct _MAC_STAT_t { /* Location: */ #define ET_MMC_FORCE_CE 64 /* - * structure for Main Memory Controller Host Memory Access Address reg in mmc - * address map. Located at address 0x7004 + * Main Memory Controller Host Memory Access Address reg in mmc + * address map. Located at address 0x7004. Top 16 bits hold the address bits */ -typedef union _MMC_SRAM_ACCESS_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 byte_enable:16; /* bits 16-31 */ - u32 reserved2:2; /* bits 14-15 */ - u32 req_addr:10; /* bits 4-13 */ - u32 reserved1:1; /* bit 3 */ - u32 is_ctrl_word:1; /* bit 2 */ - u32 wr_access:1; /* bit 1 */ - u32 req_access:1; /* bit 0 */ -#else - u32 req_access:1; /* bit 0 */ - u32 wr_access:1; /* bit 1 */ - u32 is_ctrl_word:1; /* bit 2 */ - u32 reserved1:1; /* bit 3 */ - u32 req_addr:10; /* bits 4-13 */ - u32 reserved2:2; /* bits 14-15 */ - u32 byte_enable:16; /* bits 16-31 */ -#endif - } bits; -} MMC_SRAM_ACCESS_t, *PMMC_SRAM_ACCESS_t; + +#define ET_SRAM_REQ_ACCESS 1 +#define ET_SRAM_WR_ACCESS 2 +#define ET_SRAM_IS_CTRL 4 /* * structure for Main Memory Controller Host Memory Access Data reg in mmc @@ -2314,7 +2296,7 @@ typedef union _MMC_SRAM_ACCESS_t { */ typedef struct _MMC_t { /* Location: */ u32 mmc_ctrl; /* 0x7000 */ - MMC_SRAM_ACCESS_t sram_access; /* 0x7004 */ + u32 sram_access; /* 0x7004 */ u32 sram_word1; /* 0x7008 */ u32 sram_word2; /* 0x700C */ u32 sram_word3; /* 0x7010 */ |