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authorTony Prisk <linux@prisktech.co.nz>2013-01-18 15:05:31 +1300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-01-17 18:54:32 -0800
commit12faa35ae5cbfbd0d90e2103688e87ceb46c5886 (patch)
tree483496c3aab85cb54e0d8d19cba2f814718aa44d /drivers/tty
parent962963e4ee23bc7518dfee754de5f20d35de71d9 (diff)
serial: vt8500: UART uses gated clock rather than 24Mhz reference
UART modules on Wondermedia SoCs are connected via a gated clock source, rather than directly to the 24Mhz reference clock. While uboot enables UART0 for debugging, other UART ports are unavailable until the clock is enabled. This patch checks that a valid clock is actually passed from devicetree, enables the clock in probe. This change removes the fallback when a clock was not specified as it doesn't apply any longer (and would only work if the UART clock was already enabled). DTSI files are updated for VT8500, WM8505 and WM8650. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty')
-rw-r--r--drivers/tty/serial/vt8500_serial.c34
1 files changed, 19 insertions, 15 deletions
diff --git a/drivers/tty/serial/vt8500_serial.c b/drivers/tty/serial/vt8500_serial.c
index ff391db0a22..798bf944a2e 100644
--- a/drivers/tty/serial/vt8500_serial.c
+++ b/drivers/tty/serial/vt8500_serial.c
@@ -584,6 +584,23 @@ static int vt8500_serial_probe(struct platform_device *pdev)
if (!vt8500_port)
return -ENOMEM;
+ vt8500_port->uart.membase = devm_request_and_ioremap(&pdev->dev, mmres);
+ if (!vt8500_port->uart.membase)
+ return -EADDRNOTAVAIL;
+
+ vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
+ if (IS_ERR(vt8500_port->clk)) {
+ dev_err(&pdev->dev, "failed to get clock\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = clk_prepare_enable(vt8500_port->clk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable clock\n");
+ goto err;
+ }
+
vt8500_port->uart.type = PORT_VT8500;
vt8500_port->uart.iotype = UPIO_MEM;
vt8500_port->uart.mapbase = mmres->start;
@@ -593,25 +610,11 @@ static int vt8500_serial_probe(struct platform_device *pdev)
vt8500_port->uart.line = port;
vt8500_port->uart.dev = &pdev->dev;
vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
-
- vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
- if (vt8500_port->clk) {
- vt8500_port->uart.uartclk = clk_get_rate(vt8500_port->clk);
- } else {
- /* use the default of 24Mhz if not specified and warn */
- pr_warn("%s: serial clock source not specified\n", __func__);
- vt8500_port->uart.uartclk = 24000000;
- }
+ vt8500_port->uart.uartclk = clk_get_rate(vt8500_port->clk);
snprintf(vt8500_port->name, sizeof(vt8500_port->name),
"VT8500 UART%d", pdev->id);
- vt8500_port->uart.membase = devm_request_and_ioremap(&pdev->dev, mmres);
- if (!vt8500_port->uart.membase) {
- ret = -EADDRNOTAVAIL;
- goto err;
- }
-
vt8500_uart_ports[port] = vt8500_port;
uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
@@ -630,6 +633,7 @@ static int vt8500_serial_remove(struct platform_device *pdev)
struct vt8500_port *vt8500_port = platform_get_drvdata(pdev);
platform_set_drvdata(pdev, NULL);
+ clk_disable_unprepare(vt8500_port->clk);
uart_remove_one_port(&vt8500_uart_driver, &vt8500_port->uart);
kfree(vt8500_port);