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authorMac Lin <mkl0301@gmail.com>2010-11-25 23:58:00 +0800
committerAnton Vorontsov <cbouatmailru@gmail.com>2010-11-29 18:32:47 +0300
commit760efe6910d5743084b586d3d0a3b65aea96fb2f (patch)
tree7623994cdae2f0fde8dab0bf157b0682a169ec33 /drivers/usb/Kconfig
parentcf36797f35676dafae9d44484391ac7f56b2485a (diff)
USB: cns3xxx: Add EHCI and OHCI bus glue for cns3xxx SOCs
The CNS3XXX SOC has include USB EHCI and OHCI compatible controllers. This patch adds the necessary glue logic to allow ehci-hcd and ohci-hcd drivers to work on CNS3XXX The EHCI and OHCI controllers share a common clock control and reset bit, therefore additional check for the timming of enabling and disabling is required. The USB bit of PLL Power Down Control is also shared by OTG, 24MHzUART clock, Crypto clock, PCIe reference clock, and Clock Scale Generator. Therefore we only ensure it is enabled, while not disabling it. Signed-off-by: Mac Lin <mkl0301@gmail.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>
Diffstat (limited to 'drivers/usb/Kconfig')
-rw-r--r--drivers/usb/Kconfig2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 67eb3770868..5a7c8f1d76c 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -41,6 +41,7 @@ config USB_ARCH_HAS_OHCI
default y if MFD_TC6393XB
default y if ARCH_W90X900
default y if ARCH_DAVINCI_DA8XX
+ default y if ARCH_CNS3XXX
# PPC:
default y if STB03xxx
default y if PPC_MPC52xx
@@ -66,6 +67,7 @@ config USB_ARCH_HAS_EHCI
default y if ARCH_AT91SAM9G45
default y if ARCH_MXC
default y if ARCH_OMAP3
+ default y if ARCH_CNS3XXX
default PCI
# ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.