diff options
| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-02-29 16:49:21 -0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-02-29 16:49:21 -0800 |
| commit | f7c96f59b4af72f51c7835ed073da820bc3786b3 (patch) | |
| tree | 28bcfb3ecd9a913d39ec1ffb407490fc7b5296e0 /drivers/usb/host/ehci-fsl.c | |
| parent | aac1fc386fa13f9f450909fcfb02e73db55f0c0f (diff) | |
Revert "powerpc/usb: fix usb CTRL_PHY_CLK_VALID breaks on some platform"
This reverts commit 79857e8e7b1ba740f8025b540f1e171c9a0a5d31.
To quote Shengzhou Liu:
I'm sorry, please don't apply this patch.
It appears not only on P1022 platform.
There will be more breaks on other platforms regarding
CTRL_PHY_CLK_VALID bit.
I will post a new patch with well compatibility on all
platforms as soon as I get necessary confirmations.
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/host/ehci-fsl.c')
| -rw-r--r-- | drivers/usb/host/ehci-fsl.c | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index e9d8a0cca47..7a15c223575 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -248,11 +248,7 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) struct usb_hcd *hcd = ehci_to_hcd(ehci); struct fsl_usb2_platform_data *pdata; void __iomem *non_ehci = hcd->regs; - u32 temp, chip, rev, svr; - - svr = mfspr(SPRN_SVR); - chip = svr >> 16; - rev = (svr >> 4) & 0xf; + u32 temp; pdata = hcd->self.controller->platform_data; @@ -278,6 +274,12 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0); if (pdata->operating_mode == FSL_USB2_MPH_HOST) { + unsigned int chip, rev, svr; + + svr = mfspr(SPRN_SVR); + chip = svr >> 16; + rev = (svr >> 4) & 0xf; + /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */ if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055)) ehci->has_fsl_port_bug = 1; @@ -299,15 +301,9 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001); } - /* There is no CTRL_PHY_CLK_VALID bit on some platforms, e.g. P1022 */ -#define SVR_P1022_N_ID 0x80E6 -#define SVR_P1022_S_ID 0x80EE - if (chip != SVR_P1022_N_ID && chip != SVR_P1022_S_ID) { - if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & - CTRL_PHY_CLK_VALID)) { - printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n"); - return -ENODEV; - } + if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & CTRL_PHY_CLK_VALID)) { + printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n"); + return -ENODEV; } return 0; } |