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authorNeilBrown <neilb@suse.de>2010-05-22 08:31:36 +1000
committerNeilBrown <neilb@suse.de>2010-05-22 08:31:36 +1000
commit19fdb9eefb21b72edbc365b838502780c392bad6 (patch)
treedeae04c48532d6eab64ed4b0396737bb854b5506 /drivers/usb/musb/musb_regs.h
parentbe6800a73aa2f3dc14744c3b80e676d189789f04 (diff)
parent3ff195b011d7decf501a4d55aeed312731094796 (diff)
Merge commit '3ff195b011d7decf501a4d55aeed312731094796' into for-linus
Conflicts: drivers/md/md.c - Resolved conflict in md_update_sb - Added extra 'NULL' arg to new instance of sysfs_get_dirent. Signed-off-by: NeilBrown <neilb@suse.de>
Diffstat (limited to 'drivers/usb/musb/musb_regs.h')
-rw-r--r--drivers/usb/musb/musb_regs.h40
1 files changed, 39 insertions, 1 deletions
diff --git a/drivers/usb/musb/musb_regs.h b/drivers/usb/musb/musb_regs.h
index 292894a2c24..244267527a6 100644
--- a/drivers/usb/musb/musb_regs.h
+++ b/drivers/usb/musb/musb_regs.h
@@ -75,6 +75,10 @@
/* MUSB ULPI VBUSCONTROL */
#define MUSB_ULPI_USE_EXTVBUS 0x01
#define MUSB_ULPI_USE_EXTVBUSIND 0x02
+/* ULPI_REG_CONTROL */
+#define MUSB_ULPI_REG_REQ (1 << 0)
+#define MUSB_ULPI_REG_CMPLT (1 << 1)
+#define MUSB_ULPI_RDN_WR (1 << 2)
/* TESTMODE */
#define MUSB_TEST_FORCE_HOST 0x80
@@ -251,6 +255,12 @@
/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
#define MUSB_HWVERS 0x6C /* 8 bit */
#define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */
+#define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */
+#define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */
+#define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */
+#define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */
+#define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */
+#define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */
#define MUSB_EPINFO 0x78 /* 8 bit */
#define MUSB_RAMINFO 0x79 /* 8 bit */
@@ -326,6 +336,11 @@ static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
musb_writew(mbase, MUSB_RXFIFOADD, c_off);
}
+static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
+{
+ musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
+}
+
static inline u8 musb_read_txfifosz(void __iomem *mbase)
{
return musb_readb(mbase, MUSB_TXFIFOSZ);
@@ -346,6 +361,11 @@ static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
return musb_readw(mbase, MUSB_RXFIFOADD);
}
+static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
+{
+ return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
+}
+
static inline u8 musb_read_configdata(void __iomem *mbase)
{
musb_writeb(mbase, MUSB_INDEX, 0);
@@ -491,7 +511,7 @@ static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
#define MUSB_FLAT_OFFSET(_epnum, _offset) \
(USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
-/* Not implemented - HW has seperate Tx/Rx FIFO */
+/* Not implemented - HW has separate Tx/Rx FIFO */
#define MUSB_TXCSR_MODE 0x0000
static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
@@ -510,20 +530,33 @@ static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
{
}
+static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
+{
+}
+
static inline u8 musb_read_txfifosz(void __iomem *mbase)
{
+ return 0;
}
static inline u16 musb_read_txfifoadd(void __iomem *mbase)
{
+ return 0;
}
static inline u8 musb_read_rxfifosz(void __iomem *mbase)
{
+ return 0;
}
static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
{
+ return 0;
+}
+
+static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
+{
+ return 0;
}
static inline u8 musb_read_configdata(void __iomem *mbase)
@@ -577,22 +610,27 @@ static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
{
+ return 0;
}
static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
{
+ return 0;
}
static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
{
+ return 0;
}
static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
{
+ return 0;
}
static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
{
+ return 0;
}
static inline void musb_read_txhubport(void __iomem *mbase, u8 epnum)