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authorArchit Taneja <archit@ti.com>2011-01-06 10:44:10 +0530
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-03-11 15:46:27 +0200
commit88134fa138b90518819b750891ffecc13f5f4886 (patch)
tree3a07a522cc2764bcb81dc2b4d83b8468e84295f4 /drivers/video/omap2/dss/dss.c
parent819d807c59af10cce1dcbb13539c2fb100953fcd (diff)
OMAP2PLUS: DSS2: Make members of dss_clk_source generic
The enum members of 'dss_clk_source' have clock source names specific to OMAP2/3. Change the names to more generic terms such that they now describe where the clocks come from and what they are used for. Also, change the enum member names to have "DSS_CLK_SRC" instead of "DSS_SRC" for more clarity. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dss.c')
-rw-r--r--drivers/video/omap2/dss/dss.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 01be82a4f42..998c188c882 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -278,12 +278,12 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
{
int b;
- BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK &&
- clk_src != DSS_SRC_DSS1_ALWON_FCLK);
+ BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC &&
+ clk_src != DSS_CLK_SRC_FCK);
- b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
+ b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
- if (clk_src == DSS_SRC_DSI1_PLL_FCLK)
+ if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)
dsi_wait_dsi1_pll_active();
REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */
@@ -295,12 +295,12 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
{
int b;
- BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK &&
- clk_src != DSS_SRC_DSS1_ALWON_FCLK);
+ BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DSI &&
+ clk_src != DSS_CLK_SRC_FCK);
- b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
+ b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
- if (clk_src == DSS_SRC_DSI2_PLL_FCLK)
+ if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)
dsi_wait_dsi2_pll_active();
REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
@@ -601,8 +601,8 @@ static int dss_init(bool skip_init)
}
}
- dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
- dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK;
+ dss.dsi_clk_source = DSS_CLK_SRC_FCK;
+ dss.dispc_clk_source = DSS_CLK_SRC_FCK;
dss_save_context();