diff options
| author | Florian Tobias Schandinat <FlorianSchandinat@gmx.de> | 2010-07-28 00:57:18 +0000 |
|---|---|---|
| committer | Florian Tobias Schandinat <FlorianSchandinat@gmx.de> | 2010-09-24 02:14:26 +0000 |
| commit | e3812ce4ee43f50a7423de70609f42990039f4ae (patch) | |
| tree | 12ea960d2a59088e5b5f0c78b5a23bbad5f33db9 /drivers/video/via | |
| parent | b4aaa78f4c2f9cde2f335b14f4ca30b01f9651ca (diff) | |
viafb: reset correct PLL
Looks like we did reset the PLL of the (whatever) engine instead of
the PLL of the secondary display (IGA2, LCDCK). This patch fixes it.
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: Joseph Chan <JosephChan@via.com.tw>
Diffstat (limited to 'drivers/video/via')
| -rw-r--r-- | drivers/video/via/hw.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c index 7dcb4d5bb9c..53b06514cd1 100644 --- a/drivers/video/via/hw.c +++ b/drivers/video/via/hw.c @@ -1688,8 +1688,8 @@ void viafb_set_vclock(u32 clk, int set_iga) } if (set_iga == IGA2) { - viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0); - viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0); + viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2); + viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2); } /* Fire! */ |