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authorIwo Mergler <Iwo.Mergler@netcommwireless.com>2012-08-31 08:59:48 +1000
committerDavid Woodhouse <David.Woodhouse@intel.com>2012-09-29 15:46:58 +0100
commit3cf06f4f85aea715e8caf8540760faff2fbf86d6 (patch)
tree23edc4b1b32ac093fb90672b81519f8901b14864 /drivers/zorro
parent7baf04261062826ea225ab23e07c541e279143fa (diff)
mtd: tests: test for multi-bit error correction
This tests ECC biterror recovery on a single NAND page. Mostly intended to test ECC hardware and low-level NAND driver. There are two test modes: 0 - artificially inserting bit errors until the ECC fails This is the default method and fairly quick. It should be independent of the quality of the FLASH. 1 - re-writing the same pattern repeatedly until the ECC fails. This method relies on the physics of NAND FLASH to eventually generate '0' bits if '1' has been written sufficient times. Depending on the NAND, the first bit errors will appear after 1000 or more writes and then will usually snowball, reaching the limits of the ECC quickly. The test stops after 10000 cycles, should your FLASH be exceptionally good and not generate bit errors before that. Try a different page offset in that case. Please note that neither of these tests will significantly 'use up' any FLASH endurance. Only a maximum of two erase operations will be performed. Signed-off-by: Iwo Mergler <Iwo.Mergler@netcommwireless.com.au> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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