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authorLinus Torvalds <torvalds@g5.osdl.org>2005-10-29 12:19:15 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2005-10-29 12:19:15 -0700
commite9d52234e35b27ea4ea5f2ab64ca47b1a0c740ab (patch)
tree318d37a7d55c79e6f7d86163fb28e0eccbb0fe83 /drivers
parent955c5038823748e529a49f0e33ab635d92843500 (diff)
parent09af7b443c257460d45cb6c1896d29f173fef35b (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
Diffstat (limited to 'drivers')
-rw-r--r--drivers/char/lcd.c4
-rw-r--r--drivers/char/lcd.h2
-rw-r--r--drivers/char/qtronix.c5
-rw-r--r--drivers/ide/Kconfig31
-rw-r--r--drivers/ide/ide-proc.c1
-rw-r--r--drivers/ide/mips/au1xxx-ide.c1250
-rw-r--r--drivers/media/video/indycam.c10
-rw-r--r--drivers/media/video/saa7191.c14
-rw-r--r--drivers/media/video/vino.c7
-rw-r--r--drivers/mmc/Kconfig9
-rw-r--r--drivers/mmc/Makefile1
-rw-r--r--drivers/mmc/au1xmmc.c1026
-rw-r--r--drivers/mmc/au1xmmc.h96
-rw-r--r--drivers/pcmcia/Makefile2
-rw-r--r--drivers/pcmcia/au1000_db1x00.c21
-rw-r--r--drivers/pcmcia/au1000_generic.c8
-rw-r--r--drivers/pcmcia/au1000_generic.h4
-rw-r--r--drivers/scsi/dec_esp.c2
-rw-r--r--drivers/tc/tc.c89
-rw-r--r--drivers/tc/zs.c32
-rw-r--r--drivers/video/Kconfig8
-rw-r--r--drivers/video/Makefile2
-rw-r--r--drivers/video/au1100fb.c971
-rw-r--r--drivers/video/au1100fb.h614
-rw-r--r--drivers/video/console/newport_con.c1
-rw-r--r--drivers/video/gbefb.c20
26 files changed, 3335 insertions, 895 deletions
diff --git a/drivers/char/lcd.c b/drivers/char/lcd.c
index b7716114614..29963d8be66 100644
--- a/drivers/char/lcd.c
+++ b/drivers/char/lcd.c
@@ -575,8 +575,8 @@ static inline int button_pressed(void)
static int lcd_waiters = 0;
-static long lcd_read(struct inode *inode, struct file *file, char *buf,
- unsigned long count)
+static ssize_t lcd_read(struct file *file, char *buf,
+ size_t count, loff_t *ofs)
{
long buttons_now;
diff --git a/drivers/char/lcd.h b/drivers/char/lcd.h
index 878a95280e8..a8d4ae73715 100644
--- a/drivers/char/lcd.h
+++ b/drivers/char/lcd.h
@@ -22,7 +22,7 @@ static int timeout(volatile unsigned long);
#define MAX_IDLE_TIME 120
struct lcd_display {
- unsigned long buttons;
+ unsigned buttons;
int size1;
int size2;
unsigned char line1[LCD_CHARS_PER_LINE];
diff --git a/drivers/char/qtronix.c b/drivers/char/qtronix.c
index 40a3cf62e1a..601d09baf9d 100644
--- a/drivers/char/qtronix.c
+++ b/drivers/char/qtronix.c
@@ -591,6 +591,11 @@ static int __init psaux_init(void)
return retval;
queue = (struct aux_queue *) kmalloc(sizeof(*queue), GFP_KERNEL);
+ if (!queue) {
+ misc_deregister(&psaux_mouse);
+ return -ENOMEM;
+ }
+
memset(queue, 0, sizeof(*queue));
queue->head = queue->tail = 0;
init_waitqueue_head(&queue->proc_list);
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index 1cadd2c3cad..a737886e39d 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -778,6 +778,35 @@ config BLK_DEV_IDE_PMAC_BLINK
This option enables the use of the sleep LED as a hard drive
activity LED.
+config BLK_DEV_IDE_AU1XXX
+ bool "IDE for AMD Alchemy Au1200"
+ depends on SOC_AU1200
+choice
+ prompt "IDE Mode for AMD Alchemy Au1200"
+ default CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
+ depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX
+
+config BLK_DEV_IDE_AU1XXX_PIO_DBDMA
+ bool "PIO+DbDMA IDE for AMD Alchemy Au1200"
+
+config BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+ bool "MDMA2+DbDMA IDE for AMD Alchemy Au1200"
+ depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX
+endchoice
+
+config BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
+ bool "Enable burstable Mode on DbDMA"
+ default false
+ depends BLK_DEV_IDE_AU1XXX
+ help
+ This option enable the burstable Flag on DbDMA controller
+ (cf. "AMD Alchemy 'Au1200' Processor Data Book - PRELIMINARY").
+
+config BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ
+ int "Maximum transfer size (KB) per request (up to 128)"
+ default "128"
+ depends BLK_DEV_IDE_AU1XXX
+
config IDE_ARM
def_bool ARM && (ARCH_A5K || ARCH_CLPS7500 || ARCH_RPC || ARCH_SHARK)
@@ -1013,7 +1042,7 @@ config BLK_DEV_UMC8672
endif
config BLK_DEV_IDEDMA
- def_bool BLK_DEV_IDEDMA_PCI || BLK_DEV_IDEDMA_PMAC || BLK_DEV_IDEDMA_ICS
+ def_bool BLK_DEV_IDEDMA_PCI || BLK_DEV_IDEDMA_PMAC || BLK_DEV_IDEDMA_ICS || BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
config IDEDMA_IVB
bool "IGNORE word93 Validation BITS"
diff --git a/drivers/ide/ide-proc.c b/drivers/ide/ide-proc.c
index 4063d2c34e3..84665e2ba3c 100644
--- a/drivers/ide/ide-proc.c
+++ b/drivers/ide/ide-proc.c
@@ -64,6 +64,7 @@ static int proc_ide_read_imodel
case ide_cy82c693: name = "cy82c693"; break;
case ide_4drives: name = "4drives"; break;
case ide_pmac: name = "mac-io"; break;
+ case ide_au1xxx: name = "au1xxx"; break;
default: name = "(unknown)"; break;
}
len = sprintf(page, "%s\n", name);
diff --git a/drivers/ide/mips/au1xxx-ide.c b/drivers/ide/mips/au1xxx-ide.c
new file mode 100644
index 00000000000..2b6327c576b
--- /dev/null
+++ b/drivers/ide/mips/au1xxx-ide.c
@@ -0,0 +1,1250 @@
+/*
+ * linux/drivers/ide/mips/au1xxx-ide.c version 01.30.00 Aug. 02 2005
+ *
+ * BRIEF MODULE DESCRIPTION
+ * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
+ *
+ * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option) any later
+ * version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
+ * Interface and Linux Device Driver" Application Note.
+ */
+#undef REALLY_SLOW_IO /* most systems can safely undef this */
+
+#include <linux/config.h> /* for CONFIG_BLK_DEV_IDEPCI */
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/timer.h>
+#include <linux/mm.h>
+#include <linux/ioport.h>
+#include <linux/hdreg.h>
+#include <linux/init.h>
+#include <linux/ide.h>
+#include <linux/sysdev.h>
+
+#include <linux/dma-mapping.h>
+
+#include <asm/io.h>
+#include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
+
+#if CONFIG_PM
+#include <asm/mach-au1x00/au1xxx_pm.h>
+#endif
+
+#include <asm/mach-au1x00/au1xxx_ide.h>
+
+#define DRV_NAME "au1200-ide"
+#define DRV_VERSION "1.0"
+#define DRV_AUTHOR "AMD PCS / Pete Popov <ppopov@embeddedalley.com>"
+#define DRV_DESC "Au1200 IDE"
+
+static _auide_hwif auide_hwif;
+static spinlock_t ide_tune_drive_spin_lock = SPIN_LOCK_UNLOCKED;
+static spinlock_t ide_tune_chipset_spin_lock = SPIN_LOCK_UNLOCKED;
+static int dbdma_init_done = 0;
+
+/*
+ * local I/O functions
+ */
+u8 auide_inb(unsigned long port)
+{
+ return (au_readb(port));
+}
+
+u16 auide_inw(unsigned long port)
+{
+ return (au_readw(port));
+}
+
+u32 auide_inl(unsigned long port)
+{
+ return (au_readl(port));
+}
+
+void auide_insw(unsigned long port, void *addr, u32 count)
+{
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
+
+ _auide_hwif *ahwif = &auide_hwif;
+ chan_tab_t *ctp;
+ au1x_ddma_desc_t *dp;
+
+ if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
+ DDMA_FLAGS_NOIE)) {
+ printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
+ return;
+ }
+ ctp = *((chan_tab_t **)ahwif->rx_chan);
+ dp = ctp->cur_ptr;
+ while (dp->dscr_cmd0 & DSCR_CMD0_V)
+ ;
+ ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
+#else
+ while (count--)
+ {
+ *(u16 *)addr = au_readw(port);
+ addr +=2 ;
+ }
+#endif
+}
+
+void auide_insl(unsigned long port, void *addr, u32 count)
+{
+ while (count--)
+ {
+ *(u32 *)addr = au_readl(port);
+ /* NOTE: For IDE interfaces over PCMCIA,
+ * 32-bit access does not work
+ */
+ addr += 4;
+ }
+}
+
+void auide_outb(u8 addr, unsigned long port)
+{
+ return (au_writeb(addr, port));
+}
+
+void auide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
+{
+ return (au_writeb(addr, port));
+}
+
+void auide_outw(u16 addr, unsigned long port)
+{
+ return (au_writew(addr, port));
+}
+
+void auide_outl(u32 addr, unsigned long port)
+{
+ return (au_writel(addr, port));
+}
+
+void auide_outsw(unsigned long port, void *addr, u32 count)
+{
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
+ _auide_hwif *ahwif = &auide_hwif;
+ chan_tab_t *ctp;
+ au1x_ddma_desc_t *dp;
+
+ if(!put_source_flags(ahwif->tx_chan, (void*)addr,
+ count << 1, DDMA_FLAGS_NOIE)) {
+ printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
+ return;
+ }
+ ctp = *((chan_tab_t **)ahwif->tx_chan);
+ dp = ctp->cur_ptr;
+ while (dp->dscr_cmd0 & DSCR_CMD0_V)
+ ;
+ ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
+#else
+ while (count--)
+ {
+ au_writew(*(u16 *)addr, port);
+ addr += 2;
+ }
+#endif
+}
+
+void auide_outsl(unsigned long port, void *addr, u32 count)
+{
+ while (count--)
+ {
+ au_writel(*(u32 *)addr, port);
+ /* NOTE: For IDE interfaces over PCMCIA,
+ * 32-bit access does not work
+ */
+ addr += 4;
+ }
+}
+
+static void auide_tune_drive(ide_drive_t *drive, byte pio)
+{
+ int mem_sttime;
+ int mem_stcfg;
+ unsigned long flags;
+ u8 speed;
+
+ /* get the best pio mode for the drive */
+ pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
+
+ printk("%s: setting Au1XXX IDE to PIO mode%d\n",
+ drive->name, pio);
+
+ spin_lock_irqsave(&ide_tune_drive_spin_lock, flags);
+
+ mem_sttime = 0;
+ mem_stcfg = au_readl(MEM_STCFG2);
+
+ /* set pio mode! */
+ switch(pio) {
+ case 0:
+ /* set timing parameters for RCS2# */
+ mem_sttime = SBC_IDE_PIO0_TWCS
+ | SBC_IDE_PIO0_TCSH
+ | SBC_IDE_PIO0_TCSOFF
+ | SBC_IDE_PIO0_TWP
+ | SBC_IDE_PIO0_TCSW
+ | SBC_IDE_PIO0_TPM
+ | SBC_IDE_PIO0_TA;
+ /* set configuration for RCS2# */
+ mem_stcfg |= TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
+
+ au_writel(mem_sttime,MEM_STTIME2);
+ au_writel(mem_stcfg,MEM_STCFG2);
+ break;
+
+ case 1:
+ /* set timing parameters for RCS2# */
+ mem_sttime = SBC_IDE_PIO1_TWCS
+ | SBC_IDE_PIO1_TCSH
+ | SBC_IDE_PIO1_TCSOFF
+ | SBC_IDE_PIO1_TWP
+ | SBC_IDE_PIO1_TCSW
+ | SBC_IDE_PIO1_TPM
+ | SBC_IDE_PIO1_TA;
+ /* set configuration for RCS2# */
+ mem_stcfg |= TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
+ break;
+
+ case 2:
+ /* set timing parameters for RCS2# */
+ mem_sttime = SBC_IDE_PIO2_TWCS
+ | SBC_IDE_PIO2_TCSH
+ | SBC_IDE_PIO2_TCSOFF
+ | SBC_IDE_PIO2_TWP
+ | SBC_IDE_PIO2_TCSW
+ | SBC_IDE_PIO2_TPM
+ | SBC_IDE_PIO2_TA;
+ /* set configuration for RCS2# */
+ mem_stcfg &= ~TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
+ break;
+
+ case 3:
+ /* set timing parameters for RCS2# */
+ mem_sttime = SBC_IDE_PIO3_TWCS
+ | SBC_IDE_PIO3_TCSH
+ | SBC_IDE_PIO3_TCSOFF
+ | SBC_IDE_PIO3_TWP
+ | SBC_IDE_PIO3_TCSW
+ | SBC_IDE_PIO3_TPM
+ | SBC_IDE_PIO3_TA;
+ /* set configuration for RCS2# */
+ mem_stcfg |= TS_MASK;
+ mem_stcfg &= ~TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
+
+ break;
+
+ case 4:
+ /* set timing parameters for RCS2# */
+ mem_sttime = SBC_IDE_PIO4_TWCS
+ | SBC_IDE_PIO4_TCSH
+ | SBC_IDE_PIO4_TCSOFF
+ | SBC_IDE_PIO4_TWP
+ | SBC_IDE_PIO4_TCSW
+ | SBC_IDE_PIO4_TPM
+ | SBC_IDE_PIO4_TA;
+ /* set configuration for RCS2# */
+ mem_stcfg &= ~TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
+ break;
+ }
+
+ au_writel(mem_sttime,MEM_STTIME2);
+ au_writel(mem_stcfg,MEM_STCFG2);
+
+ spin_unlock_irqrestore(&ide_tune_drive_spin_lock, flags);
+
+ speed = pio + XFER_PIO_0;
+ ide_config_drive_speed(drive, speed);
+}
+
+static int auide_tune_chipset (ide_drive_t *drive, u8 speed)
+{
+ u8 mode = 0;
+ int mem_sttime;
+ int mem_stcfg;
+ unsigned long flags;
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+ struct hd_driveid *id = drive->id;
+
+ /*
+ * Now see what the current drive is capable of,
+ * selecting UDMA only if the mate said it was ok.
+ */
+ if (id && (id->capability & 1) && drive->autodma &&
+ !__ide_dma_bad_drive(drive)) {
+ if (!mode && (id->field_valid & 2) && (id->dma_mword & 7)) {
+ if (id->dma_mword & 4)
+ mode = XFER_MW_DMA_2;
+ else if (id->dma_mword & 2)
+ mode = XFER_MW_DMA_1;
+ else if (id->dma_mword & 1)
+ mode = XFER_MW_DMA_0;
+ }
+ }
+#endif
+
+ spin_lock_irqsave(&ide_tune_chipset_spin_lock, flags);
+
+ mem_sttime = 0;
+ mem_stcfg = au_readl(MEM_STCFG2);
+
+ switch(speed) {
+ case XFER_PIO_4:
+ case XFER_PIO_3:
+ case XFER_PIO_2:
+ case XFER_PIO_1:
+ case XFER_PIO_0:
+ auide_tune_drive(drive, (speed - XFER_PIO_0));
+ break;
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+ case XFER_MW_DMA_2:
+ /* set timing parameters for RCS2# */
+ mem_sttime = SBC_IDE_MDMA2_TWCS
+ | SBC_IDE_MDMA2_TCSH
+ | SBC_IDE_MDMA2_TCSOFF
+ | SBC_IDE_MDMA2_TWP
+ | SBC_IDE_MDMA2_TCSW
+ | SBC_IDE_MDMA2_TPM
+ | SBC_IDE_MDMA2_TA;
+ /* set configuration for RCS2# */
+ mem_stcfg &= ~TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
+
+ mode = XFER_MW_DMA_2;
+ break;
+ case XFER_MW_DMA_1:
+ /* set timing parameters for RCS2# */
+ mem_sttime = SBC_IDE_MDMA1_TWCS
+ | SBC_IDE_MDMA1_TCSH
+ | SBC_IDE_MDMA1_TCSOFF
+ | SBC_IDE_MDMA1_TWP
+ | SBC_IDE_MDMA1_TCSW
+ | SBC_IDE_MDMA1_TPM
+ | SBC_IDE_MDMA1_TA;
+ /* set configuration for RCS2# */
+ mem_stcfg &= ~TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
+
+ mode = XFER_MW_DMA_1;
+ break;
+ case XFER_MW_DMA_0:
+ /* set timing parameters for RCS2# */
+ mem_sttime = SBC_IDE_MDMA0_TWCS
+ | SBC_IDE_MDMA0_TCSH
+ | SBC_IDE_MDMA0_TCSOFF
+ | SBC_IDE_MDMA0_TWP
+ | SBC_IDE_MDMA0_TCSW
+ | SBC_IDE_MDMA0_TPM
+ | SBC_IDE_MDMA0_TA;
+ /* set configuration for RCS2# */
+ mem_stcfg |= TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
+
+ mode = XFER_MW_DMA_0;
+ break;
+#endif
+ default:
+ return 1;
+ }
+
+ /*
+ * Tell the drive to switch to the new mode; abort on failure.
+ */
+ if (!mode || ide_config_drive_speed(drive, mode))
+ {
+ return 1; /* failure */
+ }
+
+
+ au_writel(mem_sttime,MEM_STTIME2);
+ au_writel(mem_stcfg,MEM_STCFG2);
+
+ spin_unlock_irqrestore(&ide_tune_chipset_spin_lock, flags);
+
+ return 0;
+}
+
+/*
+ * Multi-Word DMA + DbDMA functions
+ */
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+
+static int in_drive_list(struct hd_driveid *id,
+ const struct drive_list_entry *drive_table)
+{
+ for ( ; drive_table->id_model ; drive_table++){
+ if ((!strcmp(drive_table->id_model, id->model)) &&
+ ((strstr(drive_table->id_firmware, id->fw_rev)) ||
+ (!strcmp(drive_table->id_firmware, "ALL")))
+ )
+ return 1;
+ }
+ return 0;
+}
+
+static int auide_build_sglist(ide_drive_t *drive, struct request *rq)
+{
+ ide_hwif_t *hwif = drive->hwif;
+ _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
+ struct scatterlist *sg = hwif->sg_table;
+
+ ide_map_sg(drive, rq);
+
+ if (rq_data_dir(rq) == READ)
+ hwif->sg_dma_direction = DMA_FROM_DEVICE;
+ else
+ hwif->sg_dma_direction = DMA_TO_DEVICE;
+
+ return dma_map_sg(ahwif->dev, sg, hwif->sg_nents,
+ hwif->sg_dma_direction);
+}
+
+static int auide_build_dmatable(ide_drive_t *drive)
+{
+ int i, iswrite, count = 0;
+ ide_hwif_t *hwif = HWIF(drive);
+
+ struct request *rq = HWGROUP(drive)->rq;
+
+ _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
+ struct scatterlist *sg;
+
+ iswrite = (rq_data_dir(rq) == WRITE);
+ /* Save for interrupt context */
+ ahwif->drive = drive;
+
+ /* Build sglist */
+ hwif->sg_nents = i = auide_build_sglist(drive, rq);
+
+ if (!i)
+ return 0;
+
+ /* fill the descriptors */
+ sg = hwif->sg_table;
+ while (i && sg_dma_len(sg)) {
+ u32 cur_addr;
+ u32 cur_len;
+
+ cur_addr = sg_dma_address(sg);
+ cur_len = sg_dma_len(sg);
+
+ while (cur_len) {
+ u32 flags = DDMA_FLAGS_NOIE;
+ unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
+
+ if (++count >= PRD_ENTRIES) {
+ printk(KERN_WARNING "%s: DMA table too small\n",
+ drive->name);
+ goto use_pio_instead;
+ }
+
+ /* Lets enable intr for the last descriptor only */
+ if (1==i)
+ flags = DDMA_FLAGS_IE;
+ else
+ flags = DDMA_FLAGS_NOIE;
+
+ if (iswrite) {
+ if(!put_source_flags(ahwif->tx_chan,
+ (void*)(page_address(sg->page)
+ + sg->offset),
+ tc, flags)) {
+ printk(KERN_ERR "%s failed %d\n",
+ __FUNCTION__, __LINE__);
+ }
+ } else
+ {
+ if(!put_dest_flags(ahwif->rx_chan,
+ (void*)(page_address(sg->page)
+ + sg->offset),
+ tc, flags)) {
+ printk(KERN_ERR "%s failed %d\n",
+ __FUNCTION__, __LINE__);
+ }
+ }
+
+ cur_addr += tc;
+ cur_len -= tc;
+ }
+ sg++;
+ i--;
+ }
+
+ if (count)
+ return 1;
+
+use_pio_instead:
+ dma_unmap_sg(ahwif->dev,
+ hwif->sg_table,
+ hwif->sg_nents,
+ hwif->sg_dma_direction);
+
+ return 0; /* revert to PIO for this request */
+}
+
+static int auide_dma_end(ide_drive_t *drive)
+{
+ ide_hwif_t *hwif = HWIF(drive);
+ _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
+
+ if (hwif->sg_nents) {
+ dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents,
+ hwif->sg_dma_direction);
+ hwif->sg_nents = 0;
+ }
+
+ return 0;
+}
+
+static void auide_dma_start(ide_drive_t *drive )
+{
+// printk("%s\n", __FUNCTION__);
+}
+
+ide_startstop_t auide_dma_intr(ide_drive_t *drive)
+{
+ //printk("%s\n", __FUNCTION__);
+
+ u8 stat = 0, dma_stat = 0;
+
+ dma_stat = HWIF(drive)->ide_dma_end(drive);
+ stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */
+ if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
+ if (!dma_stat) {
+ struct request *rq = HWGROUP(drive)->rq;
+
+ ide_end_request(drive, 1, rq->nr_sectors);
+ return ide_stopped;
+ }
+ printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n",
+ drive->name, dma_stat);
+ }
+ return ide_error(drive, "dma_intr", stat);
+}
+
+static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
+{
+ //printk("%s\n", __FUNCTION__);
+
+ /* issue cmd to drive */
+ ide_execute_command(drive, command, &auide_dma_intr,
+ (2*WAIT_CMD), NULL);
+}
+
+static int auide_dma_setup(ide_drive_t *drive)
+{
+// printk("%s\n", __FUNCTION__);
+
+ if (drive->media != ide_disk)
+ return 1;
+
+ if (!auide_build_dmatable(drive))
+ /* try PIO instead of DMA */
+ return 1;
+
+ drive->waiting_for_dma = 1;
+
+ return 0;
+}
+
+static int auide_dma_check(ide_drive_t *drive)
+{
+// printk("%s\n", __FUNCTION__);
+
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+ if( !dbdma_init_done ){
+ auide_hwif.white_list = in_drive_list(drive->id,
+ dma_white_list);
+ auide_hwif.black_list = in_drive_list(drive->id,
+ dma_black_list);
+ auide_hwif.drive = drive;
+ auide_ddma_init(&auide_hwif);
+ dbdma_init_done = 1;
+ }
+#endif
+
+ /* Is the drive in our DMA black list? */
+ if ( auide_hwif.black_list ) {
+ drive->using_dma = 0;
+ printk("%s found in dma_blacklist[]! Disabling DMA.\n",
+ drive->id->model);
+ }
+ else
+ drive->using_dma = 1;
+
+ return HWIF(drive)->ide_dma_host_on(drive);
+}
+
+static int auide_dma_test_irq(ide_drive_t *drive)
+{
+// printk("%s\n", __FUNCTION__);
+
+ if (!drive->waiting_for_dma)
+ printk(KERN_WARNING "%s: ide_dma_test_irq \
+ called while not waiting\n", drive->name);
+
+ /* If dbdma didn't execute the STOP command yet, the
+ * active bit is still set
+ */
+ drive->waiting_for_dma++;
+ if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
+ printk(KERN_WARNING "%s: timeout waiting for ddma to \
+ complete\n", drive->name);
+ return 1;
+ }
+ udelay(10);
+ return 0;
+}
+
+static int auide_dma_host_on(ide_drive_t *drive)
+{
+// printk("%s\n", __FUNCTION__);
+ return 0;
+}
+
+static int auide_dma_on(ide_drive_t *drive)
+{
+// printk("%s\n", __FUNCTION__);
+ drive->using_dma = 1;
+ return auide_dma_host_on(drive);
+}
+
+
+static int auide_dma_host_off(ide_drive_t *drive)
+{
+// printk("%s\n", __FUNCTION__);
+ return 0;
+}
+
+static int auide_dma_off_quietly(ide_drive_t *drive)
+{
+// printk("%s\n", __FUNCTION__);
+ drive->using_dma = 0;
+ return auide_dma_host_off(drive);
+}
+
+static int auide_dma_lostirq(ide_drive_t *drive)
+{
+// printk("%s\n", __FUNCTION__);
+
+ printk(KERN_ERR "%s: IRQ lost\n", drive->name);
+ return 0;
+}
+
+static void auide_ddma_tx_callback(int irq, void *param, struct pt_regs *regs)
+{
+// printk("%s\n", __FUNCTION__);
+
+ _auide_hwif *ahwif = (_auide_hwif*)param;
+ ahwif->drive->waiting_for_dma = 0;
+ return;
+}
+
+static void auide_ddma_rx_callback(int irq, void *param, struct pt_regs *regs)
+{
+// printk("%s\n", __FUNCTION__);
+
+ _auide_hwif *ahwif = (_auide_hwif*)param;
+ ahwif->drive->waiting_for_dma = 0;
+ return;
+}
+
+static int auide_dma_timeout(ide_drive_t *drive)
+{
+// printk("%s\n", __FUNCTION__);
+
+ printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
+
+ if (HWIF(drive)->ide_dma_test_irq(drive))
+ return 0;
+
+ return HWIF(drive)->ide_dma_end(drive);
+}
+#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
+
+
+static int auide_ddma_init( _auide_hwif *auide )
+{
+// printk("%s\n", __FUNCTION__);
+
+ dbdev_tab_t source_dev_tab;
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
+ dbdev_tab_t target_dev_tab;
+ ide_hwif_t *hwif = auide->hwif;
+ char warning_output [2][80];
+ int i;
+#endif
+
+ /* Add our custom device to DDMA device table */
+ /* Create our new device entries in the table */
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
+ source_dev_tab.dev_id = AU1XXX_ATA_DDMA_REQ;
+
+ if( auide->white_list || auide->black_list ){
+ source_dev_tab.dev_tsize = 8;
+ source_dev_tab.dev_devwidth = 32;
+ source_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
+ source_dev_tab.dev_intlevel = 0;
+ source_dev_tab.dev_intpolarity = 0;
+
+ /* init device table for target - static bus controller - */
+ target_dev_tab.dev_id = DSCR_CMD0_ALWAYS;
+ target_dev_tab.dev_tsize = 8;
+ target_dev_tab.dev_devwidth = 32;
+ target_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
+ target_dev_tab.dev_intlevel = 0;
+ target_dev_tab.dev_intpolarity = 0;
+ target_dev_tab.dev_flags = DEV_FLAGS_ANYUSE;
+ }
+ else{
+ source_dev_tab.dev_tsize = 1;
+ source_dev_tab.dev_devwidth = 16;
+ source_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
+ source_dev_tab.dev_intlevel = 0;
+ source_dev_tab.dev_intpolarity = 0;
+
+ /* init device table for target - static bus controller - */
+ target_dev_tab.dev_id = DSCR_CMD0_ALWAYS;
+ target_dev_tab.dev_tsize = 1;
+ target_dev_tab.dev_devwidth = 16;
+ target_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
+ target_dev_tab.dev_intlevel = 0;
+ target_dev_tab.dev_intpolarity = 0;
+ target_dev_tab.dev_flags = DEV_FLAGS_ANYUSE;
+
+ sprintf(&warning_output[0][0],
+ "%s is not on ide driver white list.",
+ auide_hwif.drive->id->model);
+ for ( i=strlen(&warning_output[0][0]) ; i<76; i++ ){
+ sprintf(&warning_output[0][i]," ");
+ }
+
+ sprintf(&warning_output[1][0],
+ "To add %s please read 'Documentation/mips/AU1xxx_IDE.README'.",
+ auide_hwif.drive->id->model);
+ for ( i=strlen(&warning_output[1][0]) ; i<76; i++ ){
+ sprintf(&warning_output[1][i]," ");
+ }
+
+ printk("\n****************************************");
+ printk("****************************************\n");
+ printk("* %s *\n",&warning_output[0][0]);
+ printk("* Switch to safe MWDMA Mode! ");
+ printk(" *\n");
+ printk("* %s *\n",&warning_output[1][0]);
+ printk("****************************************");
+ printk("****************************************\n\n");
+ }
+#else
+ source_dev_tab.dev_id = DSCR_CMD0_ALWAYS;
+ source_dev_tab.dev_tsize = 8;
+ source_dev_tab.dev_devwidth = 32;
+ source_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
+ source_dev_tab.dev_intlevel = 0;
+ source_dev_tab.dev_intpolarity = 0;
+#endif
+
+#if CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
+ /* set flags for tx channel */
+ source_dev_tab.dev_flags = DEV_FLAGS_OUT
+ | DEV_FLAGS_SYNC
+ | DEV_FLAGS_BURSTABLE;
+ auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
+ /* set flags for rx channel */
+ source_dev_tab.dev_flags = DEV_FLAGS_IN
+ | DEV_FLAGS_SYNC
+ | DEV_FLAGS_BURSTABLE;
+ auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
+#else
+ /* set flags for tx channel */
+ source_dev_tab.dev_flags = DEV_FLAGS_OUT | DEV_FLAGS_SYNC;
+ auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
+ /* set flags for rx channel */
+ source_dev_tab.dev_flags = DEV_FLAGS_IN | DEV_FLAGS_SYNC;
+ auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
+#endif
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
+
+ auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
+
+ /* Get a channel for TX */
+ auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
+ auide->tx_dev_id,
+ auide_ddma_tx_callback,
+ (void*)auide);
+ /* Get a channel for RX */
+ auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
+ auide->target_dev_id,
+ auide_ddma_rx_callback,
+ (void*)auide);
+#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
+ /*
+ * Note: if call back is not enabled, update ctp->cur_ptr manually
+ */
+ auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
+ auide->tx_dev_id,
+ NULL,
+ (void*)auide);
+ auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
+ DSCR_CMD0_ALWAYS,
+ NULL,
+ (void*)auide);
+#endif
+ auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
+ NUM_DESCRIPTORS);
+ auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
+ NUM_DESCRIPTORS);
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
+ hwif->dmatable_cpu = dma_alloc_coherent(auide->dev,
+ PRD_ENTRIES * PRD_BYTES, /* 1 Page */
+ &hwif->dmatable_dma, GFP_KERNEL);
+
+ auide->sg_table = kmalloc(sizeof(struct scatterlist) * PRD_ENTRIES,
+ GFP_KERNEL|GFP_DMA);
+ if (auide->sg_table == NULL) {
+ return -ENOMEM;
+ }
+#endif
+ au1xxx_dbdma_start( auide->tx_chan );
+ au1xxx_dbdma_start( auide->rx_chan );
+ return 0;
+}
+
+static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
+{
+ int i;
+#define ide_ioreg_t unsigned long
+ ide_ioreg_t *ata_regs = hw->io_ports;
+
+ /* fixme */
+ for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
+ *ata_regs++ = (ide_ioreg_t) ahwif->regbase
+ + (ide_ioreg_t)(i << AU1XXX_ATA_REG_OFFSET);
+ }
+
+ /* set the Alternative Status register */
+ *ata_regs = (ide_ioreg_t) ahwif->regbase
+ + (ide_ioreg_t)(14 << AU1XXX_ATA_REG_OFFSET);
+}
+
+static int au_ide_probe(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ _auide_hwif *ahwif = &auide_hwif;
+ ide_hwif_t *hwif;
+ struct resource *res;
+ int ret = 0;
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
+ char *mode = "MWDMA2";
+#elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
+ char *mode = "PIO+DDMA(offload)";
+#endif
+
+ memset(&auide_hwif, 0, sizeof(_auide_hwif));
+ auide_hwif.dev = 0;
+
+ ahwif->dev = dev;
+ ahwif->irq = platform_get_irq(pdev, 0);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ if (res == NULL) {
+ pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
+ ret = -ENODEV;
+ goto out;
+ }
+
+ if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
+ pr_debug("%s: request_mem_region failed\n", DRV_NAME);
+ ret = -EBUSY;
+ goto out;
+ }
+
+ ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
+ if (ahwif->regbase == 0) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ hwif = &ide_hwifs[pdev->id];
+ hw_regs_t *hw = &hwif->hw;
+ hwif->irq = hw->irq = ahwif->irq;
+ hwif->chipset = ide_au1xxx;
+
+ auide_setup_ports(hw, ahwif);
+ memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
+
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ
+ hwif->rqsize = CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ;
+ hwif->rqsize = ((hwif->rqsize > AU1XXX_ATA_RQSIZE)
+ || (hwif->rqsize < 32)) ? AU1XXX_ATA_RQSIZE : hwif->rqsize;
+#else /* if kernel config is not set */
+ hwif->rqsize = AU1XXX_ATA_RQSIZE;
+#endif
+
+ hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+ hwif->mwdma_mask = 0x07; /* Multimode-2 DMA */
+ hwif->swdma_mask = 0x07;
+#else
+ hwif->mwdma_mask = 0x0;
+ hwif->swdma_mask = 0x0;
+#endif
+ //hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
+ hwif->noprobe = 0;
+ hwif->drives[0].unmask = 1;
+ hwif->drives[1].unmask = 1;
+
+ /* hold should be on in all cases */
+ hwif->hold = 1;
+ hwif->mmio = 2;
+
+ /* set up local I/O function entry points */
+ hwif->INB = auide_inb;
+ hwif->INW = auide_inw;
+ hwif->INL = auide_inl;
+ hwif->INSW = auide_insw;
+ hwif->INSL = auide_insl;
+ hwif->OUTB = auide_outb;
+ hwif->OUTBSYNC = auide_outbsync;
+ hwif->OUTW = auide_outw;
+ hwif->OUTL = auide_outl;
+ hwif->OUTSW = auide_outsw;
+ hwif->OUTSL = auide_outsl;
+
+ hwif->tuneproc = &auide_tune_drive;
+ hwif->speedproc = &auide_tune_chipset;
+
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+ hwif->ide_dma_off_quietly = &auide_dma_off_quietly;
+ hwif->ide_dma_timeout = &auide_dma_timeout;
+
+ hwif->ide_dma_check = &auide_dma_check;
+ hwif->dma_exec_cmd = &auide_dma_exec_cmd;
+ hwif->dma_start = &auide_dma_start;
+ hwif->ide_dma_end = &auide_dma_end;
+ hwif->dma_setup = &auide_dma_setup;
+ hwif->ide_dma_test_irq = &auide_dma_test_irq;
+ hwif->ide_dma_host_off = &auide_dma_host_off;
+ hwif->ide_dma_host_on = &auide_dma_host_on;
+ hwif->ide_dma_lostirq = &auide_dma_lostirq;
+ hwif->ide_dma_on = &auide_dma_on;
+
+ hwif->autodma = 1;
+ hwif->drives[0].autodma = hwif->autodma;
+ hwif->drives[1].autodma = hwif->autodma;
+ hwif->atapi_dma = 1;
+ hwif->drives[0].using_dma = 1;
+ hwif->drives[1].using_dma = 1;
+#else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
+ hwif->autodma = 0;
+ hwif->channel = 0;
+ hwif->hold = 1;
+ hwif->select_data = 0; /* no chipset-specific code */
+ hwif->config_data = 0; /* no chipset-specific code */
+
+ hwif->drives[0].autodma = 0;
+ hwif->drives[0].drive_data = 0; /* no drive data */
+ hwif->drives[0].using_dma = 0;
+ hwif->drives[0].waiting_for_dma = 0;
+ hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */
+ /* secondary hdd not supported */
+ hwif->drives[1].autodma = 0;
+
+ hwif->drives[1].drive_data = 0;
+ hwif->drives[1].using_dma = 0;
+ hwif->drives[1].waiting_for_dma = 0;
+ hwif->drives[1].autotune = 2; /* 1=autotune, 2=noautotune, 0=default */
+#endif
+ hwif->drives[0].io_32bit = 0; /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */
+ hwif->drives[1].io_32bit = 0; /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */
+
+ /*Register Driver with PM Framework*/
+#ifdef CONFIG_PM
+ auide_hwif.pm.lock = SPIN_LOCK_UNLOCKED;
+ auide_hwif.pm.stopped = 0;
+
+ auide_hwif.pm.dev = new_au1xxx_power_device( "ide",
+ &au1200ide_pm_callback,
+ NULL);
+ if ( auide_hwif.pm.dev == NULL )
+ printk(KERN_INFO "Unable to create a power management \
+ device entry for the au1200-IDE.\n");
+ else
+ printk(KERN_INFO "Power management device entry for the \
+ au1200-IDE loaded.\n");
+#endif
+
+ auide_hwif.hwif = hwif;
+ hwif->hwif_data = &auide_hwif;
+
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
+ auide_ddma_init(&auide_hwif);
+ dbdma_init_done = 1;
+#endif
+
+ probe_hwif_init(hwif);
+ dev_set_drvdata(dev, hwif);
+
+ printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
+
+out:
+ return ret;
+}
+
+static int au_ide_remove(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct resource *res;
+ ide_hwif_t *hwif = dev_get_drvdata(dev);
+ _auide_hwif *ahwif = &auide_hwif;
+
+ ide_unregister(hwif - ide_hwifs);
+
+ iounmap((void *)ahwif->regbase);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ release_mem_region(res->start, res->end - res->start);
+
+ return 0;
+}
+
+static struct device_driver au1200_ide_driver = {
+ .name = "au1200-ide",
+ .bus = &platform_bus_type,
+ .probe = au_ide_probe,
+ .remove = au_ide_remove,
+};
+
+static int __init au_ide_init(void)
+{
+ return driver_register(&au1200_ide_driver);
+}
+
+static void __init au_ide_exit(void)
+{
+ driver_unregister(&au1200_ide_driver);
+}
+
+#ifdef CONFIG_PM
+int au1200ide_pm_callback( au1xxx_power_dev_t *dev,\
+ au1xxx_request_t request, void *data) {
+
+ unsigned int d, err = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(auide_hwif.pm.lock, flags);
+
+ switch (request){
+ case AU1XXX_PM_SLEEP:
+ err = au1xxxide_pm_sleep(dev);
+ break;
+ case AU1XXX_PM_WAKEUP:
+ d = *((unsigned int*)data);
+ if ( d > 0 && d <= 99) {
+ err = au1xxxide_pm_standby(dev);
+ }
+ else {
+ err = au1xxxide_pm_resume(dev);
+ }
+ break;
+ case AU1XXX_PM_GETSTATUS:
+ err = au1xxxide_pm_getstatus(dev);
+ break;
+ case AU1XXX_PM_ACCESS:
+ err = au1xxxide_pm_access(dev);
+ break;
+ case AU1XXX_PM_IDLE:
+ err = au1xxxide_pm_idle(dev);
+ break;
+ case AU1XXX_PM_CLEANUP:
+ err = au1xxxide_pm_cleanup(dev);
+ break;
+ default:
+ err = -1;
+ break;
+ }
+
+ spin_unlock_irqrestore(auide_hwif.pm.lock, flags);
+
+ return err;
+}
+
+static int au1xxxide_pm_standby( au1xxx_power_dev_t *dev ) {
+ return 0;
+}
+
+static int au1xxxide_pm_sleep( au1xxx_power_dev_t *dev ) {
+
+ int retval;
+ ide_hwif_t *hwif = auide_hwif.hwif;
+ struct request rq;
+ struct request_pm_state rqpm;
+ ide_task_t args;
+
+ if(auide_hwif.pm.stopped)
+ return -1;
+
+ /*
+ * wait until hard disc is ready
+ */
+ if ( wait_for_ready(&hwif->drives[0], 35000) ) {
+ printk("Wait for drive sleep timeout!\n");
+ retval = -1;
+ }
+
+ /*
+ * sequenz to tell the high level ide driver that pm is resuming
+ */
+ memset(&rq, 0, sizeof(rq));
+ memset(&rqpm, 0, sizeof(rqpm));
+ memset(&args, 0, sizeof(args));
+ rq.flags = REQ_PM_SUSPEND;
+ rq.special = &args;
+ rq.pm = &rqpm;
+ rqpm.pm_step = ide_pm_state_start_suspend;
+ rqpm.pm_state = PMSG_SUSPEND;
+
+ retval = ide_do_drive_cmd(&hwif->drives[0], &rq, ide_wait);
+
+ if (wait_for_ready (&hwif->drives[0], 35000)) {
+ printk("Wait for drive sleep timeout!\n");
+ retval = -1;
+ }
+
+ /*
+ * stop dbdma channels
+ */
+ au1xxx_dbdma_reset(auide_hwif.tx_chan);
+ au1xxx_dbdma_reset(auide_hwif.rx_chan);
+
+ auide_hwif.pm.stopped = 1;
+
+ return retval;
+}
+
+static int au1xxxide_pm_resume( au1xxx_power_dev_t *dev ) {
+
+ int retval;
+ ide_hwif_t *hwif = auide_hwif.hwif;
+ struct request rq;
+ struct request_pm_state rqpm;
+ ide_task_t args;
+
+ if(!auide_hwif.pm.stopped)
+ return -1;
+
+ /*
+ * start dbdma channels
+ */
+ au1xxx_dbdma_start(auide_hwif.tx_chan);
+ au1xxx_dbdma_start(auide_hwif.rx_chan);
+
+ /*
+ * wait until hard disc is ready
+ */
+ if (wait_for_ready ( &hwif->drives[0], 35000)) {
+ printk("Wait for drive wake up timeout!\n");
+ retval = -1;
+ }
+
+ /*
+ * sequenz to tell the high level ide driver that pm is resuming
+ */
+ memset(&rq, 0, sizeof(rq));
+ memset(&rqpm, 0, sizeof(rqpm));
+ memset(&args, 0, sizeof(args));
+ rq.flags = REQ_PM_RESUME;
+ rq.special = &args;
+ rq.pm = &rqpm;
+ rqpm.pm_step = ide_pm_state_start_resume;
+ rqpm.pm_state = PMSG_ON;
+
+ retval = ide_do_drive_cmd(&hwif->drives[0], &rq, ide_head_wait);
+
+ /*
+ * wait for hard disc
+ */
+ if ( wait_for_ready(&hwif->drives[0], 35000) ) {
+ printk("Wait for drive wake up timeout!\n");
+ retval = -1;
+ }
+
+ auide_hwif.pm.stopped = 0;
+
+ return retval;
+}
+
+static int au1xxxide_pm_getstatus( au1xxx_power_dev_t *dev ) {
+ return dev->cur_state;
+}
+
+static int au1xxxide_pm_access( au1xxx_power_dev_t *dev ) {
+ if (dev->cur_state != AWAKE_STATE)
+ return 0;
+ else
+ return -1;
+}
+
+static int au1xxxide_pm_idle( au1xxx_power_dev_t *dev ) {
+ return 0;
+}
+
+static int au1xxxide_pm_cleanup( au1xxx_power_dev_t *dev ) {
+ return 0;
+}
+#endif /* CONFIG_PM */
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("AU1200 IDE driver");
+
+module_init(au_ide_init);
+module_exit(au_ide_exit);
diff --git a/drivers/media/video/indycam.c b/drivers/media/video/indycam.c
index b2b0384cd4b..26dd06ec89a 100644
--- a/drivers/media/video/indycam.c
+++ b/drivers/media/video/indycam.c
@@ -9,16 +9,16 @@
* published by the Free Software Foundation.
*/
-#include <linux/module.h>
-#include <linux/init.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fs.h>
+#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/major.h>
-#include <linux/slab.h>
+#include <linux/module.h>
#include <linux/mm.h>
#include <linux/sched.h>
+#include <linux/slab.h>
#include <linux/videodev.h>
/* IndyCam decodes stream of photons into digital image representation ;-) */
@@ -44,8 +44,6 @@ MODULE_LICENSE("GPL");
#define indycam_regdump(client)
#endif
-#define VINO_ADAPTER (I2C_ALGO_SGI | I2C_HW_SGI_VINO)
-
struct indycam {
struct i2c_client *client;
int version;
@@ -300,7 +298,7 @@ out_free_client:
static int indycam_probe(struct i2c_adapter *adap)
{
/* Indy specific crap */
- if (adap->id == VINO_ADAPTER)
+ if (adap->id == I2C_HW_SGI_VINO)
return indycam_attach(adap, INDYCAM_ADDR, 0);
/* Feel free to add probe here :-) */
return -ENODEV;
diff --git a/drivers/media/video/saa7191.c b/drivers/media/video/saa7191.c
index 454f5c1199b..3ddbb62312b 100644
--- a/drivers/media/video/saa7191.c
+++ b/drivers/media/video/saa7191.c
@@ -9,16 +9,16 @@
* published by the Free Software Foundation.
*/
-#include <linux/module.h>
-#include <linux/init.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fs.h>
+#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/major.h>
-#include <linux/slab.h>
+#include <linux/module.h>
#include <linux/mm.h>
#include <linux/sched.h>
+#include <linux/slab.h>
#include <linux/videodev.h>
#include <linux/video_decoder.h>
@@ -33,8 +33,6 @@ MODULE_VERSION(SAA7191_MODULE_VERSION);
MODULE_AUTHOR("Mikael Nousiainen <tmnousia@cc.hut.fi>");
MODULE_LICENSE("GPL");
-#define VINO_ADAPTER (I2C_ALGO_SGI | I2C_HW_SGI_VINO)
-
struct saa7191 {
struct i2c_client *client;
@@ -337,7 +335,7 @@ out_free_client:
static int saa7191_probe(struct i2c_adapter *adap)
{
/* Always connected to VINO */
- if (adap->id == VINO_ADAPTER)
+ if (adap->id == I2C_HW_SGI_VINO)
return saa7191_attach(adap, SAA7191_ADDR, 0);
/* Feel free to add probe here :-) */
return -ENODEV;
@@ -364,7 +362,7 @@ static int saa7191_command(struct i2c_client *client, unsigned int cmd,
cap->flags = VIDEO_DECODER_PAL | VIDEO_DECODER_NTSC |
VIDEO_DECODER_SECAM | VIDEO_DECODER_AUTO;
- cap->inputs = (client->adapter->id == VINO_ADAPTER) ? 2 : 1;
+ cap->inputs = (client->adapter->id == I2C_HW_SGI_VINO) ? 2 : 1;
cap->outputs = 1;
break;
}
@@ -422,7 +420,7 @@ static int saa7191_command(struct i2c_client *client, unsigned int cmd,
int *iarg = arg;
switch (client->adapter->id) {
- case VINO_ADAPTER:
+ case I2C_HW_SGI_VINO:
return saa7191_set_input(client, *iarg);
default:
if (*iarg != 0)
diff --git a/drivers/media/video/vino.c b/drivers/media/video/vino.c
index d8a0f763ca1..ed4394e854a 100644
--- a/drivers/media/video/vino.c
+++ b/drivers/media/video/vino.c
@@ -26,14 +26,15 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/delay.h>
+#include <linux/dma-mapping.h>
#include <linux/errno.h>
#include <linux/fs.h>
+#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/dma-mapping.h>
-#include <linux/time.h>
#include <linux/moduleparam.h>
+#include <linux/time.h>
+#include <linux/version.h>
#ifdef CONFIG_KMOD
#include <linux/kmod.h>
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 4991bbd054f..c483a863b11 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -60,4 +60,13 @@ config MMC_WBSD
If unsure, say N.
+config MMC_AU1X
+ tristate "Alchemy AU1XX0 MMC Card Interface support"
+ depends on SOC_AU1X00 && MMC
+ help
+ This selects the AMD Alchemy(R) Multimedia card interface.
+ iIf you have a Alchemy platform with a MMC slot, say Y or M here.
+
+ If unsure, say N.
+
endmenu
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 89510c2086c..e351e71146e 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_MMC_BLOCK) += mmc_block.o
obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
obj-$(CONFIG_MMC_PXA) += pxamci.o
obj-$(CONFIG_MMC_WBSD) += wbsd.o
+obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
mmc_core-y := mmc.o mmc_queue.o mmc_sysfs.o
diff --git a/drivers/mmc/au1xmmc.c b/drivers/mmc/au1xmmc.c
new file mode 100644
index 00000000000..aaf04638054
--- /dev/null
+++ b/drivers/mmc/au1xmmc.c
@@ -0,0 +1,1026 @@
+/*
+ * linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver
+ *
+ * Copyright (c) 2005, Advanced Micro Devices, Inc.
+ *
+ * Developed with help from the 2.4.30 MMC AU1XXX controller including
+ * the following copyright notices:
+ * Copyright (c) 2003-2004 Embedded Edge, LLC.
+ * Portions Copyright (C) 2002 Embedix, Inc
+ * Copyright 2002 Hewlett-Packard Company
+
+ * 2.6 version of this driver inspired by:
+ * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
+ * All Rights Reserved.
+ * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
+ * All Rights Reserved.
+ *
+
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* Why is a timer used to detect insert events?
+ *
+ * From the AU1100 MMC application guide:
+ * If the Au1100-based design is intended to support both MultiMediaCards
+ * and 1- or 4-data bit SecureDigital cards, then the solution is to
+ * connect a weak (560KOhm) pull-up resistor to connector pin 1.
+ * In doing so, a MMC card never enters SPI-mode communications,
+ * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
+ * (the low to high transition will not occur).
+ *
+ * So we use the timer to check the status manually.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+
+#include <linux/mmc/host.h>
+#include <linux/mmc/protocol.h>
+#include <asm/io.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
+#include <asm/mach-au1x00/au1100_mmc.h>
+#include <asm/scatterlist.h>
+
+#include <au1xxx.h>
+#include "au1xmmc.h"
+
+#define DRIVER_NAME "au1xxx-mmc"
+
+/* Set this to enable special debugging macros */
+/* #define MMC_DEBUG */
+
+#ifdef MMC_DEBUG
+#define DEBUG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
+#else
+#define DEBUG(fmt, idx, args...)
+#endif
+
+const struct {
+ u32 iobase;
+ u32 tx_devid, rx_devid;
+ u16 bcsrpwr;
+ u16 bcsrstatus;
+ u16 wpstatus;
+} au1xmmc_card_table[] = {
+ { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0,
+ BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP },
+#ifndef CONFIG_MIPS_DB1200
+ { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1,
+ BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP }
+#endif
+};
+
+#define AU1XMMC_CONTROLLER_COUNT \
+ (sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0]))
+
+/* This array stores pointers for the hosts (used by the IRQ handler) */
+struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT];
+static int dma = 1;
+
+#ifdef MODULE
+MODULE_PARM(dma, "i");
+MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)");
+#endif
+
+static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
+{
+ u32 val = au_readl(HOST_CONFIG(host));
+ val |= mask;
+ au_writel(val, HOST_CONFIG(host));
+ au_sync();
+}
+
+static inline void FLUSH_FIFO(struct au1xmmc_host *host)
+{
+ u32 val = au_readl(HOST_CONFIG2(host));
+
+ au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
+ au_sync_delay(1);
+
+ /* SEND_STOP will turn off clock control - this re-enables it */
+ val &= ~SD_CONFIG2_DF;
+
+ au_writel(val, HOST_CONFIG2(host));
+ au_sync();
+}
+
+static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
+{
+ u32 val = au_readl(HOST_CONFIG(host));
+ val &= ~mask;
+ au_writel(val, HOST_CONFIG(host));
+ au_sync();
+}
+
+static inline void SEND_STOP(struct au1xmmc_host *host)
+{
+
+ /* We know the value of CONFIG2, so avoid a read we don't need */
+ u32 mask = SD_CONFIG2_EN;
+
+ WARN_ON(host->status != HOST_S_DATA);
+ host->status = HOST_S_STOP;
+
+ au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host));
+ au_sync();
+
+ /* Send the stop commmand */
+ au_writel(STOP_CMD, HOST_CMD(host));
+}
+
+static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
+{
+
+ u32 val = au1xmmc_card_table[host->id].bcsrpwr;
+
+ bcsr->board &= ~val;
+ if (state) bcsr->board |= val;
+
+ au_sync_delay(1);
+}
+
+static inline int au1xmmc_card_inserted(struct au1xmmc_host *host)
+{
+ return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus)
+ ? 1 : 0;
+}
+
+static inline int au1xmmc_card_readonly(struct au1xmmc_host *host)
+{
+ return (bcsr->status & au1xmmc_card_table[host->id].wpstatus)
+ ? 1 : 0;
+}
+
+static void au1xmmc_finish_request(struct au1xmmc_host *host)
+{
+
+ struct mmc_request *mrq = host->mrq;
+
+ host->mrq = NULL;
+ host->flags &= HOST_F_ACTIVE;
+
+ host->dma.len = 0;
+ host->dma.dir = 0;
+
+ host->pio.index = 0;
+ host->pio.offset = 0;
+ host->pio.len = 0;
+
+ host->status = HOST_S_IDLE;
+
+ bcsr->disk_leds |= (1 << 8);
+
+ mmc_request_done(host->mmc, mrq);
+}
+
+static void au1xmmc_tasklet_finish(unsigned long param)
+{
+ struct au1xmmc_host *host = (struct au1xmmc_host *) param;
+ au1xmmc_finish_request(host);
+}
+
+static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
+ struct mmc_command *cmd)
+{
+
+ u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
+
+ switch(cmd->flags) {
+ case MMC_RSP_R1:
+ mmccmd |= SD_CMD_RT_1;
+ break;
+ case MMC_RSP_R1B:
+ mmccmd |= SD_CMD_RT_1B;
+ break;
+ case MMC_RSP_R2:
+ mmccmd |= SD_CMD_RT_2;
+ break;
+ case MMC_RSP_R3:
+ mmccmd |= SD_CMD_RT_3;
+ break;
+ }
+
+ switch(cmd->opcode) {
+ case MMC_READ_SINGLE_BLOCK:
+ case SD_APP_SEND_SCR:
+ mmccmd |= SD_CMD_CT_2;
+ break;
+ case MMC_READ_MULTIPLE_BLOCK:
+ mmccmd |= SD_CMD_CT_4;
+ break;
+ case MMC_WRITE_BLOCK:
+ mmccmd |= SD_CMD_CT_1;
+ break;
+
+ case MMC_WRITE_MULTIPLE_BLOCK:
+ mmccmd |= SD_CMD_CT_3;
+ break;
+ case MMC_STOP_TRANSMISSION:
+ mmccmd |= SD_CMD_CT_7;
+ break;
+ }
+
+ au_writel(cmd->arg, HOST_CMDARG(host));
+ au_sync();
+
+ if (wait)
+ IRQ_OFF(host, SD_CONFIG_CR);
+
+ au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
+ au_sync();
+
+ /* Wait for the command to go on the line */
+
+ while(1) {
+ if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
+ break;
+ }
+
+ /* Wait for the command to come back */
+
+ if (wait) {
+ u32 status = au_readl(HOST_STATUS(host));
+
+ while(!(status & SD_STATUS_CR))
+ status = au_readl(HOST_STATUS(host));
+
+ /* Clear the CR status */
+ au_writel(SD_STATUS_CR, HOST_STATUS(host));
+
+ IRQ_ON(host, SD_CONFIG_CR);
+ }
+
+ return MMC_ERR_NONE;
+}
+
+static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
+{
+
+ struct mmc_request *mrq = host->mrq;
+ struct mmc_data *data;
+ u32 crc;
+
+ WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
+
+ if (host->mrq == NULL)
+ return;
+
+ data = mrq->cmd->data;
+
+ if (status == 0)
+ status = au_readl(HOST_STATUS(host));
+
+ /* The transaction is really over when the SD_STATUS_DB bit is clear */
+
+ while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
+ status = au_readl(HOST_STATUS(host));
+
+ data->error = MMC_ERR_NONE;
+ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
+
+ /* Process any errors */
+
+ crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
+ if (host->flags & HOST_F_XMIT)
+ crc |= ((status & 0x07) == 0x02) ? 0 : 1;
+
+ if (crc)
+ data->error = MMC_ERR_BADCRC;
+
+ /* Clear the CRC bits */
+ au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
+
+ data->bytes_xfered = 0;
+
+ if (data->error == MMC_ERR_NONE) {
+ if (host->flags & HOST_F_DMA) {
+ u32 chan = DMA_CHANNEL(host);
+
+ chan_tab_t *c = *((chan_tab_t **) chan);
+ au1x_dma_chan_t *cp = c->chan_ptr;
+ data->bytes_xfered = cp->ddma_bytecnt;
+ }
+ else
+ data->bytes_xfered =
+ (data->blocks * (1 << data->blksz_bits)) -
+ host->pio.len;
+ }
+
+ au1xmmc_finish_request(host);
+}
+
+static void au1xmmc_tasklet_data(unsigned long param)
+{
+ struct au1xmmc_host *host = (struct au1xmmc_host *) param;
+
+ u32 status = au_readl(HOST_STATUS(host));
+ au1xmmc_data_complete(host, status);
+}
+
+#define AU1XMMC_MAX_TRANSFER 8
+
+static void au1xmmc_send_pio(struct au1xmmc_host *host)
+{
+
+ struct mmc_data *data = 0;
+ int sg_len, max, count = 0;
+ unsigned char *sg_ptr;
+ u32 status = 0;
+ struct scatterlist *sg;
+
+ data = host->mrq->data;
+
+ if (!(host->flags & HOST_F_XMIT))
+ return;
+
+ /* This is the pointer to the data buffer */
+ sg = &data->sg[host->pio.index];
+ sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
+
+ /* This is the space left inside the buffer */
+ sg_len = data->sg[host->pio.index].length - host->pio.offset;
+
+ /* Check to if we need less then the size of the sg_buffer */
+
+ max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
+ if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
+
+ for(count = 0; count < max; count++ ) {
+ unsigned char val;
+
+ status = au_readl(HOST_STATUS(host));
+
+ if (!(status & SD_STATUS_TH))
+ break;
+
+ val = *sg_ptr++;
+
+ au_writel((unsigned long) val, HOST_TXPORT(host));
+ au_sync();
+ }
+
+ host->pio.len -= count;
+ host->pio.offset += count;
+
+ if (count == sg_len) {
+ host->pio.index++;
+ host->pio.offset = 0;
+ }
+
+ if (host->pio.len == 0) {
+ IRQ_OFF(host, SD_CONFIG_TH);
+
+ if (host->flags & HOST_F_STOP)
+ SEND_STOP(host);
+
+ tasklet_schedule(&host->data_task);
+ }
+}
+
+static void au1xmmc_receive_pio(struct au1xmmc_host *host)
+{
+
+ struct mmc_data *data = 0;
+ int sg_len = 0, max = 0, count = 0;
+ unsigned char *sg_ptr = 0;
+ u32 status = 0;
+ struct scatterlist *sg;
+
+ data = host->mrq->data;
+
+ if (!(host->flags & HOST_F_RECV))
+ return;
+
+ max = host->pio.len;
+
+ if (host->pio.index < host->dma.len) {
+ sg = &data->sg[host->pio.index];
+ sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
+
+ /* This is the space left inside the buffer */
+ sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
+
+ /* Check to if we need less then the size of the sg_buffer */
+ if (sg_len < max) max = sg_len;
+ }
+
+ if (max > AU1XMMC_MAX_TRANSFER)
+ max = AU1XMMC_MAX_TRANSFER;
+
+ for(count = 0; count < max; count++ ) {
+ u32 val;
+ status = au_readl(HOST_STATUS(host));
+
+ if (!(status & SD_STATUS_NE))
+ break;
+
+ if (status & SD_STATUS_RC) {
+ DEBUG("RX CRC Error [%d + %d].\n", host->id,
+ host->pio.len, count);
+ break;
+ }
+
+ if (status & SD_STATUS_RO) {
+ DEBUG("RX Overrun [%d + %d]\n", host->id,
+ host->pio.len, count);
+ break;
+ }
+ else if (status & SD_STATUS_RU) {
+ DEBUG("RX Underrun [%d + %d]\n", host->id,
+ host->pio.len, count);
+ break;
+ }
+
+ val = au_readl(HOST_RXPORT(host));
+
+ if (sg_ptr)
+ *sg_ptr++ = (unsigned char) (val & 0xFF);
+ }
+
+ host->pio.len -= count;
+ host->pio.offset += count;
+
+ if (sg_len && count == sg_len) {
+ host->pio.index++;
+ host->pio.offset = 0;
+ }
+
+ if (host->pio.len == 0) {
+ //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
+ IRQ_OFF(host, SD_CONFIG_NE);
+
+ if (host->flags & HOST_F_STOP)
+ SEND_STOP(host);
+
+ tasklet_schedule(&host->data_task);
+ }
+}
+
+/* static void au1xmmc_cmd_complete
+ This is called when a command has been completed - grab the response
+ and check for errors. Then start the data transfer if it is indicated.
+*/
+
+static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
+{
+
+ struct mmc_request *mrq = host->mrq;
+ struct mmc_command *cmd;
+ int trans;
+
+ if (!host->mrq)
+ return;
+
+ cmd = mrq->cmd;
+ cmd->error = MMC_ERR_NONE;
+
+ if ((cmd->flags & MMC_RSP_MASK) == MMC_RSP_SHORT) {
+
+ /* Techincally, we should be getting all 48 bits of the response
+ * (SD_RESP1 + SD_RESP2), but because our response omits the CRC,
+ * our data ends up being shifted 8 bits to the right. In this case,
+ * that means that the OSR data starts at bit 31, so we can just
+ * read RESP0 and return that
+ */
+
+ cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
+ }
+ else if ((cmd->flags & MMC_RSP_MASK) == MMC_RSP_LONG) {
+ u32 r[4];
+ int i;
+
+ r[0] = au_readl(host->iobase + SD_RESP3);
+ r[1] = au_readl(host->iobase + SD_RESP2);
+ r[2] = au_readl(host->iobase + SD_RESP1);
+ r[3] = au_readl(host->iobase + SD_RESP0);
+
+ /* The CRC is omitted from the response, so really we only got
+ * 120 bytes, but the engine expects 128 bits, so we have to shift
+ * things up
+ */
+
+ for(i = 0; i < 4; i++) {
+ cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
+ if (i != 3) cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
+ }
+ }
+
+ /* Figure out errors */
+
+ if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
+ cmd->error = MMC_ERR_BADCRC;
+
+ trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
+
+ if (!trans || cmd->error != MMC_ERR_NONE) {
+
+ IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
+ tasklet_schedule(&host->finish_task);
+ return;
+ }
+
+ host->status = HOST_S_DATA;
+
+ if (host->flags & HOST_F_DMA) {
+ u32 channel = DMA_CHANNEL(host);
+
+ /* Start the DMA as soon as the buffer gets something in it */
+
+ if (host->flags & HOST_F_RECV) {
+ u32 mask = SD_STATUS_DB | SD_STATUS_NE;
+
+ while((status & mask) != mask)
+ status = au_readl(HOST_STATUS(host));
+ }
+
+ au1xxx_dbdma_start(channel);
+ }
+}
+
+static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
+{
+
+ unsigned int pbus = get_au1x00_speed();
+ unsigned int divisor;
+ u32 config;
+
+ /* From databook:
+ divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
+ */
+
+ pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
+ pbus /= 2;
+
+ divisor = ((pbus / rate) / 2) - 1;
+
+ config = au_readl(HOST_CONFIG(host));
+
+ config &= ~(SD_CONFIG_DIV);
+ config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
+
+ au_writel(config, HOST_CONFIG(host));
+ au_sync();
+}
+
+static int
+au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
+{
+
+ int datalen = data->blocks * (1 << data->blksz_bits);
+
+ if (dma != 0)
+ host->flags |= HOST_F_DMA;
+
+ if (data->flags & MMC_DATA_READ)
+ host->flags |= HOST_F_RECV;
+ else
+ host->flags |= HOST_F_XMIT;
+
+ if (host->mrq->stop)
+ host->flags |= HOST_F_STOP;
+
+ host->dma.dir = DMA_BIDIRECTIONAL;
+
+ host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
+ data->sg_len, host->dma.dir);
+
+ if (host->dma.len == 0)
+ return MMC_ERR_TIMEOUT;
+
+ au_writel((1 << data->blksz_bits) - 1, HOST_BLKSIZE(host));
+
+ if (host->flags & HOST_F_DMA) {
+ int i;
+ u32 channel = DMA_CHANNEL(host);
+
+ au1xxx_dbdma_stop(channel);
+
+ for(i = 0; i < host->dma.len; i++) {
+ u32 ret = 0, flags = DDMA_FLAGS_NOIE;
+ struct scatterlist *sg = &data->sg[i];
+ int sg_len = sg->length;
+
+ int len = (datalen > sg_len) ? sg_len : datalen;
+
+ if (i == host->dma.len - 1)
+ flags = DDMA_FLAGS_IE;
+
+ if (host->flags & HOST_F_XMIT){
+ ret = au1xxx_dbdma_put_source_flags(channel,
+ (void *) (page_address(sg->page) +
+ sg->offset),
+ len, flags);
+ }
+ else {
+ ret = au1xxx_dbdma_put_dest_flags(channel,
+ (void *) (page_address(sg->page) +
+ sg->offset),
+ len, flags);
+ }
+
+ if (!ret)
+ goto dataerr;
+
+ datalen -= len;
+ }
+ }
+ else {
+ host->pio.index = 0;
+ host->pio.offset = 0;
+ host->pio.len = datalen;
+
+ if (host->flags & HOST_F_XMIT)
+ IRQ_ON(host, SD_CONFIG_TH);
+ else
+ IRQ_ON(host, SD_CONFIG_NE);
+ //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
+ }
+
+ return MMC_ERR_NONE;
+
+ dataerr:
+ dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir);
+ return MMC_ERR_TIMEOUT;
+}
+
+/* static void au1xmmc_request
+ This actually starts a command or data transaction
+*/
+
+static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
+{
+
+ struct au1xmmc_host *host = mmc_priv(mmc);
+ int ret = MMC_ERR_NONE;
+
+ WARN_ON(irqs_disabled());
+ WARN_ON(host->status != HOST_S_IDLE);
+
+ host->mrq = mrq;
+ host->status = HOST_S_CMD;
+
+ bcsr->disk_leds &= ~(1 << 8);
+
+ if (mrq->data) {
+ FLUSH_FIFO(host);
+ ret = au1xmmc_prepare_data(host, mrq->data);
+ }
+
+ if (ret == MMC_ERR_NONE)
+ ret = au1xmmc_send_command(host, 0, mrq->cmd);
+
+ if (ret != MMC_ERR_NONE) {
+ mrq->cmd->error = ret;
+ au1xmmc_finish_request(host);
+ }
+}
+
+static void au1xmmc_reset_controller(struct au1xmmc_host *host)
+{
+
+ /* Apply the clock */
+ au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
+ au_sync_delay(1);
+
+ au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
+ au_sync_delay(5);
+
+ au_writel(~0, HOST_STATUS(host));
+ au_sync();
+
+ au_writel(0, HOST_BLKSIZE(host));
+ au_writel(0x001fffff, HOST_TIMEOUT(host));
+ au_sync();
+
+ au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
+ au_sync();
+
+ au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
+ au_sync_delay(1);
+
+ au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
+ au_sync();
+
+ /* Configure interrupts */
+ au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
+ au_sync();
+}
+
+
+static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
+{
+ struct au1xmmc_host *host = mmc_priv(mmc);
+
+ DEBUG("set_ios (power=%u, clock=%uHz, vdd=%u, mode=%u)\n",
+ host->id, ios->power_mode, ios->clock, ios->vdd,
+ ios->bus_mode);
+
+ if (ios->power_mode == MMC_POWER_OFF)
+ au1xmmc_set_power(host, 0);
+ else if (ios->power_mode == MMC_POWER_ON) {
+ au1xmmc_set_power(host, 1);
+ }
+
+ if (ios->clock && ios->clock != host->clock) {
+ au1xmmc_set_clock(host, ios->clock);
+ host->clock = ios->clock;
+ }
+}
+
+static void au1xmmc_dma_callback(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id;
+ u32 status;
+
+ /* Avoid spurious interrupts */
+
+ if (!host->mrq)
+ return;
+
+ if (host->flags & HOST_F_STOP)
+ SEND_STOP(host);
+
+ tasklet_schedule(&host->data_task);
+}
+
+#define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
+#define STATUS_DATA_IN (SD_STATUS_NE)
+#define STATUS_DATA_OUT (SD_STATUS_TH)
+
+static irqreturn_t au1xmmc_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+
+ u32 status;
+ int i, ret = 0;
+
+ disable_irq(AU1100_SD_IRQ);
+
+ for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
+ struct au1xmmc_host * host = au1xmmc_hosts[i];
+ u32 handled = 1;
+
+ status = au_readl(HOST_STATUS(host));
+
+ if (host->mrq && (status & STATUS_TIMEOUT)) {
+ if (status & SD_STATUS_RAT)
+ host->mrq->cmd->error = MMC_ERR_TIMEOUT;
+
+ else if (status & SD_STATUS_DT)
+ host->mrq->data->error = MMC_ERR_TIMEOUT;
+
+ /* In PIO mode, interrupts might still be enabled */
+ IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
+
+ //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF);
+ tasklet_schedule(&host->finish_task);
+ }
+#if 0
+ else if (status & SD_STATUS_DD) {
+
+ /* Sometimes we get a DD before a NE in PIO mode */
+
+ if (!(host->flags & HOST_F_DMA) &&
+ (status & SD_STATUS_NE))
+ au1xmmc_receive_pio(host);
+ else {
+ au1xmmc_data_complete(host, status);
+ //tasklet_schedule(&host->data_task);
+ }
+ }
+#endif
+ else if (status & (SD_STATUS_CR)) {
+ if (host->status == HOST_S_CMD)
+ au1xmmc_cmd_complete(host,status);
+ }
+ else if (!(host->flags & HOST_F_DMA)) {
+ if ((host->flags & HOST_F_XMIT) &&
+ (status & STATUS_DATA_OUT))
+ au1xmmc_send_pio(host);
+ else if ((host->flags & HOST_F_RECV) &&
+ (status & STATUS_DATA_IN))
+ au1xmmc_receive_pio(host);
+ }
+ else if (status & 0x203FBC70) {
+ DEBUG("Unhandled status %8.8x\n", host->id, status);
+ handled = 0;
+ }
+
+ au_writel(status, HOST_STATUS(host));
+ au_sync();
+
+ ret |= handled;
+ }
+
+ enable_irq(AU1100_SD_IRQ);
+ return ret;
+}
+
+static void au1xmmc_poll_event(unsigned long arg)
+{
+ struct au1xmmc_host *host = (struct au1xmmc_host *) arg;
+
+ int card = au1xmmc_card_inserted(host);
+ int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
+
+ if (card != controller) {
+ host->flags &= ~HOST_F_ACTIVE;
+ if (card) host->flags |= HOST_F_ACTIVE;
+ mmc_detect_change(host->mmc, 0);
+ }
+
+ if (host->mrq != NULL) {
+ u32 status = au_readl(HOST_STATUS(host));
+ DEBUG("PENDING - %8.8x\n", host->id, status);
+ }
+
+ mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
+}
+
+static dbdev_tab_t au1xmmc_mem_dbdev =
+{
+ DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0
+};
+
+static void au1xmmc_init_dma(struct au1xmmc_host *host)
+{
+
+ u32 rxchan, txchan;
+
+ int txid = au1xmmc_card_table[host->id].tx_devid;
+ int rxid = au1xmmc_card_table[host->id].rx_devid;
+
+ /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
+ of 8 bits. And since devices are shared, we need to create
+ our own to avoid freaking out other devices
+ */
+
+ int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
+
+ txchan = au1xxx_dbdma_chan_alloc(memid, txid,
+ au1xmmc_dma_callback, (void *) host);
+
+ rxchan = au1xxx_dbdma_chan_alloc(rxid, memid,
+ au1xmmc_dma_callback, (void *) host);
+
+ au1xxx_dbdma_set_devwidth(txchan, 8);
+ au1xxx_dbdma_set_devwidth(rxchan, 8);
+
+ au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT);
+ au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT);
+
+ host->tx_chan = txchan;
+ host->rx_chan = rxchan;
+}
+
+struct mmc_host_ops au1xmmc_ops = {
+ .request = au1xmmc_request,
+ .set_ios = au1xmmc_set_ios,
+};
+
+static int au1xmmc_probe(struct device *dev)
+{
+
+ int i, ret = 0;
+
+ /* THe interrupt is shared among all controllers */
+ ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, SA_INTERRUPT, "MMC", 0);
+
+ if (ret) {
+ printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n",
+ AU1100_SD_IRQ, ret);
+ return -ENXIO;
+ }
+
+ disable_irq(AU1100_SD_IRQ);
+
+ for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
+ struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), dev);
+ struct au1xmmc_host *host = 0;
+
+ if (!mmc) {
+ printk(DRIVER_NAME "ERROR: no mem for host %d\n", i);
+ au1xmmc_hosts[i] = 0;
+ continue;
+ }
+
+ mmc->ops = &au1xmmc_ops;
+
+ mmc->f_min = 450000;
+ mmc->f_max = 24000000;
+
+ mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
+ mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
+
+ mmc->ocr_avail = AU1XMMC_OCR;
+
+ host = mmc_priv(mmc);
+ host->mmc = mmc;
+
+ host->id = i;
+ host->iobase = au1xmmc_card_table[host->id].iobase;
+ host->clock = 0;
+ host->power_mode = MMC_POWER_OFF;
+
+ host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0;
+ host->status = HOST_S_IDLE;
+
+ init_timer(&host->timer);
+
+ host->timer.function = au1xmmc_poll_event;
+ host->timer.data = (unsigned long) host;
+ host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
+
+ tasklet_init(&host->data_task, au1xmmc_tasklet_data,
+ (unsigned long) host);
+
+ tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
+ (unsigned long) host);
+
+ spin_lock_init(&host->lock);
+
+ if (dma != 0)
+ au1xmmc_init_dma(host);
+
+ au1xmmc_reset_controller(host);
+
+ mmc_add_host(mmc);
+ au1xmmc_hosts[i] = host;
+
+ add_timer(&host->timer);
+
+ printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n",
+ host->id, host->iobase, dma ? "dma" : "pio");
+ }
+
+ enable_irq(AU1100_SD_IRQ);
+
+ return 0;
+}
+
+static int au1xmmc_remove(struct device *dev)
+{
+
+ int i;
+
+ disable_irq(AU1100_SD_IRQ);
+
+ for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
+ struct au1xmmc_host *host = au1xmmc_hosts[i];
+ if (!host) continue;
+
+ tasklet_kill(&host->data_task);
+ tasklet_kill(&host->finish_task);
+
+ del_timer_sync(&host->timer);
+ au1xmmc_set_power(host, 0);
+
+ mmc_remove_host(host->mmc);
+
+ au1xxx_dbdma_chan_free(host->tx_chan);
+ au1xxx_dbdma_chan_free(host->rx_chan);
+
+ au_writel(0x0, HOST_ENABLE(host));
+ au_sync();
+ }
+
+ free_irq(AU1100_SD_IRQ, 0);
+ return 0;
+}
+
+static struct device_driver au1xmmc_driver = {
+ .name = DRIVER_NAME,
+ .bus = &platform_bus_type,
+ .probe = au1xmmc_probe,
+ .remove = au1xmmc_remove,
+ .suspend = NULL,
+ .resume = NULL
+};
+
+static int __init au1xmmc_init(void)
+{
+ return driver_register(&au1xmmc_driver);
+}
+
+static void __exit au1xmmc_exit(void)
+{
+ driver_unregister(&au1xmmc_driver);
+}
+
+module_init(au1xmmc_init);
+module_exit(au1xmmc_exit);
+
+#ifdef MODULE
+MODULE_AUTHOR("Advanced Micro Devices, Inc");
+MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
+MODULE_LICENSE("GPL");
+#endif
+
diff --git a/drivers/mmc/au1xmmc.h b/drivers/mmc/au1xmmc.h
new file mode 100644
index 00000000000..341cbdf0bac
--- /dev/null
+++ b/drivers/mmc/au1xmmc.h
@@ -0,0 +1,96 @@
+#ifndef _AU1XMMC_H_
+#define _AU1XMMC_H_
+
+/* Hardware definitions */
+
+#define AU1XMMC_DESCRIPTOR_COUNT 1
+#define AU1XMMC_DESCRIPTOR_SIZE 2048
+
+#define AU1XMMC_OCR ( MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
+ MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
+ MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
+
+/* Easy access macros */
+
+#define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
+#define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
+#define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
+#define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT)
+#define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT)
+#define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG)
+#define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
+#define HOST_CMD(h) ((h)->iobase + SD_CMD)
+#define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
+#define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
+#define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
+
+#define DMA_CHANNEL(h) \
+ ( ((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
+
+/* This gives us a hard value for the stop command that we can write directly
+ * to the command register
+ */
+
+#define STOP_CMD (SD_CMD_RT_1B|SD_CMD_CT_7|(0xC << SD_CMD_CI_SHIFT)|SD_CMD_GO)
+
+/* This is the set of interrupts that we configure by default */
+
+#if 0
+#define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_DD | \
+ SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I)
+#endif
+
+#define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | \
+ SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I)
+/* The poll event (looking for insert/remove events runs twice a second */
+#define AU1XMMC_DETECT_TIMEOUT (HZ/2)
+
+struct au1xmmc_host {
+ struct mmc_host *mmc;
+ struct mmc_request *mrq;
+
+ u32 id;
+
+ u32 flags;
+ u32 iobase;
+ u32 clock;
+ u32 bus_width;
+ u32 power_mode;
+
+ int status;
+
+ struct {
+ int len;
+ int dir;
+ } dma;
+
+ struct {
+ int index;
+ int offset;
+ int len;
+ } pio;
+
+ u32 tx_chan;
+ u32 rx_chan;
+
+ struct timer_list timer;
+ struct tasklet_struct finish_task;
+ struct tasklet_struct data_task;
+
+ spinlock_t lock;
+};
+
+/* Status flags used by the host structure */
+
+#define HOST_F_XMIT 0x0001
+#define HOST_F_RECV 0x0002
+#define HOST_F_DMA 0x0010
+#define HOST_F_ACTIVE 0x0100
+#define HOST_F_STOP 0x1000
+
+#define HOST_S_IDLE 0x0001
+#define HOST_S_CMD 0x0002
+#define HOST_S_DATA 0x0003
+#define HOST_S_STOP 0x0004
+
+#endif
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index a41fbb38fdc..77ecee7f987 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -42,9 +42,11 @@ pxa2xx_core-y += soc_common.o pxa2xx_base.o
au1x00_ss-y += au1000_generic.o
au1x00_ss-$(CONFIG_MIPS_PB1000) += au1000_pb1x00.o
au1x00_ss-$(CONFIG_MIPS_PB1100) += au1000_pb1x00.o
+au1x00_ss-$(CONFIG_MIPS_PB1200) += au1000_db1x00.o
au1x00_ss-$(CONFIG_MIPS_PB1500) += au1000_pb1x00.o
au1x00_ss-$(CONFIG_MIPS_DB1000) += au1000_db1x00.o
au1x00_ss-$(CONFIG_MIPS_DB1100) += au1000_db1x00.o
+au1x00_ss-$(CONFIG_MIPS_DB1200) += au1000_db1x00.o
au1x00_ss-$(CONFIG_MIPS_DB1500) += au1000_db1x00.o
au1x00_ss-$(CONFIG_MIPS_DB1550) += au1000_db1x00.o
au1x00_ss-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o
diff --git a/drivers/pcmcia/au1000_db1x00.c b/drivers/pcmcia/au1000_db1x00.c
index 42cf8bfbcc9..24cfee1a412 100644
--- a/drivers/pcmcia/au1000_db1x00.c
+++ b/drivers/pcmcia/au1000_db1x00.c
@@ -40,7 +40,15 @@
#include <asm/irq.h>
#include <asm/signal.h>
#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-db1x00/db1x00.h>
+
+#if defined(CONFIG_MIPS_DB1200)
+ #include <db1200.h>
+#elif defined(CONFIG_MIPS_PB1200)
+ #include <pb1200.h>
+#else
+ #include <asm/mach-db1x00/db1x00.h>
+ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+#endif
#include "au1000_generic.h"
@@ -50,7 +58,6 @@
#define debug(x,args...)
#endif
-static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
struct au1000_pcmcia_socket au1000_pcmcia_socket[PCMCIA_NUM_SOCKS];
extern int au1x00_pcmcia_socket_probe(struct device *, struct pcmcia_low_level *, int, int);
@@ -59,6 +66,8 @@ static int db1x00_pcmcia_hw_init(struct au1000_pcmcia_socket *skt)
{
#ifdef CONFIG_MIPS_DB1550
skt->irq = skt->nr ? AU1000_GPIO_5 : AU1000_GPIO_3;
+#elif defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200)
+ skt->irq = skt->nr ? BOARD_PC1_INT : BOARD_PC0_INT;
#else
skt->irq = skt->nr ? AU1000_GPIO_5 : AU1000_GPIO_2;
#endif
@@ -85,11 +94,19 @@ db1x00_pcmcia_socket_state(struct au1000_pcmcia_socket *skt, struct pcmcia_state
switch (skt->nr) {
case 0:
vs = bcsr->status & 0x3;
+#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200)
+ inserted = BOARD_CARD_INSERTED(0);
+#else
inserted = !(bcsr->status & (1<<4));
+#endif
break;
case 1:
vs = (bcsr->status & 0xC)>>2;
+#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200)
+ inserted = BOARD_CARD_INSERTED(1);
+#else
inserted = !(bcsr->status & (1<<5));
+#endif
break;
default:/* should never happen */
return;
diff --git a/drivers/pcmcia/au1000_generic.c b/drivers/pcmcia/au1000_generic.c
index d90a634cebf..ba48cef3a9d 100644
--- a/drivers/pcmcia/au1000_generic.c
+++ b/drivers/pcmcia/au1000_generic.c
@@ -490,7 +490,7 @@ int au1x00_drv_pcmcia_remove(struct device *dev)
flush_scheduled_work();
skt->ops->hw_shutdown(skt);
au1x00_pcmcia_config_skt(skt, &dead_socket);
- iounmap(skt->virt_io);
+ iounmap(skt->virt_io + (u32)mips_io_port_base);
skt->virt_io = NULL;
}
@@ -528,10 +528,6 @@ static struct device_driver au1x00_pcmcia_driver = {
.resume = pcmcia_socket_dev_resume,
};
-static struct platform_device au1x00_device = {
- .name = "au1x00-pcmcia",
- .id = 0,
-};
/* au1x00_pcmcia_init()
*
@@ -545,7 +541,6 @@ static int __init au1x00_pcmcia_init(void)
int error = 0;
if ((error = driver_register(&au1x00_pcmcia_driver)))
return error;
- platform_device_register(&au1x00_device);
return error;
}
@@ -556,7 +551,6 @@ static int __init au1x00_pcmcia_init(void)
static void __exit au1x00_pcmcia_exit(void)
{
driver_unregister(&au1x00_pcmcia_driver);
- platform_device_unregister(&au1x00_device);
}
module_init(au1x00_pcmcia_init);
diff --git a/drivers/pcmcia/au1000_generic.h b/drivers/pcmcia/au1000_generic.h
index d5122b1ea94..b0e7908392a 100644
--- a/drivers/pcmcia/au1000_generic.h
+++ b/drivers/pcmcia/au1000_generic.h
@@ -44,13 +44,13 @@
/* pcmcia socket 1 needs external glue logic so the memory map
* differs from board to board.
*/
-#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1550)
+#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_PB1200)
#define AU1X_SOCK1_IO 0xF08000000
#define AU1X_SOCK1_PHYS_ATTR 0xF48000000
#define AU1X_SOCK1_PHYS_MEM 0xF88000000
#define AU1X_SOCK1_PSEUDO_PHYS_ATTR 0xF4800000
#define AU1X_SOCK1_PSEUDO_PHYS_MEM 0xF8800000
-#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
+#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) || defined(CONFIG_MIPS_DB1200)
#define AU1X_SOCK1_IO 0xF04000000
#define AU1X_SOCK1_PHYS_ATTR 0xF44000000
#define AU1X_SOCK1_PHYS_MEM 0xF84000000
diff --git a/drivers/scsi/dec_esp.c b/drivers/scsi/dec_esp.c
index 315f95a0d6c..4f39890b44a 100644
--- a/drivers/scsi/dec_esp.c
+++ b/drivers/scsi/dec_esp.c
@@ -228,7 +228,7 @@ static int dec_esp_detect(Scsi_Host_Template * tpnt)
mem_start = get_tc_base_addr(slot);
/* Store base addr into esp struct */
- esp->slot = PHYSADDR(mem_start);
+ esp->slot = CPHYSADDR(mem_start);
esp->dregs = 0;
esp->eregs = (struct ESP_regs *) (mem_start + DEC_SCSI_SREG);
diff --git a/drivers/tc/tc.c b/drivers/tc/tc.c
index a89ef4df80c..a0e5af638e0 100644
--- a/drivers/tc/tc.c
+++ b/drivers/tc/tc.c
@@ -8,33 +8,31 @@
* for more details.
*
* Copyright (c) Harald Koerfgen, 1998
- * Copyright (c) 2001, 2003 Maciej W. Rozycki
+ * Copyright (c) 2001, 2003, 2005 Maciej W. Rozycki
*/
-#include <linux/string.h>
#include <linux/init.h>
-#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/types.h>
#include <asm/addrspace.h>
+#include <asm/bug.h>
#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/paccess.h>
+
#include <asm/dec/machtype.h>
#include <asm/dec/prom.h>
#include <asm/dec/tcinfo.h>
#include <asm/dec/tcmodule.h>
#include <asm/dec/interrupts.h>
-#include <asm/paccess.h>
-#include <asm/ptrace.h>
-
-#define TC_DEBUG
MODULE_LICENSE("GPL");
slot_info tc_bus[MAX_SLOT];
static int num_tcslots;
static tcinfo *info;
-unsigned long system_base;
-
/*
* Interface to the world. Read comment in include/asm-mips/tc.h.
*/
@@ -97,13 +95,16 @@ unsigned long get_tc_speed(void)
static void __init tc_probe(unsigned long startaddr, unsigned long size,
int slots)
{
+ unsigned long slotaddr;
int i, slot, err;
long offset;
- unsigned char pattern[4];
- unsigned char *module;
+ u8 pattern[4];
+ volatile u8 *module;
for (slot = 0; slot < slots; slot++) {
- module = (char *)(startaddr + slot * size);
+ slotaddr = startaddr + slot * size;
+ module = ioremap_nocache(slotaddr, size);
+ BUG_ON(!module);
offset = OLDCARD;
@@ -112,8 +113,10 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
err |= get_dbe(pattern[1], module + OLDCARD + TC_PATTERN1);
err |= get_dbe(pattern[2], module + OLDCARD + TC_PATTERN2);
err |= get_dbe(pattern[3], module + OLDCARD + TC_PATTERN3);
- if (err)
+ if (err) {
+ iounmap(module);
continue;
+ }
if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
pattern[2] != 0xaa || pattern[3] != 0xff) {
@@ -124,16 +127,20 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
err |= get_dbe(pattern[1], module + TC_PATTERN1);
err |= get_dbe(pattern[2], module + TC_PATTERN2);
err |= get_dbe(pattern[3], module + TC_PATTERN3);
- if (err)
+ if (err) {
+ iounmap(module);
continue;
+ }
}
if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
- pattern[2] != 0xaa || pattern[3] != 0xff)
+ pattern[2] != 0xaa || pattern[3] != 0xff) {
+ iounmap(module);
continue;
+ }
- tc_bus[slot].base_addr = (unsigned long)module;
- for(i = 0; i < 8; i++) {
+ tc_bus[slot].base_addr = slotaddr;
+ for (i = 0; i < 8; i++) {
tc_bus[slot].firmware[i] =
module[TC_FIRM_VER + offset + 4 * i];
tc_bus[slot].vendor[i] =
@@ -171,13 +178,15 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
tc_bus[slot].interrupt = -1;
break;
}
+
+ iounmap(module);
}
}
/*
* the main entry
*/
-void __init tc_init(void)
+static int __init tc_init(void)
{
int tc_clock;
int i;
@@ -185,7 +194,7 @@ void __init tc_init(void)
unsigned long slot_size;
if (!TURBOCHANNEL)
- return;
+ return 0;
for (i = 0; i < MAX_SLOT; i++) {
tc_bus[i].base_addr = 0;
@@ -196,8 +205,8 @@ void __init tc_init(void)
tc_bus[i].flags = FREE;
}
- info = (tcinfo *) rex_gettcinfo();
- slot0addr = (unsigned long)KSEG1ADDR(rex_slot_address(0));
+ info = rex_gettcinfo();
+ slot0addr = CPHYSADDR((long)rex_slot_address(0));
switch (mips_machtype) {
case MACH_DS5000_200:
@@ -216,37 +225,24 @@ void __init tc_init(void)
tc_clock = 10000 / info->clk_period;
- if (TURBOCHANNEL && info->slot_size && slot0addr) {
- printk("TURBOchannel rev. %1d at %2d.%1d MHz ", info->revision,
- tc_clock / 10, tc_clock % 10);
- printk("(with%s parity)\n", info->parity ? "" : "out");
+ if (info->slot_size && slot0addr) {
+ pr_info("TURBOchannel rev. %d at %d.%d MHz (with%s parity)\n",
+ info->revision, tc_clock / 10, tc_clock % 10,
+ info->parity ? "" : "out");
slot_size = info->slot_size << 20;
tc_probe(slot0addr, slot_size, num_tcslots);
- /*
- * All TURBOchannel DECstations have the onboard devices
- * where the (num_tcslots + 0 or 1 on DS5k/xx) Option Module
- * would be.
- */
- if(mips_machtype == MACH_DS5000_XX)
- i = 1;
- else
- i = 0;
-
- system_base = slot0addr + slot_size * (num_tcslots + i);
-
-#ifdef TC_DEBUG
- for (i = 0; i < num_tcslots; i++)
- if (tc_bus[i].base_addr) {
- printk(" slot %d: ", i);
- printk("%s %s %s\n", tc_bus[i].vendor,
- tc_bus[i].name, tc_bus[i].firmware);
- }
-#endif
- ioport_resource.end = KSEG2 - 1;
+ for (i = 0; i < num_tcslots; i++) {
+ if (!tc_bus[i].base_addr)
+ continue;
+ pr_info(" slot %d: %s %s %s\n", i, tc_bus[i].vendor,
+ tc_bus[i].name, tc_bus[i].firmware);
+ }
}
+
+ return 0;
}
subsys_initcall(tc_init);
@@ -257,4 +253,3 @@ EXPORT_SYMBOL(release_tc_card);
EXPORT_SYMBOL(get_tc_base_addr);
EXPORT_SYMBOL(get_tc_irq_nr);
EXPORT_SYMBOL(get_tc_speed);
-EXPORT_SYMBOL(system_base);
diff --git a/drivers/tc/zs.c b/drivers/tc/zs.c
index 6bed8713897..c52af73a251 100644
--- a/drivers/tc/zs.c
+++ b/drivers/tc/zs.c
@@ -65,14 +65,14 @@
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/bootinfo.h>
-#include <asm/dec/serial.h>
-#ifdef CONFIG_MACH_DECSTATION
#include <asm/dec/interrupts.h>
+#include <asm/dec/ioasic_addrs.h>
#include <asm/dec/machtype.h>
+#include <asm/dec/serial.h>
+#include <asm/dec/system.h>
#include <asm/dec/tc.h>
-#include <asm/dec/ioasic_addrs.h>
-#endif
+
#ifdef CONFIG_KGDB
#include <asm/kgdb.h>
#endif
@@ -192,18 +192,6 @@ static void probe_sccs(void);
static void change_speed(struct dec_serial *info);
static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
-/*
- * tmp_buf is used as a temporary buffer by serial_write. We need to
- * lock it in case the copy_from_user blocks while swapping in a page,
- * and some other program tries to do a serial write at the same time.
- * Since the lock will only come under contention when the system is
- * swapping and available memory is low, it makes sense to share one
- * buffer across all the serial ports, since it significantly saves
- * memory if large numbers of serial ports are open.
- */
-static unsigned char tmp_buf[4096]; /* This is cheating */
-static DECLARE_MUTEX(tmp_buf_sem);
-
static inline int serial_paranoia_check(struct dec_serial *info,
char *name, const char *routine)
{
@@ -1628,30 +1616,22 @@ static void __init probe_sccs(void)
return;
}
- /*
- * When serial console is activated, tc_init has not been called yet
- * and system_base is undefined. Unfortunately we have to hardcode
- * system_base for this case :-(. HK
- */
switch(mips_machtype) {
#ifdef CONFIG_MACH_DECSTATION
case MACH_DS5000_2X0:
case MACH_DS5900:
- system_base = KSEG1ADDR(0x1f800000);
n_chips = 2;
zs_parms = &ds_parms;
zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
break;
case MACH_DS5000_1XX:
- system_base = KSEG1ADDR(0x1c000000);
n_chips = 2;
zs_parms = &ds_parms;
zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
break;
case MACH_DS5000_XX:
- system_base = KSEG1ADDR(0x1c000000);
n_chips = 1;
zs_parms = &ds_parms;
zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
@@ -1673,10 +1653,10 @@ static void __init probe_sccs(void)
* The sccs reside on the high byte of the 16 bit IOBUS
*/
zs_channels[n_channels].control =
- (volatile unsigned char *)system_base +
+ (volatile void *)CKSEG1ADDR(dec_kn_slot_base +
(0 == chip ? zs_parms->scc0 : zs_parms->scc1) +
(0 == channel ? zs_parms->channel_a_offset :
- zs_parms->channel_b_offset);
+ zs_parms->channel_b_offset));
zs_channels[n_channels].data =
zs_channels[n_channels].control + 4;
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1cd942abb58..7e297947a2b 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1376,7 +1376,7 @@ config FB_HIT
config FB_PMAG_AA
bool "PMAG-AA TURBOchannel framebuffer support"
- depends on (FB = y) && MACH_DECSTATION && TC
+ depends on (FB = y) && TC
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
@@ -1387,7 +1387,7 @@ config FB_PMAG_AA
config FB_PMAG_BA
bool "PMAG-BA TURBOchannel framebuffer support"
- depends on (FB = y) && MACH_DECSTATION && TC
+ depends on (FB = y) && TC
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
@@ -1398,7 +1398,7 @@ config FB_PMAG_BA
config FB_PMAGB_B
bool "PMAGB-B TURBOchannel framebuffer support"
- depends on (FB = y) && MACH_DECSTATION && TC
+ depends on (FB = y) && TC
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
@@ -1410,7 +1410,7 @@ config FB_PMAGB_B
config FB_MAXINE
bool "Maxine (Personal DECstation) onboard framebuffer support"
- depends on (FB = y) && MACH_DECSTATION && TC
+ depends on (FB = y) && MACH_DECSTATION
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 1fff29f48ca..97c5d03ac8d 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -86,7 +86,7 @@ obj-$(CONFIG_FB_CIRRUS) += cirrusfb.o
obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o
obj-$(CONFIG_FB_PXA) += pxafb.o
obj-$(CONFIG_FB_W100) += w100fb.o
-obj-$(CONFIG_FB_AU1100) += au1100fb.o fbgen.o
+obj-$(CONFIG_FB_AU1100) += au1100fb.o
obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o
obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o
obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o
diff --git a/drivers/video/au1100fb.c b/drivers/video/au1100fb.c
index b6fe30c3ad6..a5129806172 100644
--- a/drivers/video/au1100fb.c
+++ b/drivers/video/au1100fb.c
@@ -2,6 +2,11 @@
* BRIEF MODULE DESCRIPTION
* Au1100 LCD Driver.
*
+ * Rewritten for 2.6 by Embedded Alley Solutions
+ * <source@embeddedalley.com>, based on submissions by
+ * Karl Lessard <klessard@sunrisetelecom.com>
+ * <c.pellegrin@exadron.com>
+ *
* Copyright 2002 MontaVista Software
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
@@ -33,298 +38,253 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-
+#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
-#include <linux/tty.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
-#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/ctype.h>
+#include <linux/dma-mapping.h>
-#include <asm/au1000.h>
-#include <asm/pb1100.h>
-#include "au1100fb.h"
+#include <asm/mach-au1x00/au1000.h>
-#include <video/fbcon.h>
-#include <video/fbcon-mfb.h>
-#include <video/fbcon-cfb2.h>
-#include <video/fbcon-cfb4.h>
-#include <video/fbcon-cfb8.h>
-#include <video/fbcon-cfb16.h>
+#define DEBUG 0
+
+#include "au1100fb.h"
/*
* Sanity check. If this is a new Au1100 based board, search for
* the PB1100 ifdefs to make sure you modify the code accordingly.
*/
-#if defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_HYDROGEN3)
+#if defined(CONFIG_MIPS_PB1100)
+ #include <asm/mach-pb1x00/pb1100.h>
+#elif defined(CONFIG_MIPS_DB1100)
+ #include <asm/mach-db1x00/db1x00.h>
#else
-error Unknown Au1100 board
+ #error "Unknown Au1100 board, Au1100 FB driver not supported"
#endif
-#define CMAPSIZE 16
-
-static int my_lcd_index; /* default is zero */
-struct known_lcd_panels *p_lcd;
-AU1100_LCD *p_lcd_reg = (AU1100_LCD *)AU1100_LCD_ADDR;
-
-struct au1100fb_info {
- struct fb_info_gen gen;
- unsigned long fb_virt_start;
- unsigned long fb_size;
- unsigned long fb_phys;
- int mmaped;
- int nohwcursor;
+#define DRIVER_NAME "au1100fb"
+#define DRIVER_DESC "LCD controller driver for AU1100 processors"
- struct { unsigned red, green, blue, pad; } palette[256];
+#define to_au1100fb_device(_info) \
+ (_info ? container_of(_info, struct au1100fb_device, info) : NULL);
-#if defined(FBCON_HAS_CFB16)
- u16 fbcon_cmap16[16];
-#endif
+/* Bitfields format supported by the controller. Note that the order of formats
+ * SHOULD be the same as in the LCD_CONTROL_SBPPF field, so we can retrieve the
+ * right pixel format by doing rgb_bitfields[LCD_CONTROL_SBPPF_XXX >> LCD_CONTROL_SBPPF]
+ */
+struct fb_bitfield rgb_bitfields[][4] =
+{
+ /* Red, Green, Blue, Transp */
+ { { 10, 6, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
+ { { 11, 5, 0 }, { 5, 6, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
+ { { 11, 5, 0 }, { 6, 5, 0 }, { 0, 6, 0 }, { 0, 0, 0 } },
+ { { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 15, 1, 0 } },
+ { { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 1, 0 } },
+
+ /* The last is used to describe 12bpp format */
+ { { 8, 4, 0 }, { 4, 4, 0 }, { 0, 4, 0 }, { 0, 0, 0 } },
};
-
-struct au1100fb_par {
- struct fb_var_screeninfo var;
-
- int line_length; // in bytes
- int cmap_len; // color-map length
+static struct fb_fix_screeninfo au1100fb_fix __initdata = {
+ .id = "AU1100 FB",
+ .xpanstep = 1,
+ .ypanstep = 1,
+ .type = FB_TYPE_PACKED_PIXELS,
+ .accel = FB_ACCEL_NONE,
};
-
-static struct au1100fb_info fb_info;
-static struct au1100fb_par current_par;
-static struct display disp;
-
-int au1100fb_init(void);
-void au1100fb_setup(char *options, int *ints);
-static int au1100fb_mmap(struct fb_info *fb, struct file *file,
- struct vm_area_struct *vma);
-static int au1100_blank(int blank_mode, struct fb_info_gen *info);
-static int au1100fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
- u_long arg, int con, struct fb_info *info);
-
-void au1100_nocursor(struct display *p, int mode, int xx, int yy){};
-
-static struct fb_ops au1100fb_ops = {
- .owner = THIS_MODULE,
- .fb_get_fix = fbgen_get_fix,
- .fb_get_var = fbgen_get_var,
- .fb_set_var = fbgen_set_var,
- .fb_get_cmap = fbgen_get_cmap,
- .fb_set_cmap = fbgen_set_cmap,
- .fb_pan_display = fbgen_pan_display,
- .fb_ioctl = au1100fb_ioctl,
- .fb_mmap = au1100fb_mmap,
+static struct fb_var_screeninfo au1100fb_var __initdata = {
+ .activate = FB_ACTIVATE_NOW,
+ .height = -1,
+ .width = -1,
+ .vmode = FB_VMODE_NONINTERLACED,
};
-static void au1100_detect(void)
-{
- /*
- * This function should detect the current video mode settings
- * and store it as the default video mode
- */
+static struct au1100fb_drv_info drv_info;
- /*
- * Yeh, well, we're not going to change any settings so we're
- * always stuck with the default ...
+/*
+ * Set hardware with var settings. This will enable the controller with a specific
+ * mode, normally validated with the fb_check_var method
*/
-
-}
-
-static int au1100_encode_fix(struct fb_fix_screeninfo *fix,
- const void *_par, struct fb_info_gen *_info)
+int au1100fb_setmode(struct au1100fb_device *fbdev)
{
- struct au1100fb_info *info = (struct au1100fb_info *) _info;
- struct au1100fb_par *par = (struct au1100fb_par *) _par;
- struct fb_var_screeninfo *var = &par->var;
-
- memset(fix, 0, sizeof(struct fb_fix_screeninfo));
-
- fix->smem_start = info->fb_phys;
- fix->smem_len = info->fb_size;
- fix->type = FB_TYPE_PACKED_PIXELS;
- fix->type_aux = 0;
- fix->visual = (var->bits_per_pixel == 8) ?
- FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
- fix->ywrapstep = 0;
- fix->xpanstep = 1;
- fix->ypanstep = 1;
- fix->line_length = current_par.line_length;
- return 0;
-}
+ struct fb_info *info = &fbdev->info;
+ u32 words;
+ int index;
-static void set_color_bitfields(struct fb_var_screeninfo *var)
-{
- switch (var->bits_per_pixel) {
- case 8:
- var->red.offset = 0;
- var->red.length = 8;
- var->green.offset = 0;
- var->green.length = 8;
- var->blue.offset = 0;
- var->blue.length = 8;
- var->transp.offset = 0;
- var->transp.length = 0;
- break;
- case 16: /* RGB 565 */
- var->red.offset = 11;
- var->red.length = 5;
- var->green.offset = 5;
- var->green.length = 6;
- var->blue.offset = 0;
- var->blue.length = 5;
- var->transp.offset = 0;
- var->transp.length = 0;
- break;
+ if (!fbdev)
+ return -EINVAL;
+
+ /* Update var-dependent FB info */
+ if (panel_is_active(fbdev->panel) || panel_is_color(fbdev->panel)) {
+ if (info->var.bits_per_pixel <= 8) {
+ /* palettized */
+ info->var.red.offset = 0;
+ info->var.red.length = info->var.bits_per_pixel;
+ info->var.red.msb_right = 0;
+
+ info->var.green.offset = 0;
+ info->var.green.length = info->var.bits_per_pixel;
+ info->var.green.msb_right = 0;
+
+ info->var.blue.offset = 0;
+ info->var.blue.length = info->var.bits_per_pixel;
+ info->var.blue.msb_right = 0;
+
+ info->var.transp.offset = 0;
+ info->var.transp.length = 0;
+ info->var.transp.msb_right = 0;
+
+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+ info->fix.line_length = info->var.xres_virtual /
+ (8/info->var.bits_per_pixel);
+ } else {
+ /* non-palettized */
+ index = (fbdev->panel->control_base & LCD_CONTROL_SBPPF_MASK) >> LCD_CONTROL_SBPPF_BIT;
+ info->var.red = rgb_bitfields[index][0];
+ info->var.green = rgb_bitfields[index][1];
+ info->var.blue = rgb_bitfields[index][2];
+ info->var.transp = rgb_bitfields[index][3];
+
+ info->fix.visual = FB_VISUAL_TRUECOLOR;
+ info->fix.line_length = info->var.xres_virtual << 1; /* depth=16 */
+ }
+ } else {
+ /* mono */
+ info->fix.visual = FB_VISUAL_MONO10;
+ info->fix.line_length = info->var.xres_virtual / 8;
}
- var->red.msb_right = 0;
- var->green.msb_right = 0;
- var->blue.msb_right = 0;
- var->transp.msb_right = 0;
-}
+ info->screen_size = info->fix.line_length * info->var.yres_virtual;
-static int au1100_decode_var(const struct fb_var_screeninfo *var,
- void *_par, struct fb_info_gen *_info)
-{
+ /* Determine BPP mode and format */
+ fbdev->regs->lcd_control = fbdev->panel->control_base |
+ ((info->var.rotate/90) << LCD_CONTROL_SM_BIT);
- struct au1100fb_par *par = (struct au1100fb_par *)_par;
+ fbdev->regs->lcd_intenable = 0;
+ fbdev->regs->lcd_intstatus = 0;
- /*
- * Don't allow setting any of these yet: xres and yres don't
- * make sense for LCD panels.
- */
- if (var->xres != p_lcd->xres ||
- var->yres != p_lcd->yres ||
- var->xres != p_lcd->xres ||
- var->yres != p_lcd->yres) {
- return -EINVAL;
- }
- if(var->bits_per_pixel != p_lcd->bpp) {
- return -EINVAL;
- }
+ fbdev->regs->lcd_horztiming = fbdev->panel->horztiming;
- memset(par, 0, sizeof(struct au1100fb_par));
- par->var = *var;
-
- /* FIXME */
- switch (var->bits_per_pixel) {
- case 8:
- par->var.bits_per_pixel = 8;
- break;
- case 16:
- par->var.bits_per_pixel = 16;
- break;
- default:
- printk("color depth %d bpp not supported\n",
- var->bits_per_pixel);
- return -EINVAL;
+ fbdev->regs->lcd_verttiming = fbdev->panel->verttiming;
+
+ fbdev->regs->lcd_clkcontrol = fbdev->panel->clkcontrol_base;
+ fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(fbdev->fb_phys);
+
+ if (panel_is_dual(fbdev->panel)) {
+ /* Second panel display seconf half of screen if possible,
+ * otherwise display the same as the first panel */
+ if (info->var.yres_virtual >= (info->var.yres << 1)) {
+ fbdev->regs->lcd_dmaaddr1 = LCD_DMA_SA_N(fbdev->fb_phys +
+ (info->fix.line_length *
+ (info->var.yres_virtual >> 1)));
+ } else {
+ fbdev->regs->lcd_dmaaddr1 = LCD_DMA_SA_N(fbdev->fb_phys);
+ }
}
- set_color_bitfields(&par->var);
- par->cmap_len = (par->var.bits_per_pixel == 8) ? 256 : 16;
- return 0;
-}
-static int au1100_encode_var(struct fb_var_screeninfo *var,
- const void *par, struct fb_info_gen *_info)
-{
+ words = info->fix.line_length / sizeof(u32);
+ if (!info->var.rotate || (info->var.rotate == 180)) {
+ words *= info->var.yres_virtual;
+ if (info->var.rotate /* 180 */) {
+ words -= (words % 8); /* should be divisable by 8 */
+ }
+ }
+ fbdev->regs->lcd_words = LCD_WRD_WRDS_N(words);
- *var = ((struct au1100fb_par *)par)->var;
- return 0;
-}
+ fbdev->regs->lcd_pwmdiv = 0;
+ fbdev->regs->lcd_pwmhi = 0;
-static void
-au1100_get_par(void *_par, struct fb_info_gen *_info)
-{
- *(struct au1100fb_par *)_par = current_par;
-}
+ /* Resume controller */
+ fbdev->regs->lcd_control |= LCD_CONTROL_GO;
-static void au1100_set_par(const void *par, struct fb_info_gen *info)
-{
- /* nothing to do: we don't change any settings */
+ return 0;
}
-static int au1100_getcolreg(unsigned regno, unsigned *red, unsigned *green,
- unsigned *blue, unsigned *transp,
- struct fb_info *info)
+/* fb_setcolreg
+ * Set color in LCD palette.
+ */
+int au1100fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *fbi)
{
+ struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
+ u32 *palette = fbdev->regs->lcd_pallettebase;
+ u32 value;
- struct au1100fb_info* i = (struct au1100fb_info*)info;
-
- if (regno > 255)
- return 1;
+ if (regno > (AU1100_LCD_NBR_PALETTE_ENTRIES - 1))
+ return -EINVAL;
- *red = i->palette[regno].red;
- *green = i->palette[regno].green;
- *blue = i->palette[regno].blue;
- *transp = 0;
+ if (fbi->var.grayscale) {
+ /* Convert color to grayscale */
+ red = green = blue =
+ (19595 * red + 38470 * green + 7471 * blue) >> 16;
+ }
- return 0;
-}
+ if (fbi->fix.visual == FB_VISUAL_TRUECOLOR) {
+ /* Place color in the pseudopalette */
+ if (regno > 16)
+ return -EINVAL;
-static int au1100_setcolreg(unsigned regno, unsigned red, unsigned green,
- unsigned blue, unsigned transp,
- struct fb_info *info)
-{
- struct au1100fb_info* i = (struct au1100fb_info *)info;
- u32 rgbcol;
-
- if (regno > 255)
- return 1;
-
- i->palette[regno].red = red;
- i->palette[regno].green = green;
- i->palette[regno].blue = blue;
-
- switch(p_lcd->bpp) {
-#ifdef FBCON_HAS_CFB8
- case 8:
- red >>= 10;
- green >>= 10;
- blue >>= 10;
- p_lcd_reg->lcd_pallettebase[regno] = (blue&0x1f) |
- ((green&0x3f)<<5) | ((red&0x1f)<<11);
- break;
-#endif
-#ifdef FBCON_HAS_CFB16
- case 16:
- i->fbcon_cmap16[regno] =
- ((red & 0xf800) >> 0) |
- ((green & 0xfc00) >> 5) |
- ((blue & 0xf800) >> 11);
- break;
-#endif
- default:
- break;
+ palette = (u32*)fbi->pseudo_palette;
+
+ red >>= (16 - fbi->var.red.length);
+ green >>= (16 - fbi->var.green.length);
+ blue >>= (16 - fbi->var.blue.length);
+
+ value = (red << fbi->var.red.offset) |
+ (green << fbi->var.green.offset)|
+ (blue << fbi->var.blue.offset);
+ value &= 0xFFFF;
+
+ } else if (panel_is_active(fbdev->panel)) {
+ /* COLOR TFT PALLETTIZED (use RGB 565) */
+ value = (red & 0xF800)|((green >> 5) & 0x07E0)|((blue >> 11) & 0x001F);
+ value &= 0xFFFF;
+
+ } else if (panel_is_color(fbdev->panel)) {
+ /* COLOR STN MODE */
+ value = (((panel_swap_rgb(fbdev->panel) ? blue : red) >> 12) & 0x000F) |
+ ((green >> 8) & 0x00F0) |
+ (((panel_swap_rgb(fbdev->panel) ? red : blue) >> 4) & 0x0F00);
+ value &= 0xFFF;
+ } else {
+ /* MONOCHROME MODE */
+ value = (green >> 12) & 0x000F;
+ value &= 0xF;
}
+ palette[regno] = value;
+
return 0;
}
-
-static int au1100_blank(int blank_mode, struct fb_info_gen *_info)
+/* fb_blank
+ * Blank the screen. Depending on the mode, the screen will be
+ * activated with the backlight color, or desactivated
+ */
+int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi)
{
+ struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
+
+ print_dbg("fb_blank %d %p", blank_mode, fbi);
switch (blank_mode) {
+
case VESA_NO_BLANKING:
- /* turn on panel */
- //printk("turn on panel\n");
+ /* Turn on panel */
+ fbdev->regs->lcd_control |= LCD_CONTROL_GO;
#ifdef CONFIG_MIPS_PB1100
- p_lcd_reg->lcd_control |= LCD_CONTROL_GO;
- au_writew(au_readw(PB1100_G_CONTROL) | p_lcd->mode_backlight,
+ if (drv_info.panel_idx == 1) {
+ au_writew(au_readw(PB1100_G_CONTROL)
+ | (PB1100_G_CONTROL_BL | PB1100_G_CONTROL_VDD),
PB1100_G_CONTROL);
-#endif
-#ifdef CONFIG_MIPS_HYDROGEN3
- /* Turn controller & power supply on, GPIO213 */
- au_writel(0x20002000, 0xB1700008);
- au_writel(0x00040000, 0xB1900108);
- au_writel(0x01000100, 0xB1700008);
+ }
#endif
au_sync();
break;
@@ -332,12 +292,14 @@ static int au1100_blank(int blank_mode, struct fb_info_gen *_info)
case VESA_VSYNC_SUSPEND:
case VESA_HSYNC_SUSPEND:
case VESA_POWERDOWN:
- /* turn off panel */
- //printk("turn off panel\n");
+ /* Turn off panel */
+ fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
#ifdef CONFIG_MIPS_PB1100
- au_writew(au_readw(PB1100_G_CONTROL) & ~p_lcd->mode_backlight,
+ if (drv_info.panel_idx == 1) {
+ au_writew(au_readw(PB1100_G_CONTROL)
+ & ~(PB1100_G_CONTROL_BL | PB1100_G_CONTROL_VDD),
PB1100_G_CONTROL);
- p_lcd_reg->lcd_control &= ~LCD_CONTROL_GO;
+ }
#endif
au_sync();
break;
@@ -348,49 +310,87 @@ static int au1100_blank(int blank_mode, struct fb_info_gen *_info)
return 0;
}
-static void au1100_set_disp(const void *unused, struct display *disp,
- struct fb_info_gen *info)
+/* fb_pan_display
+ * Pan display in x and/or y as specified
+ */
+int au1100fb_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi)
{
- disp->screen_base = (char *)fb_info.fb_virt_start;
-
- switch (disp->var.bits_per_pixel) {
-#ifdef FBCON_HAS_CFB8
- case 8:
- disp->dispsw = &fbcon_cfb8;
- if (fb_info.nohwcursor)
- fbcon_cfb8.cursor = au1100_nocursor;
- break;
-#endif
-#ifdef FBCON_HAS_CFB16
- case 16:
- disp->dispsw = &fbcon_cfb16;
- disp->dispsw_data = fb_info.fbcon_cmap16;
- if (fb_info.nohwcursor)
- fbcon_cfb16.cursor = au1100_nocursor;
- break;
-#endif
- default:
- disp->dispsw = &fbcon_dummy;
- disp->dispsw_data = NULL;
- break;
+ struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
+ int dy;
+
+ print_dbg("fb_pan_display %p %p", var, fbi);
+
+ if (!var || !fbdev) {
+ return -EINVAL;
+ }
+
+ if (var->xoffset - fbi->var.xoffset) {
+ /* No support for X panning for now! */
+ return -EINVAL;
+ }
+
+ print_dbg("fb_pan_display 2 %p %p", var, fbi);
+ dy = var->yoffset - fbi->var.yoffset;
+ if (dy) {
+
+ u32 dmaaddr;
+
+ print_dbg("Panning screen of %d lines", dy);
+
+ dmaaddr = fbdev->regs->lcd_dmaaddr0;
+ dmaaddr += (fbi->fix.line_length * dy);
+
+ /* TODO: Wait for current frame to finished */
+ fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr);
+
+ if (panel_is_dual(fbdev->panel)) {
+ dmaaddr = fbdev->regs->lcd_dmaaddr1;
+ dmaaddr += (fbi->fix.line_length * dy);
+ fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr);
+ }
+ }
+ print_dbg("fb_pan_display 3 %p %p", var, fbi);
+
+ return 0;
+}
+
+/* fb_rotate
+ * Rotate the display of this angle. This doesn't seems to be used by the core,
+ * but as our hardware supports it, so why not implementing it...
+ */
+void au1100fb_fb_rotate(struct fb_info *fbi, int angle)
+{
+ struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
+
+ print_dbg("fb_rotate %p %d", fbi, angle);
+
+ if (fbdev && (angle > 0) && !(angle % 90)) {
+
+ fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
+
+ fbdev->regs->lcd_control &= ~(LCD_CONTROL_SM_MASK);
+ fbdev->regs->lcd_control |= ((angle/90) << LCD_CONTROL_SM_BIT);
+
+ fbdev->regs->lcd_control |= LCD_CONTROL_GO;
}
}
-static int
-au1100fb_mmap(struct fb_info *_fb,
- struct file *file,
- struct vm_area_struct *vma)
+/* fb_mmap
+ * Map video memory in user space. We don't use the generic fb_mmap method mainly
+ * to allow the use of the TLB streaming flag (CCA=6)
+ */
+int au1100fb_fb_mmap(struct fb_info *fbi, struct file *file, struct vm_area_struct *vma)
{
+ struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
unsigned int len;
unsigned long start=0, off;
- struct au1100fb_info *fb = (struct au1100fb_info *)_fb;
if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) {
return -EINVAL;
}
- start = fb_info.fb_phys & PAGE_MASK;
- len = PAGE_ALIGN((start & ~PAGE_MASK) + fb_info.fb_size);
+ start = fbdev->fb_phys & PAGE_MASK;
+ len = PAGE_ALIGN((start & ~PAGE_MASK) + fbdev->fb_len);
off = vma->vm_pgoff << PAGE_SHIFT;
@@ -401,276 +401,309 @@ au1100fb_mmap(struct fb_info *_fb,
off += start;
vma->vm_pgoff = off >> PAGE_SHIFT;
- pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK;
- //pgprot_val(vma->vm_page_prot) |= _CACHE_CACHABLE_NONCOHERENT;
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
pgprot_val(vma->vm_page_prot) |= (6 << 9); //CCA=6
- /* This is an IO map - tell maydump to skip this VMA */
vma->vm_flags |= VM_IO;
- if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
+ if (io_remap_page_range(vma, vma->vm_start, off,
vma->vm_end - vma->vm_start,
vma->vm_page_prot)) {
return -EAGAIN;
}
- fb->mmaped = 1;
return 0;
}
-int au1100_pan_display(const struct fb_var_screeninfo *var,
- struct fb_info_gen *info)
+static struct fb_ops au1100fb_ops =
{
- return 0;
-}
+ .owner = THIS_MODULE,
+ .fb_setcolreg = au1100fb_fb_setcolreg,
+ .fb_blank = au1100fb_fb_blank,
+ .fb_pan_display = au1100fb_fb_pan_display,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+ .fb_rotate = au1100fb_fb_rotate,
+ .fb_mmap = au1100fb_fb_mmap,
+};
-static int au1100fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
- u_long arg, int con, struct fb_info *info)
-{
- /* nothing to do yet */
- return -EINVAL;
-}
-static struct fbgen_hwswitch au1100_switch = {
- au1100_detect,
- au1100_encode_fix,
- au1100_decode_var,
- au1100_encode_var,
- au1100_get_par,
- au1100_set_par,
- au1100_getcolreg,
- au1100_setcolreg,
- au1100_pan_display,
- au1100_blank,
- au1100_set_disp
-};
+/*-------------------------------------------------------------------------*/
+/* AU1100 LCD controller device driver */
-int au1100_setmode(void)
+int au1100fb_drv_probe(struct device *dev)
{
- int words;
-
- /* FIXME Need to accomodate for swivel mode and 12bpp, <8bpp*/
- switch (p_lcd->mode_control & LCD_CONTROL_SM)
- {
- case LCD_CONTROL_SM_0:
- case LCD_CONTROL_SM_180:
- words = (p_lcd->xres * p_lcd->yres * p_lcd->bpp) / 32;
- break;
- case LCD_CONTROL_SM_90:
- case LCD_CONTROL_SM_270:
- /* is this correct? */
- words = (p_lcd->xres * p_lcd->bpp) / 8;
- break;
- default:
- printk("mode_control reg not initialized\n");
+ struct au1100fb_device *fbdev = NULL;
+ struct resource *regs_res;
+ unsigned long page;
+ u32 sys_clksrc;
+
+ if (!dev)
return -EINVAL;
+
+ /* Allocate new device private */
+ if (!(fbdev = kmalloc(sizeof(struct au1100fb_device), GFP_KERNEL))) {
+ print_err("fail to allocate device private record");
+ return -ENOMEM;
}
+ memset((void*)fbdev, 0, sizeof(struct au1100fb_device));
- /*
- * Setup LCD controller
- */
+ fbdev->panel = &known_lcd_panels[drv_info.panel_idx];
- p_lcd_reg->lcd_control = p_lcd->mode_control;
- p_lcd_reg->lcd_intstatus = 0;
- p_lcd_reg->lcd_intenable = 0;
- p_lcd_reg->lcd_horztiming = p_lcd->mode_horztiming;
- p_lcd_reg->lcd_verttiming = p_lcd->mode_verttiming;
- p_lcd_reg->lcd_clkcontrol = p_lcd->mode_clkcontrol;
- p_lcd_reg->lcd_words = words - 1;
- p_lcd_reg->lcd_dmaaddr0 = fb_info.fb_phys;
+ dev_set_drvdata(dev, (void*)fbdev);
- /* turn on panel */
-#ifdef CONFIG_MIPS_PB1100
- au_writew(au_readw(PB1100_G_CONTROL) | p_lcd->mode_backlight,
- PB1100_G_CONTROL);
-#endif
-#ifdef CONFIG_MIPS_HYDROGEN3
- /* Turn controller & power supply on, GPIO213 */
- au_writel(0x20002000, 0xB1700008);
- au_writel(0x00040000, 0xB1900108);
- au_writel(0x01000100, 0xB1700008);
-#endif
+ /* Allocate region for our registers and map them */
+ if (!(regs_res = platform_get_resource(to_platform_device(dev),
+ IORESOURCE_MEM, 0))) {
+ print_err("fail to retrieve registers resource");
+ return -EFAULT;
+ }
- p_lcd_reg->lcd_control |= LCD_CONTROL_GO;
+ au1100fb_fix.mmio_start = regs_res->start;
+ au1100fb_fix.mmio_len = regs_res->end - regs_res->start + 1;
- return 0;
-}
+ if (!request_mem_region(au1100fb_fix.mmio_start, au1100fb_fix.mmio_len,
+ DRIVER_NAME)) {
+ print_err("fail to lock memory region at 0x%08x",
+ au1100fb_fix.mmio_start);
+ return -EBUSY;
+ }
+ fbdev->regs = (struct au1100fb_regs*)KSEG1ADDR(au1100fb_fix.mmio_start);
-int __init au1100fb_init(void)
-{
- uint32 sys_clksrc;
- unsigned long page;
+ print_dbg("Register memory map at %p", fbdev->regs);
+ print_dbg("phys=0x%08x, size=%d", fbdev->regs_phys, fbdev->regs_len);
- /*
- * Get the panel information/display mode and update the registry
- */
- p_lcd = &panels[my_lcd_index];
-
- switch (p_lcd->mode_control & LCD_CONTROL_SM)
- {
- case LCD_CONTROL_SM_0:
- case LCD_CONTROL_SM_180:
- p_lcd->xres =
- (p_lcd->mode_horztiming & LCD_HORZTIMING_PPL) + 1;
- p_lcd->yres =
- (p_lcd->mode_verttiming & LCD_VERTTIMING_LPP) + 1;
- break;
- case LCD_CONTROL_SM_90:
- case LCD_CONTROL_SM_270:
- p_lcd->yres =
- (p_lcd->mode_horztiming & LCD_HORZTIMING_PPL) + 1;
- p_lcd->xres =
- (p_lcd->mode_verttiming & LCD_VERTTIMING_LPP) + 1;
- break;
- }
- /*
- * Panel dimensions x bpp must be divisible by 32
- */
- if (((p_lcd->yres * p_lcd->bpp) % 32) != 0)
- printk("VERT %% 32\n");
- if (((p_lcd->xres * p_lcd->bpp) % 32) != 0)
- printk("HORZ %% 32\n");
- /*
- * Allocate LCD framebuffer from system memory
- */
- fb_info.fb_size = (p_lcd->xres * p_lcd->yres * p_lcd->bpp) / 8;
-
- current_par.var.xres = p_lcd->xres;
- current_par.var.xres_virtual = p_lcd->xres;
- current_par.var.yres = p_lcd->yres;
- current_par.var.yres_virtual = p_lcd->yres;
- current_par.var.bits_per_pixel = p_lcd->bpp;
-
- /* FIX!!! only works for 8/16 bpp */
- current_par.line_length = p_lcd->xres * p_lcd->bpp / 8; /* in bytes */
- fb_info.fb_virt_start = (unsigned long )
- __get_free_pages(GFP_ATOMIC | GFP_DMA,
- get_order(fb_info.fb_size + 0x1000));
- if (!fb_info.fb_virt_start) {
- printk("Unable to allocate fb memory\n");
+ /* Allocate the framebuffer to the maximum screen size * nbr of video buffers */
+ fbdev->fb_len = fbdev->panel->xres * fbdev->panel->yres *
+ (fbdev->panel->bpp >> 3) * AU1100FB_NBR_VIDEO_BUFFERS;
+
+ fbdev->fb_mem = dma_alloc_coherent(dev, PAGE_ALIGN(fbdev->fb_len),
+ &fbdev->fb_phys, GFP_KERNEL);
+ if (!fbdev->fb_mem) {
+ print_err("fail to allocate frambuffer (size: %dK))",
+ fbdev->fb_len / 1024);
return -ENOMEM;
}
- fb_info.fb_phys = virt_to_bus((void *)fb_info.fb_virt_start);
+
+ au1100fb_fix.smem_start = fbdev->fb_phys;
+ au1100fb_fix.smem_len = fbdev->fb_len;
/*
* Set page reserved so that mmap will work. This is necessary
* since we'll be remapping normal memory.
*/
- for (page = fb_info.fb_virt_start;
- page < PAGE_ALIGN(fb_info.fb_virt_start + fb_info.fb_size);
+ for (page = (unsigned long)fbdev->fb_mem;
+ page < PAGE_ALIGN((unsigned long)fbdev->fb_mem + fbdev->fb_len);
page += PAGE_SIZE) {
+#if CONFIG_DMA_NONCOHERENT
+ SetPageReserved(virt_to_page(CAC_ADDR(page)));
+#else
SetPageReserved(virt_to_page(page));
+#endif
}
- memset((void *)fb_info.fb_virt_start, 0, fb_info.fb_size);
-
- /* set freqctrl now to allow more time to stabilize */
- /* zero-out out LCD bits */
- sys_clksrc = au_readl(SYS_CLKSRC) & ~0x000003e0;
- sys_clksrc |= p_lcd->mode_toyclksrc;
- au_writel(sys_clksrc, SYS_CLKSRC);
-
- /* FIXME add check to make sure auxpll is what is expected! */
- au1100_setmode();
-
- fb_info.gen.parsize = sizeof(struct au1100fb_par);
- fb_info.gen.fbhw = &au1100_switch;
-
- strcpy(fb_info.gen.info.modename, "Au1100 LCD");
- fb_info.gen.info.changevar = NULL;
- fb_info.gen.info.node = -1;
-
- fb_info.gen.info.fbops = &au1100fb_ops;
- fb_info.gen.info.disp = &disp;
- fb_info.gen.info.switch_con = &fbgen_switch;
- fb_info.gen.info.updatevar = &fbgen_update_var;
- fb_info.gen.info.blank = &fbgen_blank;
- fb_info.gen.info.flags = FBINFO_FLAG_DEFAULT;
-
- /* This should give a reasonable default video mode */
- fbgen_get_var(&disp.var, -1, &fb_info.gen.info);
- fbgen_do_set_var(&disp.var, 1, &fb_info.gen);
- fbgen_set_disp(-1, &fb_info.gen);
- fbgen_install_cmap(0, &fb_info.gen);
- if (register_framebuffer(&fb_info.gen.info) < 0)
- return -EINVAL;
- printk(KERN_INFO "fb%d: %s frame buffer device\n",
- GET_FB_IDX(fb_info.gen.info.node),
- fb_info.gen.info.modename);
+ print_dbg("Framebuffer memory map at %p", fbdev->fb_mem);
+ print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024);
+
+ /* Setup LCD clock to AUX (48 MHz) */
+ sys_clksrc = au_readl(SYS_CLKSRC) & ~(SYS_CS_ML_MASK | SYS_CS_DL | SYS_CS_CL);
+ au_writel((sys_clksrc | (1 << SYS_CS_ML_BIT)), SYS_CLKSRC);
+
+ /* load the panel info into the var struct */
+ au1100fb_var.bits_per_pixel = fbdev->panel->bpp;
+ au1100fb_var.xres = fbdev->panel->xres;
+ au1100fb_var.xres_virtual = au1100fb_var.xres;
+ au1100fb_var.yres = fbdev->panel->yres;
+ au1100fb_var.yres_virtual = au1100fb_var.yres;
+
+ fbdev->info.screen_base = fbdev->fb_mem;
+ fbdev->info.fbops = &au1100fb_ops;
+ fbdev->info.fix = au1100fb_fix;
+
+ if (!(fbdev->info.pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL))) {
+ return -ENOMEM;
+ }
+ memset(fbdev->info.pseudo_palette, 0, sizeof(u32) * 16);
+
+ if (fb_alloc_cmap(&fbdev->info.cmap, AU1100_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
+ print_err("Fail to allocate colormap (%d entries)",
+ AU1100_LCD_NBR_PALETTE_ENTRIES);
+ kfree(fbdev->info.pseudo_palette);
+ return -EFAULT;
+ }
+
+ fbdev->info.var = au1100fb_var;
+
+ /* Set h/w registers */
+ au1100fb_setmode(fbdev);
+
+ /* Register new framebuffer */
+ if (register_framebuffer(&fbdev->info) < 0) {
+ print_err("cannot register new framebuffer");
+ goto failed;
+ }
+
+ return 0;
+
+failed:
+ if (fbdev->regs) {
+ release_mem_region(fbdev->regs_phys, fbdev->regs_len);
+ }
+ if (fbdev->fb_mem) {
+ dma_free_noncoherent(dev, fbdev->fb_len, fbdev->fb_mem, fbdev->fb_phys);
+ }
+ if (fbdev->info.cmap.len != 0) {
+ fb_dealloc_cmap(&fbdev->info.cmap);
+ }
+ kfree(fbdev);
+ dev_set_drvdata(dev, NULL);
return 0;
}
+int au1100fb_drv_remove(struct device *dev)
+{
+ struct au1100fb_device *fbdev = NULL;
+
+ if (!dev)
+ return -ENODEV;
+
+ fbdev = (struct au1100fb_device*) dev_get_drvdata(dev);
+
+#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
+ au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info);
+#endif
+ fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
-void au1100fb_cleanup(struct fb_info *info)
+ /* Clean up all probe data */
+ unregister_framebuffer(&fbdev->info);
+
+ release_mem_region(fbdev->regs_phys, fbdev->regs_len);
+
+ dma_free_coherent(dev, PAGE_ALIGN(fbdev->fb_len), fbdev->fb_mem, fbdev->fb_phys);
+
+ fb_dealloc_cmap(&fbdev->info.cmap);
+ kfree(fbdev->info.pseudo_palette);
+ kfree((void*)fbdev);
+
+ return 0;
+}
+
+int au1100fb_drv_suspend(struct device *dev, u32 state, u32 level)
+{
+ /* TODO */
+ return 0;
+}
+
+int au1100fb_drv_resume(struct device *dev, u32 level)
{
- unregister_framebuffer(info);
+ /* TODO */
+ return 0;
}
+static struct device_driver au1100fb_driver = {
+ .name = "au1100-lcd",
+ .bus = &platform_bus_type,
-void au1100fb_setup(char *options, int *ints)
+ .probe = au1100fb_drv_probe,
+ .remove = au1100fb_drv_remove,
+ .suspend = au1100fb_drv_suspend,
+ .resume = au1100fb_drv_resume,
+};
+
+/*-------------------------------------------------------------------------*/
+
+/* Kernel driver */
+
+int au1100fb_setup(char *options)
{
char* this_opt;
- int i;
- int num_panels = sizeof(panels)/sizeof(struct known_lcd_panels);
+ int num_panels = ARRAY_SIZE(known_lcd_panels);
+ char* mode = NULL;
+ int panel_idx = 0;
+ if (num_panels <= 0) {
+ print_err("No LCD panels supported by driver!");
+ return -EFAULT;
+ }
- if (!options || !*options)
- return;
-
- for(this_opt=strtok(options, ","); this_opt;
- this_opt=strtok(NULL, ",")) {
+ if (options) {
+ while ((this_opt = strsep(&options,",")) != NULL) {
+ /* Panel option */
if (!strncmp(this_opt, "panel:", 6)) {
-#if defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100)
- /* Read Pb1100 Switch S10 ? */
- if (!strncmp(this_opt+6, "s10", 3))
- {
- int panel;
- panel = *(volatile int *)0xAE000008; /* BCSR SWITCHES */
- panel >>= 8;
- panel &= 0x0F;
- if (panel >= num_panels) panel = 0;
- my_lcd_index = panel;
- }
- else
-#endif
- /* Get the panel name, everything else if fixed */
- for (i=0; i<num_panels; i++) {
- if (!strncmp(this_opt+6, panels[i].panel_name,
+ int i;
+ this_opt += 6;
+ for (i = 0; i < num_panels; i++) {
+ if (!strncmp(this_opt,
+ known_lcd_panels[i].name,
strlen(this_opt))) {
- my_lcd_index = i;
+ panel_idx = i;
break;
}
}
+ if (i >= num_panels) {
+ print_warn("Panel %s not supported!", this_opt);
+ }
+ }
+ /* Mode option (only option that start with digit) */
+ else if (isdigit(this_opt[0])) {
+ mode = kmalloc(strlen(this_opt) + 1, GFP_KERNEL);
+ strncpy(mode, this_opt, strlen(this_opt) + 1);
+ }
+ /* Unsupported option */
+ else {
+ print_warn("Unsupported option \"%s\"", this_opt);
}
- else if (!strncmp(this_opt, "nohwcursor", 10)) {
- printk("nohwcursor\n");
- fb_info.nohwcursor = 1;
}
}
- printk("au1100fb: Panel %d %s\n", my_lcd_index,
- panels[my_lcd_index].panel_name);
-}
+ drv_info.panel_idx = panel_idx;
+ drv_info.opt_mode = mode;
+ print_info("Panel=%s Mode=%s",
+ known_lcd_panels[drv_info.panel_idx].name,
+ drv_info.opt_mode ? drv_info.opt_mode : "default");
+ return 0;
+}
-#ifdef MODULE
-MODULE_LICENSE("GPL");
-int init_module(void)
+int __init au1100fb_init(void)
{
- return au1100fb_init();
+ char* options;
+ int ret;
+
+ print_info("" DRIVER_DESC "");
+
+ memset(&drv_info, 0, sizeof(drv_info));
+
+ if (fb_get_options(DRIVER_NAME, &options))
+ return -ENODEV;
+
+ /* Setup driver with options */
+ ret = au1100fb_setup(options);
+ if (ret < 0) {
+ print_err("Fail to setup driver");
+ return ret;
+ }
+
+ return driver_register(&au1100fb_driver);
}
-void cleanup_module(void)
+void __exit au1100fb_cleanup(void)
{
- au1100fb_cleanup(void);
+ driver_unregister(&au1100fb_driver);
+
+ if (drv_info.opt_mode)
+ kfree(drv_info.opt_mode);
}
-MODULE_AUTHOR("Pete Popov <ppopov@mvista.com>");
-MODULE_DESCRIPTION("Au1100 LCD framebuffer device driver");
-#endif /* MODULE */
+module_init(au1100fb_init);
+module_exit(au1100fb_cleanup);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/au1100fb.h b/drivers/video/au1100fb.h
index 657c560ab73..2855534dc23 100644
--- a/drivers/video/au1100fb.h
+++ b/drivers/video/au1100fb.h
@@ -30,352 +30,352 @@
#ifndef _AU1100LCD_H
#define _AU1100LCD_H
+#include <asm/mach-au1x00/au1000.h>
+
+#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
+#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
+#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
+
+#if DEBUG
+#define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg)
+#else
+#define print_dbg(f, arg...) do {} while (0)
+#endif
+
+#if defined(__BIG_ENDIAN)
+#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
+#else
+#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
+#endif
+#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
+
/********************************************************************/
-#define uint32 unsigned long
-typedef volatile struct
-{
- uint32 lcd_control;
- uint32 lcd_intstatus;
- uint32 lcd_intenable;
- uint32 lcd_horztiming;
- uint32 lcd_verttiming;
- uint32 lcd_clkcontrol;
- uint32 lcd_dmaaddr0;
- uint32 lcd_dmaaddr1;
- uint32 lcd_words;
- uint32 lcd_pwmdiv;
- uint32 lcd_pwmhi;
- uint32 reserved[(0x0400-0x002C)/4];
- uint32 lcd_pallettebase[256];
-
-} AU1100_LCD;
+
+/* LCD controller restrictions */
+#define AU1100_LCD_MAX_XRES 800
+#define AU1100_LCD_MAX_YRES 600
+#define AU1100_LCD_MAX_BPP 16
+#define AU1100_LCD_MAX_CLK 48000000
+#define AU1100_LCD_NBR_PALETTE_ENTRIES 256
+
+/* Default number of visible screen buffer to allocate */
+#define AU1100FB_NBR_VIDEO_BUFFERS 4
/********************************************************************/
-#define AU1100_LCD_ADDR 0xB5000000
+struct au1100fb_panel
+{
+ const char name[25]; /* Full name <vendor>_<model> */
-/*
- * Register bit definitions
- */
+ u32 control_base; /* Mode-independent control values */
+ u32 clkcontrol_base; /* Panel pixclock preferences */
-/* lcd_control */
-#define LCD_CONTROL_SBPPF (7<<18)
-#define LCD_CONTROL_SBPPF_655 (0<<18)
-#define LCD_CONTROL_SBPPF_565 (1<<18)
-#define LCD_CONTROL_SBPPF_556 (2<<18)
-#define LCD_CONTROL_SBPPF_1555 (3<<18)
-#define LCD_CONTROL_SBPPF_5551 (4<<18)
-#define LCD_CONTROL_WP (1<<17)
-#define LCD_CONTROL_WD (1<<16)
-#define LCD_CONTROL_C (1<<15)
-#define LCD_CONTROL_SM (3<<13)
-#define LCD_CONTROL_SM_0 (0<<13)
-#define LCD_CONTROL_SM_90 (1<<13)
-#define LCD_CONTROL_SM_180 (2<<13)
-#define LCD_CONTROL_SM_270 (3<<13)
-#define LCD_CONTROL_DB (1<<12)
-#define LCD_CONTROL_CCO (1<<11)
-#define LCD_CONTROL_DP (1<<10)
-#define LCD_CONTROL_PO (3<<8)
-#define LCD_CONTROL_PO_00 (0<<8)
-#define LCD_CONTROL_PO_01 (1<<8)
-#define LCD_CONTROL_PO_10 (2<<8)
-#define LCD_CONTROL_PO_11 (3<<8)
-#define LCD_CONTROL_MPI (1<<7)
-#define LCD_CONTROL_PT (1<<6)
-#define LCD_CONTROL_PC (1<<5)
-#define LCD_CONTROL_BPP (7<<1)
-#define LCD_CONTROL_BPP_1 (0<<1)
-#define LCD_CONTROL_BPP_2 (1<<1)
-#define LCD_CONTROL_BPP_4 (2<<1)
-#define LCD_CONTROL_BPP_8 (3<<1)
-#define LCD_CONTROL_BPP_12 (4<<1)
-#define LCD_CONTROL_BPP_16 (5<<1)
-#define LCD_CONTROL_GO (1<<0)
-
-/* lcd_intstatus, lcd_intenable */
-#define LCD_INT_SD (1<<7)
-#define LCD_INT_OF (1<<6)
-#define LCD_INT_UF (1<<5)
-#define LCD_INT_SA (1<<3)
-#define LCD_INT_SS (1<<2)
-#define LCD_INT_S1 (1<<1)
-#define LCD_INT_S0 (1<<0)
-
-/* lcd_horztiming */
-#define LCD_HORZTIMING_HN2 (255<<24)
-#define LCD_HORZTIMING_HN2_N(N) (((N)-1)<<24)
-#define LCD_HORZTIMING_HN1 (255<<16)
-#define LCD_HORZTIMING_HN1_N(N) (((N)-1)<<16)
-#define LCD_HORZTIMING_HPW (63<<10)
-#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<10)
-#define LCD_HORZTIMING_PPL (1023<<0)
-#define LCD_HORZTIMING_PPL_N(N) (((N)-1)<<0)
-
-/* lcd_verttiming */
-#define LCD_VERTTIMING_VN2 (255<<24)
-#define LCD_VERTTIMING_VN2_N(N) (((N)-1)<<24)
-#define LCD_VERTTIMING_VN1 (255<<16)
-#define LCD_VERTTIMING_VN1_N(N) (((N)-1)<<16)
-#define LCD_VERTTIMING_VPW (63<<10)
-#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<10)
-#define LCD_VERTTIMING_LPP (1023<<0)
-#define LCD_VERTTIMING_LPP_N(N) (((N)-1)<<0)
-
-/* lcd_clkcontrol */
-#define LCD_CLKCONTROL_IB (1<<18)
-#define LCD_CLKCONTROL_IC (1<<17)
-#define LCD_CLKCONTROL_IH (1<<16)
-#define LCD_CLKCONTROL_IV (1<<15)
-#define LCD_CLKCONTROL_BF (31<<10)
-#define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10)
-#define LCD_CLKCONTROL_PCD (1023<<0)
-#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0)
-
-/* lcd_pwmdiv */
-#define LCD_PWMDIV_EN (1<<12)
-#define LCD_PWMDIV_PWMDIV (2047<<0)
-#define LCD_PWMDIV_PWMDIV_N(N) (((N)-1)<<0)
-
-/* lcd_pwmhi */
-#define LCD_PWMHI_PWMHI1 (2047<<12)
-#define LCD_PWMHI_PWMHI1_N(N) ((N)<<12)
-#define LCD_PWMHI_PWMHI0 (2047<<0)
-#define LCD_PWMHI_PWMHI0_N(N) ((N)<<0)
-
-/* lcd_pallettebase - MONOCHROME */
-#define LCD_PALLETTE_MONO_MI (15<<0)
-#define LCD_PALLETTE_MONO_MI_N(N) ((N)<<0)
-
-/* lcd_pallettebase - COLOR */
-#define LCD_PALLETTE_COLOR_BI (15<<8)
-#define LCD_PALLETTE_COLOR_BI_N(N) ((N)<<8)
-#define LCD_PALLETTE_COLOR_GI (15<<4)
-#define LCD_PALLETTE_COLOR_GI_N(N) ((N)<<4)
-#define LCD_PALLETTE_COLOR_RI (15<<0)
-#define LCD_PALLETTE_COLOR_RI_N(N) ((N)<<0)
-
-/* lcd_palletebase - COLOR TFT PALLETIZED */
-#define LCD_PALLETTE_TFT_DC (65535<<0)
-#define LCD_PALLETTE_TFT_DC_N(N) ((N)<<0)
+ u32 horztiming;
+ u32 verttiming;
-/********************************************************************/
+ u32 xres; /* Maximum horizontal resolution */
+ u32 yres; /* Maximum vertical resolution */
+ u32 bpp; /* Maximum depth supported */
+};
-struct known_lcd_panels
+struct au1100fb_regs
{
- uint32 xres;
- uint32 yres;
- uint32 bpp;
- unsigned char panel_name[256];
- uint32 mode_control;
- uint32 mode_horztiming;
- uint32 mode_verttiming;
- uint32 mode_clkcontrol;
- uint32 mode_pwmdiv;
- uint32 mode_pwmhi;
- uint32 mode_toyclksrc;
- uint32 mode_backlight;
+ u32 lcd_control;
+ u32 lcd_intstatus;
+ u32 lcd_intenable;
+ u32 lcd_horztiming;
+ u32 lcd_verttiming;
+ u32 lcd_clkcontrol;
+ u32 lcd_dmaaddr0;
+ u32 lcd_dmaaddr1;
+ u32 lcd_words;
+ u32 lcd_pwmdiv;
+ u32 lcd_pwmhi;
+ u32 reserved[(0x0400-0x002C)/4];
+ u32 lcd_pallettebase[256];
+};
+
+struct au1100fb_device {
+
+ struct fb_info info; /* FB driver info record */
+ struct au1100fb_panel *panel; /* Panel connected to this device */
+
+ struct au1100fb_regs* regs; /* Registers memory map */
+ size_t regs_len;
+ unsigned int regs_phys;
+
+ unsigned char* fb_mem; /* FrameBuffer memory map */
+ size_t fb_len;
+ dma_addr_t fb_phys;
};
-#if defined(__BIG_ENDIAN)
-#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_11
-#else
-#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_00
-#endif
+/********************************************************************/
-/*
- * The fb driver assumes that AUX PLL is at 48MHz. That can
- * cover up to 800x600 resolution; if you need higher resolution,
- * you should modify the driver as needed, not just this structure.
+#define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
+ #define LCD_CONTROL_SBB_BIT 21
+ #define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
+ #define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
+ #define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
+ #define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
+ #define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
+ #define LCD_CONTROL_SBPPF_BIT 18
+ #define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
+ #define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
+ #define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
+ #define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
+ #define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
+ #define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
+ #define LCD_CONTROL_WP (1<<17)
+ #define LCD_CONTROL_WD (1<<16)
+ #define LCD_CONTROL_C (1<<15)
+ #define LCD_CONTROL_SM_BIT 13
+ #define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
+ #define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
+ #define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
+ #define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
+ #define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
+ #define LCD_CONTROL_DB (1<<12)
+ #define LCD_CONTROL_CCO (1<<11)
+ #define LCD_CONTROL_DP (1<<10)
+ #define LCD_CONTROL_PO_BIT 8
+ #define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
+ #define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
+ #define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
+ #define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
+ #define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
+ #define LCD_CONTROL_MPI (1<<7)
+ #define LCD_CONTROL_PT (1<<6)
+ #define LCD_CONTROL_PC (1<<5)
+ #define LCD_CONTROL_BPP_BIT 1
+ #define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
+ #define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
+ #define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
+ #define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
+ #define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
+ #define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
+ #define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
+ #define LCD_CONTROL_GO (1<<0)
+
+#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
+#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
+ #define LCD_INT_SD (1<<7)
+ #define LCD_INT_OF (1<<6)
+ #define LCD_INT_UF (1<<5)
+ #define LCD_INT_SA (1<<3)
+ #define LCD_INT_SS (1<<2)
+ #define LCD_INT_S1 (1<<1)
+ #define LCD_INT_S0 (1<<0)
+
+#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
+ #define LCD_HORZTIMING_HN2_BIT 24
+ #define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
+ #define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
+ #define LCD_HORZTIMING_HN1_BIT 16
+ #define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
+ #define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
+ #define LCD_HORZTIMING_HPW_BIT 10
+ #define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
+ #define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
+ #define LCD_HORZTIMING_PPL_BIT 0
+ #define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
+ #define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
+
+#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
+ #define LCD_VERTTIMING_VN2_BIT 24
+ #define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
+ #define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
+ #define LCD_VERTTIMING_VN1_BIT 16
+ #define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
+ #define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
+ #define LCD_VERTTIMING_VPW_BIT 10
+ #define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
+ #define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
+ #define LCD_VERTTIMING_LPP_BIT 0
+ #define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
+ #define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
+
+#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
+ #define LCD_CLKCONTROL_IB (1<<18)
+ #define LCD_CLKCONTROL_IC (1<<17)
+ #define LCD_CLKCONTROL_IH (1<<16)
+ #define LCD_CLKCONTROL_IV (1<<15)
+ #define LCD_CLKCONTROL_BF_BIT 10
+ #define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
+ #define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
+ #define LCD_CLKCONTROL_PCD_BIT 0
+ #define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
+ #define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
+
+#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
+#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
+ #define LCD_DMA_SA_BIT 5
+ #define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
+ #define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
+
+#define LCD_WORDS (AU1100_LCD_BASE + 0x20)
+ #define LCD_WRD_WRDS_BIT 0
+ #define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
+ #define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
+
+#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
+ #define LCD_PWMDIV_EN (1<<12)
+ #define LCD_PWMDIV_PWMDIV_BIT 0
+ #define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
+ #define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
+
+#define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
+ #define LCD_PWMHI_PWMHI1_BIT 12
+ #define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
+ #define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
+ #define LCD_PWMHI_PWMHI0_BIT 0
+ #define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
+ #define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
+
+#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
+ #define LCD_PALLETTE_MONO_MI_BIT 0
+ #define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
+ #define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
+
+ #define LCD_PALLETTE_COLOR_RI_BIT 8
+ #define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
+ #define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
+ #define LCD_PALLETTE_COLOR_GI_BIT 4
+ #define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
+ #define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
+ #define LCD_PALLETTE_COLOR_BI_BIT 0
+ #define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
+ #define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
+
+ #define LCD_PALLETTE_TFT_DC_BIT 0
+ #define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
+ #define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
+
+/********************************************************************/
+
+/* List of panels known to work with the AU1100 LCD controller.
+ * To add a new panel, enter the same specifications as the
+ * Generic_TFT one, and MAKE SURE that it doesn't conflicts
+ * with the controller restrictions. Restrictions are:
+ *
+ * STN color panels: max_bpp <= 12
+ * STN mono panels: max_bpp <= 4
+ * TFT panels: max_bpp <= 16
+ * max_xres <= 800
+ * max_yres <= 600
*/
-struct known_lcd_panels panels[] =
+static struct au1100fb_panel known_lcd_panels[] =
{
- { /* 0: Pb1100 LCDA: Sharp 320x240 TFT panel */
- 320, /* xres */
- 240, /* yres */
- 16, /* bpp */
-
- "Sharp_320x240_16",
- /* mode_control */
+ /* 800x600x16bpp CRT */
+ [0] = {
+ .name = "CRT_800x600_16",
+ .xres = 800,
+ .yres = 600,
+ .bpp = 16,
+ .control_base = 0x0004886A |
+ LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
+ LCD_CONTROL_BPP_16,
+ .clkcontrol_base = 0x00020000,
+ .horztiming = 0x005aff1f,
+ .verttiming = 0x16000e57,
+ },
+ /* just the standard LCD */
+ [1] = {
+ .name = "WWPC LCD",
+ .xres = 240,
+ .yres = 320,
+ .bpp = 16,
+ .control_base = 0x0006806A,
+ .horztiming = 0x0A1010EF,
+ .verttiming = 0x0301013F,
+ .clkcontrol_base = 0x00018001,
+ },
+ /* Sharp 320x240 TFT panel */
+ [2] = {
+ .name = "Sharp_LQ038Q5DR01",
+ .xres = 320,
+ .yres = 240,
+ .bpp = 16,
+ .control_base =
( LCD_CONTROL_SBPPF_565
- /*LCD_CONTROL_WP*/
- /*LCD_CONTROL_WD*/
| LCD_CONTROL_C
| LCD_CONTROL_SM_0
- /*LCD_CONTROL_DB*/
- /*LCD_CONTROL_CCO*/
- /*LCD_CONTROL_DP*/
- | LCD_DEFAULT_PIX_FORMAT
- /*LCD_CONTROL_MPI*/
+ | LCD_CONTROL_DEFAULT_PO
| LCD_CONTROL_PT
| LCD_CONTROL_PC
| LCD_CONTROL_BPP_16 ),
-
- /* mode_horztiming */
+ .horztiming =
( LCD_HORZTIMING_HN2_N(8)
| LCD_HORZTIMING_HN1_N(60)
| LCD_HORZTIMING_HPW_N(12)
| LCD_HORZTIMING_PPL_N(320) ),
-
- /* mode_verttiming */
+ .verttiming =
( LCD_VERTTIMING_VN2_N(5)
| LCD_VERTTIMING_VN1_N(17)
| LCD_VERTTIMING_VPW_N(1)
| LCD_VERTTIMING_LPP_N(240) ),
-
- /* mode_clkcontrol */
- ( 0
- /*LCD_CLKCONTROL_IB*/
- /*LCD_CLKCONTROL_IC*/
- /*LCD_CLKCONTROL_IH*/
- /*LCD_CLKCONTROL_IV*/
- | LCD_CLKCONTROL_PCD_N(1) ),
-
- /* mode_pwmdiv */
- 0,
-
- /* mode_pwmhi */
- 0,
-
- /* mode_toyclksrc */
- ((1<<7) | (1<<6) | (1<<5)),
-
- /* mode_backlight */
- 6
+ .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
},
- { /* 1: Pb1100 LCDC 640x480 TFT panel */
- 640, /* xres */
- 480, /* yres */
- 16, /* bpp */
-
- "Generic_640x480_16",
-
- /* mode_control */
- 0x004806a | LCD_DEFAULT_PIX_FORMAT,
-
- /* mode_horztiming */
- 0x3434d67f,
-
- /* mode_verttiming */
- 0x0e0e39df,
-
- /* mode_clkcontrol */
- ( 0
- /*LCD_CLKCONTROL_IB*/
- /*LCD_CLKCONTROL_IC*/
- /*LCD_CLKCONTROL_IH*/
- /*LCD_CLKCONTROL_IV*/
- | LCD_CLKCONTROL_PCD_N(1) ),
-
- /* mode_pwmdiv */
- 0,
-
- /* mode_pwmhi */
- 0,
-
- /* mode_toyclksrc */
- ((1<<7) | (1<<6) | (0<<5)),
-
- /* mode_backlight */
- 7
+ /* Hitachi SP14Q005 and possibly others */
+ [3] = {
+ .name = "Hitachi_SP14Qxxx",
+ .xres = 320,
+ .yres = 240,
+ .bpp = 4,
+ .control_base =
+ ( LCD_CONTROL_C
+ | LCD_CONTROL_BPP_4 ),
+ .horztiming =
+ ( LCD_HORZTIMING_HN2_N(1)
+ | LCD_HORZTIMING_HN1_N(1)
+ | LCD_HORZTIMING_HPW_N(1)
+ | LCD_HORZTIMING_PPL_N(320) ),
+ .verttiming =
+ ( LCD_VERTTIMING_VN2_N(1)
+ | LCD_VERTTIMING_VN1_N(1)
+ | LCD_VERTTIMING_VPW_N(1)
+ | LCD_VERTTIMING_LPP_N(240) ),
+ .clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
},
- { /* 2: Pb1100 LCDB 640x480 PrimeView TFT panel */
- 640, /* xres */
- 480, /* yres */
- 16, /* bpp */
-
- "PrimeView_640x480_16",
-
- /* mode_control */
- 0x0004886a | LCD_DEFAULT_PIX_FORMAT,
-
- /* mode_horztiming */
- 0x0e4bfe7f,
-
- /* mode_verttiming */
- 0x210805df,
-
- /* mode_clkcontrol */
- 0x00038001,
-
- /* mode_pwmdiv */
- 0,
-
- /* mode_pwmhi */
- 0,
-
- /* mode_toyclksrc */
- ((1<<7) | (1<<6) | (0<<5)),
-
- /* mode_backlight */
- 7
+ /* Generic 640x480 TFT panel */
+ [4] = {
+ .name = "TFT_640x480_16",
+ .xres = 640,
+ .yres = 480,
+ .bpp = 16,
+ .control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
+ .horztiming = 0x3434d67f,
+ .verttiming = 0x0e0e39df,
+ .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
},
- { /* 3: Pb1100 800x600x16bpp NEON CRT */
- 800, /* xres */
- 600, /* yres */
- 16, /* bpp */
-
- "NEON_800x600_16",
-
- /* mode_control */
- 0x0004886A | LCD_DEFAULT_PIX_FORMAT,
-
- /* mode_horztiming */
- 0x005AFF1F,
-
- /* mode_verttiming */
- 0x16000E57,
-
- /* mode_clkcontrol */
- 0x00020000,
-
- /* mode_pwmdiv */
- 0,
-
- /* mode_pwmhi */
- 0,
-
- /* mode_toyclksrc */
- ((1<<7) | (1<<6) | (0<<5)),
-
- /* mode_backlight */
- 7
+ /* Pb1100 LCDB 640x480 PrimeView TFT panel */
+ [5] = {
+ .name = "PrimeView_640x480_16",
+ .xres = 640,
+ .yres = 480,
+ .bpp = 16,
+ .control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
+ .horztiming = 0x0e4bfe7f,
+ .verttiming = 0x210805df,
+ .clkcontrol_base = 0x00038001,
},
+};
- { /* 4: Pb1100 640x480x16bpp NEON CRT */
- 640, /* xres */
- 480, /* yres */
- 16, /* bpp */
-
- "NEON_640x480_16",
-
- /* mode_control */
- 0x0004886A | LCD_DEFAULT_PIX_FORMAT,
-
- /* mode_horztiming */
- 0x0052E27F,
-
- /* mode_verttiming */
- 0x18000DDF,
-
- /* mode_clkcontrol */
- 0x00020000,
+struct au1100fb_drv_info {
+ int panel_idx;
+ char *opt_mode;
+};
- /* mode_pwmdiv */
- 0,
+/********************************************************************/
- /* mode_pwmhi */
- 0,
+/* Inline helpers */
- /* mode_toyclksrc */
- ((1<<7) | (1<<6) | (0<<5)),
+#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
+#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
+#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
+#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
- /* mode_backlight */
- 7
- },
-};
#endif /* _AU1100LCD_H */
diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c
index e793ffd39db..762c7a59314 100644
--- a/drivers/video/console/newport_con.c
+++ b/drivers/video/console/newport_con.c
@@ -32,7 +32,6 @@
#include <linux/font.h>
-extern struct font_desc font_vga_8x16;
extern unsigned long sgi_gfxaddr;
#define FONT_DATA ((unsigned char *)font_vga_8x16.data)
diff --git a/drivers/video/gbefb.c b/drivers/video/gbefb.c
index d3c1922cb13..485604cd446 100644
--- a/drivers/video/gbefb.c
+++ b/drivers/video/gbefb.c
@@ -1126,7 +1126,7 @@ static int __init gbefb_probe(struct device *dev)
gbefb_setup(options);
#endif
- if (!request_mem_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) {
+ if (!request_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) {
printk(KERN_ERR "gbefb: couldn't reserve mmio region\n");
ret = -EBUSY;
goto out_release_framebuffer;
@@ -1152,12 +1152,24 @@ static int __init gbefb_probe(struct device *dev)
if (gbe_mem_phys) {
/* memory was allocated at boot time */
gbe_mem = ioremap_nocache(gbe_mem_phys, gbe_mem_size);
+ if (!gbe_mem) {
+ printk(KERN_ERR "gbefb: couldn't map framebuffer\n");
+ ret = -ENOMEM;
+ goto out_tiles_free;
+ }
+
gbe_dma_addr = 0;
} else {
/* try to allocate memory with the classical allocator
* this has high chance to fail on low memory machines */
gbe_mem = dma_alloc_coherent(NULL, gbe_mem_size, &gbe_dma_addr,
GFP_KERNEL);
+ if (!gbe_mem) {
+ printk(KERN_ERR "gbefb: couldn't allocate framebuffer memory\n");
+ ret = -ENOMEM;
+ goto out_tiles_free;
+ }
+
gbe_mem_phys = (unsigned long) gbe_dma_addr;
}
@@ -1165,12 +1177,6 @@ static int __init gbefb_probe(struct device *dev)
mtrr_add(gbe_mem_phys, gbe_mem_size, MTRR_TYPE_WRCOMB, 1);
#endif
- if (!gbe_mem) {
- printk(KERN_ERR "gbefb: couldn't map framebuffer\n");
- ret = -ENXIO;
- goto out_tiles_free;
- }
-
/* map framebuffer memory into tiles table */
for (i = 0; i < (gbe_mem_size >> TILE_SHIFT); i++)
gbe_tiles.cpu[i] = (gbe_mem_phys >> TILE_SHIFT) + i;
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2024-12-26 23:43:44 +0000