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authorJamie Iles <jamie@jamieiles.com>2011-03-14 17:38:30 +0000
committerJamie Iles <jamie@jamieiles.com>2011-11-22 15:21:20 +0000
commit0116da4fcc1ae8a80d9002441e98768f2a6fa2fe (patch)
tree503b19e91670f415fa5edfae95cd8b52170d417a /drivers
parent757a03c6e004fbbdef872cb7ecdc940a891b8e6e (diff)
macb: allow GEM to have configurable receive buffer size
GEM has configurable receive buffer sizes so requires this to be programmed up. Any size < 2048 and a multiple of 64 bytes is permitted. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Tested-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ethernet/cadence/macb.c17
-rw-r--r--drivers/net/ethernet/cadence/macb.h5
2 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 38f1932013d..64d61461bdc 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -856,6 +856,21 @@ static u32 macb_dbw(struct macb *bp)
}
}
+/*
+ * Configure the receive DMA engine to use the correct receive buffer size.
+ * This is a configurable parameter for GEM.
+ */
+static void macb_configure_dma(struct macb *bp)
+{
+ u32 dmacfg;
+
+ if (macb_is_gem(bp)) {
+ dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
+ dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64);
+ gem_writel(bp, DMACFG, dmacfg);
+ }
+}
+
static void macb_init_hw(struct macb *bp)
{
u32 config;
@@ -874,6 +889,8 @@ static void macb_init_hw(struct macb *bp)
config |= macb_dbw(bp);
macb_writel(bp, NCFGR, config);
+ macb_configure_dma(bp);
+
/* Initialize TX and RX buffers */
macb_writel(bp, RBQP, bp->rx_ring_dma);
macb_writel(bp, TBQP, bp->tx_ring_dma);
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 71424aae9c5..193107884a5 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -64,6 +64,7 @@
/* GEM register offsets. */
#define GEM_NCFGR 0x0004
#define GEM_USRIO 0x000c
+#define GEM_DMACFG 0x0010
#define GEM_HRB 0x0080
#define GEM_HRT 0x0084
#define GEM_SA1B 0x0088
@@ -154,6 +155,10 @@
#define GEM_DBW64 1
#define GEM_DBW128 2
+/* Bitfields in DMACFG. */
+#define GEM_RXBS_OFFSET 16
+#define GEM_RXBS_SIZE 8
+
/* Bitfields in NSR */
#define MACB_NSR_LINK_OFFSET 0
#define MACB_NSR_LINK_SIZE 1