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authorMatt Carlson <mcarlson@broadcom.com>2010-04-12 06:58:26 +0000
committerDavid S. Miller <davem@davemloft.net>2010-04-13 02:25:44 -0700
commita977dbe8445b8a81d6127c4aa9112a2c29a1a008 (patch)
tree00120e7881eb329122d0d4ca06d4b90b6c8c0444 /drivers
parent1a3190254c0d1d1951e1d7e93542387c6ec82384 (diff)
tg3: Reduce 57765 core clock when link at 10Mbps
This patch reduces the core clock to 6.25MHz when operating at 10Mbps link speed. This is needed to prevent a bug that will ultimately cause transmits to cease. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/tg3.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index a0ab89eb8bc..3e893231fef 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7654,6 +7654,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
tw32(GRC_MODE, grc_mode);
+
+ val = tr32(TG3_CPMU_LSPD_10MB_CLK);
+ val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
+ val |= CPMU_LSPD_10MB_MACCLK_6_25;
+ tw32(TG3_CPMU_LSPD_10MB_CLK, val);
}
/* This works around an issue with Athlon chipsets on