diff options
| author | Nick Nunley <nicholasx.d.nunley@intel.com> | 2010-07-01 13:37:54 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-07-01 22:45:55 -0700 |
| commit | ede3ef0d940ef052466f42c849390b23c6859abc (patch) | |
| tree | bf222dc6133e09189011fa39ba02ec2f96c7644e /drivers | |
| parent | 7475271004b66e9c22e1bb28f240a38c5d6fe76e (diff) | |
igb: fix PHY config access on 82580
82580 NICs can have up to 4 functions. This fixes phy accesses
to use the correct locks for functions 2 and 3.
Signed-off-by: Nicholas Nunley <nicholasx.d.nunley@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/igb/e1000_82575.c | 8 | ||||
| -rw-r--r-- | drivers/net/igb/e1000_defines.h | 2 |
2 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c index 86438b59fa2..06251a9e9f1 100644 --- a/drivers/net/igb/e1000_82575.c +++ b/drivers/net/igb/e1000_82575.c @@ -295,6 +295,10 @@ static s32 igb_acquire_phy_82575(struct e1000_hw *hw) if (hw->bus.func == E1000_FUNC_1) mask = E1000_SWFW_PHY1_SM; + else if (hw->bus.func == E1000_FUNC_2) + mask = E1000_SWFW_PHY2_SM; + else if (hw->bus.func == E1000_FUNC_3) + mask = E1000_SWFW_PHY3_SM; return igb_acquire_swfw_sync_82575(hw, mask); } @@ -312,6 +316,10 @@ static void igb_release_phy_82575(struct e1000_hw *hw) if (hw->bus.func == E1000_FUNC_1) mask = E1000_SWFW_PHY1_SM; + else if (hw->bus.func == E1000_FUNC_2) + mask = E1000_SWFW_PHY2_SM; + else if (hw->bus.func == E1000_FUNC_3) + mask = E1000_SWFW_PHY3_SM; igb_release_swfw_sync_82575(hw, mask); } diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h index 24d9be64342..90bc29d7e18 100644 --- a/drivers/net/igb/e1000_defines.h +++ b/drivers/net/igb/e1000_defines.h @@ -164,6 +164,8 @@ #define E1000_SWFW_EEP_SM 0x1 #define E1000_SWFW_PHY0_SM 0x2 #define E1000_SWFW_PHY1_SM 0x4 +#define E1000_SWFW_PHY2_SM 0x20 +#define E1000_SWFW_PHY3_SM 0x40 /* FACTPS Definitions */ /* Device Control */ |