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authorIngo Molnar <mingo@elte.hu>2009-03-18 09:57:02 +0100
committerIngo Molnar <mingo@elte.hu>2009-03-18 09:57:02 +0100
commit37ba317c9ed19eb126e40bbf563f2711e191a636 (patch)
treec5865768f341fc0ab41899fe9af9dc5918784cee /drivers
parent708dc5125309cd33c5daaad3026cc4ae6ef39c8b (diff)
parentee568b25ee9e160b32d1aef73d8b2ee9c05d34db (diff)
Merge branches 'sched/cleanups' and 'linus' into sched/core
Diffstat (limited to 'drivers')
-rw-r--r--drivers/acpi/bus.c9
-rw-r--r--drivers/acpi/numa.c2
-rw-r--r--drivers/acpi/osl.c50
-rw-r--r--drivers/acpi/sleep.c16
-rw-r--r--drivers/ata/ata_piix.c37
-rw-r--r--drivers/ata/libata-sff.c6
-rw-r--r--drivers/ata/sata_mv.c3
-rw-r--r--drivers/block/xsysace.c22
-rw-r--r--drivers/char/agp/parisc-agp.c23
-rw-r--r--drivers/ide/ide-atapi.c12
-rw-r--r--drivers/ide/ide-dma.c12
-rw-r--r--drivers/ide/ide-floppy.c6
-rw-r--r--drivers/md/dm-crypt.c43
-rw-r--r--drivers/md/dm-io.c2
-rw-r--r--drivers/md/dm-ioctl.c7
-rw-r--r--drivers/md/dm.c32
-rw-r--r--drivers/media/dvb/bt8xx/dst.c2
-rw-r--r--drivers/media/dvb/dvb-core/dvb_frontend.c7
-rw-r--r--drivers/media/dvb/frontends/stb0899_algo.c14
-rw-r--r--drivers/media/dvb/frontends/stb0899_drv.c2
-rw-r--r--drivers/media/dvb/frontends/stb0899_priv.h12
-rw-r--r--drivers/media/dvb/frontends/stb6100.c4
-rw-r--r--drivers/media/dvb/frontends/zl10353.c2
-rw-r--r--drivers/media/dvb/frontends/zl10353.h3
-rw-r--r--drivers/media/video/gspca/m5602/m5602_s5k4aa.c6
-rw-r--r--drivers/media/video/saa7134/saa7134-dvb.c1
-rw-r--r--drivers/media/video/tvaudio.c2
-rw-r--r--drivers/media/video/zoran/Kconfig1
-rw-r--r--drivers/net/Kconfig13
-rw-r--r--drivers/net/Makefile2
-rw-r--r--drivers/net/benet/Kconfig7
-rw-r--r--drivers/net/benet/Makefile7
-rw-r--r--drivers/net/benet/be.h327
-rw-r--r--drivers/net/benet/be_cmds.c861
-rw-r--r--drivers/net/benet/be_cmds.h688
-rw-r--r--drivers/net/benet/be_ethtool.c362
-rw-r--r--drivers/net/benet/be_hw.h211
-rw-r--r--drivers/net/benet/be_main.c1903
-rw-r--r--drivers/net/bnx2x.h2
-rw-r--r--drivers/net/bnx2x_init.h4
-rw-r--r--drivers/net/bnx2x_main.c21
-rw-r--r--drivers/net/dnet.c994
-rw-r--r--drivers/net/dnet.h225
-rw-r--r--drivers/net/ibm_newemac/core.c3
-rw-r--r--drivers/net/igb/igb_main.c26
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c1
-rw-r--r--drivers/net/mv643xx_eth.c10
-rw-r--r--drivers/net/netxen/netxen_nic.h1
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c22
-rw-r--r--drivers/net/netxen/netxen_nic_main.c3
-rw-r--r--drivers/net/qlge/qlge.h1
-rw-r--r--drivers/net/qlge/qlge_main.c57
-rw-r--r--drivers/net/r8169.c122
-rw-r--r--drivers/net/via-velocity.c15
-rw-r--r--drivers/parisc/dino.c13
-rw-r--r--drivers/parisc/gsc.c39
-rw-r--r--drivers/parisc/iosapic.c16
-rw-r--r--drivers/parisc/lba_pci.c4
-rw-r--r--drivers/parisc/sba_iommu.c63
-rw-r--r--drivers/platform/x86/Kconfig14
-rw-r--r--drivers/platform/x86/acer-wmi.c2
-rw-r--r--drivers/platform/x86/asus-laptop.c5
-rw-r--r--drivers/platform/x86/eeepc-laptop.c6
-rw-r--r--drivers/platform/x86/thinkpad_acpi.c8
-rw-r--r--drivers/platform/x86/wmi.c2
-rw-r--r--drivers/scsi/fcoe/fc_transport_fcoe.c91
-rw-r--r--drivers/scsi/fcoe/fcoe_sw.c56
-rw-r--r--drivers/scsi/fcoe/libfcoe.c318
-rw-r--r--drivers/scsi/lasi700.c2
-rw-r--r--drivers/scsi/libfc/fc_disc.c63
-rw-r--r--drivers/scsi/libfc/fc_exch.c32
-rw-r--r--drivers/scsi/libfc/fc_fcp.c56
-rw-r--r--drivers/scsi/libfc/fc_lport.c173
-rw-r--r--drivers/scsi/libfc/fc_rport.c197
-rw-r--r--drivers/scsi/qla2xxx/qla_attr.c9
-rw-r--r--drivers/scsi/qla2xxx/qla_init.c19
-rw-r--r--drivers/scsi/qla2xxx/qla_mbx.c3
-rw-r--r--drivers/scsi/qla2xxx/qla_mid.c10
-rw-r--r--drivers/scsi/qla2xxx/qla_os.c6
-rw-r--r--drivers/scsi/qla2xxx/qla_version.h2
-rw-r--r--drivers/scsi/sd.c26
-rw-r--r--drivers/scsi/zalon.c2
-rw-r--r--drivers/video/logo/logo_linux_clut224.ppm4428
-rw-r--r--drivers/video/logo/logo_linux_vga16.ppm4339
84 files changed, 12038 insertions, 4192 deletions
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 765fd1c56cd..bee64b73c91 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -758,8 +758,7 @@ static int __init acpi_bus_init(void)
acpi_status status = AE_OK;
extern acpi_status acpi_os_initialize1(void);
-
- status = acpi_os_initialize1();
+ acpi_os_initialize1();
status =
acpi_enable_subsystem(ACPI_NO_HARDWARE_INIT | ACPI_NO_ACPI_ENABLE);
@@ -769,12 +768,6 @@ static int __init acpi_bus_init(void)
goto error1;
}
- if (ACPI_FAILURE(status)) {
- printk(KERN_ERR PREFIX
- "Unable to initialize ACPI OS objects\n");
- goto error1;
- }
-
/*
* ACPI 2.0 requires the EC driver to be loaded and work before
* the EC device is found in the namespace (i.e. before acpi_initialize_objects()
diff --git a/drivers/acpi/numa.c b/drivers/acpi/numa.c
index c5e292aab0e..3a0d8ef25c7 100644
--- a/drivers/acpi/numa.c
+++ b/drivers/acpi/numa.c
@@ -277,7 +277,7 @@ int acpi_get_node(acpi_handle *handle)
int pxm, node = -1;
pxm = acpi_get_pxm(handle);
- if (pxm >= 0)
+ if (pxm >= 0 && pxm < MAX_PXM_DOMAINS)
node = acpi_map_pxm_to_node(pxm);
return node;
diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c
index b3193ec0a2e..1e35f342957 100644
--- a/drivers/acpi/osl.c
+++ b/drivers/acpi/osl.c
@@ -1317,54 +1317,6 @@ acpi_os_validate_interface (char *interface)
return AE_SUPPORT;
}
-#ifdef CONFIG_X86
-
-struct aml_port_desc {
- uint start;
- uint end;
- char* name;
- char warned;
-};
-
-static struct aml_port_desc aml_invalid_port_list[] = {
- {0x20, 0x21, "PIC0", 0},
- {0xA0, 0xA1, "PIC1", 0},
- {0x4D0, 0x4D1, "ELCR", 0}
-};
-
-/*
- * valid_aml_io_address()
- *
- * if valid, return true
- * else invalid, warn once, return false
- */
-static bool valid_aml_io_address(uint address, uint length)
-{
- int i;
- int entries = sizeof(aml_invalid_port_list) / sizeof(struct aml_port_desc);
-
- for (i = 0; i < entries; ++i) {
- if ((address >= aml_invalid_port_list[i].start &&
- address <= aml_invalid_port_list[i].end) ||
- (address + length >= aml_invalid_port_list[i].start &&
- address + length <= aml_invalid_port_list[i].end))
- {
- if (!aml_invalid_port_list[i].warned)
- {
- printk(KERN_ERR "ACPI: Denied BIOS AML access"
- " to invalid port 0x%x+0x%x (%s)\n",
- address, length,
- aml_invalid_port_list[i].name);
- aml_invalid_port_list[i].warned = 1;
- }
- return false; /* invalid */
- }
- }
- return true; /* valid */
-}
-#else
-static inline bool valid_aml_io_address(uint address, uint length) { return true; }
-#endif
/******************************************************************************
*
* FUNCTION: acpi_os_validate_address
@@ -1394,8 +1346,6 @@ acpi_os_validate_address (
switch (space_id) {
case ACPI_ADR_SPACE_SYSTEM_IO:
- if (!valid_aml_io_address(address, length))
- return AE_AML_ILLEGAL_ADDRESS;
case ACPI_ADR_SPACE_SYSTEM_MEMORY:
/* Only interference checks against SystemIO and SytemMemory
are needed */
diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c
index 519266654f0..00456fccfa3 100644
--- a/drivers/acpi/sleep.c
+++ b/drivers/acpi/sleep.c
@@ -378,6 +378,22 @@ static struct dmi_system_id __initdata acpisleep_dmi_table[] = {
DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
},
},
+ {
+ .callback = init_old_suspend_ordering,
+ .ident = "Asus Pundit P1-AH2 (M2N8L motherboard)",
+ .matches = {
+ DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."),
+ DMI_MATCH(DMI_BOARD_NAME, "M2N8L"),
+ },
+ },
+ {
+ .callback = init_set_sci_en_on_resume,
+ .ident = "Toshiba Satellite L300",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "Satellite L300"),
+ },
+ },
{},
};
#endif /* CONFIG_SUSPEND */
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index 54961c0b2c7..ef8b30d577b 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -1289,6 +1289,39 @@ static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
return map;
}
+static bool piix_no_sidpr(struct ata_host *host)
+{
+ struct pci_dev *pdev = to_pci_dev(host->dev);
+
+ /*
+ * Samsung DB-P70 only has three ATA ports exposed and
+ * curiously the unconnected first port reports link online
+ * while not responding to SRST protocol causing excessive
+ * detection delay.
+ *
+ * Unfortunately, the system doesn't carry enough DMI
+ * information to identify the machine but does have subsystem
+ * vendor and device set. As it's unclear whether the
+ * subsystem vendor/device is used only for this specific
+ * board, the port can't be disabled solely with the
+ * information; however, turning off SIDPR access works around
+ * the problem. Turn it off.
+ *
+ * This problem is reported in bnc#441240.
+ *
+ * https://bugzilla.novell.com/show_bug.cgi?id=441420
+ */
+ if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
+ pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
+ pdev->subsystem_device == 0xb049) {
+ dev_printk(KERN_WARNING, host->dev,
+ "Samsung DB-P70 detected, disabling SIDPR\n");
+ return true;
+ }
+
+ return false;
+}
+
static int __devinit piix_init_sidpr(struct ata_host *host)
{
struct pci_dev *pdev = to_pci_dev(host->dev);
@@ -1302,6 +1335,10 @@ static int __devinit piix_init_sidpr(struct ata_host *host)
if (hpriv->map[i] == IDE)
return 0;
+ /* is it blacklisted? */
+ if (piix_no_sidpr(host))
+ return 0;
+
if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
return 0;
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c
index 714cb046b59..f93dc029dfd 100644
--- a/drivers/ata/libata-sff.c
+++ b/drivers/ata/libata-sff.c
@@ -2066,6 +2066,7 @@ static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
udelay(20); /* FIXME: flush */
iowrite8(ap->ctl, ioaddr->ctl_addr);
+ ap->last_ctl = ap->ctl;
/* wait the port to become ready */
return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
@@ -2190,8 +2191,10 @@ void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
}
/* set up device control */
- if (ap->ioaddr.ctl_addr)
+ if (ap->ioaddr.ctl_addr) {
iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
+ ap->last_ctl = ap->ctl;
+ }
}
EXPORT_SYMBOL_GPL(ata_sff_postreset);
@@ -2534,6 +2537,7 @@ void ata_bus_reset(struct ata_port *ap)
if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
/* set up device control for ATA_FLAG_SATA_RESET */
iowrite8(ap->ctl, ioaddr->ctl_addr);
+ ap->last_ctl = ap->ctl;
}
DPRINTK("EXIT\n");
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 7007edd2d45..74b1080d116 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -2218,12 +2218,13 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance)
else
handled = mv_host_intr(host, pending_irqs);
}
- spin_unlock(&host->lock);
/* for MSI: unmask; interrupt cause bits will retrigger now */
if (using_msi)
writel(hpriv->main_irq_mask, hpriv->main_irq_mask_addr);
+ spin_unlock(&host->lock);
+
return IRQ_RETVAL(handled);
}
diff --git a/drivers/block/xsysace.c b/drivers/block/xsysace.c
index 381d686fc1a..119be3442f2 100644
--- a/drivers/block/xsysace.c
+++ b/drivers/block/xsysace.c
@@ -489,6 +489,28 @@ static void ace_fsm_dostate(struct ace_device *ace)
ace->fsm_state, ace->id_req_count);
#endif
+ /* Verify that there is actually a CF in the slot. If not, then
+ * bail out back to the idle state and wake up all the waiters */
+ status = ace_in32(ace, ACE_STATUS);
+ if ((status & ACE_STATUS_CFDETECT) == 0) {
+ ace->fsm_state = ACE_FSM_STATE_IDLE;
+ ace->media_change = 1;
+ set_capacity(ace->gd, 0);
+ dev_info(ace->dev, "No CF in slot\n");
+
+ /* Drop all pending requests */
+ while ((req = elv_next_request(ace->queue)) != NULL)
+ end_request(req, 0);
+
+ /* Drop back to IDLE state and notify waiters */
+ ace->fsm_state = ACE_FSM_STATE_IDLE;
+ ace->id_result = -EIO;
+ while (ace->id_req_count) {
+ complete(&ace->id_completion);
+ ace->id_req_count--;
+ }
+ }
+
switch (ace->fsm_state) {
case ACE_FSM_STATE_IDLE:
/* See if there is anything to do */
diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c
index db60539bf67..699e3422ad9 100644
--- a/drivers/char/agp/parisc-agp.c
+++ b/drivers/char/agp/parisc-agp.c
@@ -359,9 +359,16 @@ fail:
return error;
}
-static struct device *next_device(struct klist_iter *i) {
- struct klist_node * n = klist_next(i);
- return n ? container_of(n, struct device, knode_parent) : NULL;
+static int
+find_quicksilver(struct device *dev, void *data)
+{
+ struct parisc_device **lba = data;
+ struct parisc_device *padev = to_parisc_device(dev);
+
+ if (IS_QUICKSILVER(padev))
+ *lba = padev;
+
+ return 0;
}
static int
@@ -372,8 +379,6 @@ parisc_agp_init(void)
int err = -1;
struct parisc_device *sba = NULL, *lba = NULL;
struct lba_device *lbadev = NULL;
- struct device *dev = NULL;
- struct klist_iter i;
if (!sba_list)
goto out;
@@ -386,13 +391,7 @@ parisc_agp_init(void)
}
/* Now search our Pluto for our precious AGP device... */
- klist_iter_init(&sba->dev.klist_children, &i);
- while ((dev = next_device(&i))) {
- struct parisc_device *padev = to_parisc_device(dev);
- if (IS_QUICKSILVER(padev))
- lba = padev;
- }
- klist_iter_exit(&i);
+ device_for_each_child(&sba->dev, &lba, find_quicksilver);
if (!lba) {
printk(KERN_INFO DRVPFX "No AGP devices found.\n");
diff --git a/drivers/ide/ide-atapi.c b/drivers/ide/ide-atapi.c
index e96c0126059..e9d042dba0e 100644
--- a/drivers/ide/ide-atapi.c
+++ b/drivers/ide/ide-atapi.c
@@ -140,6 +140,12 @@ static void ide_queue_pc_head(ide_drive_t *drive, struct gendisk *disk,
rq->cmd_flags |= REQ_PREEMPT;
rq->buffer = (char *)pc;
rq->rq_disk = disk;
+
+ if (pc->req_xfer) {
+ rq->data = pc->buf;
+ rq->data_len = pc->req_xfer;
+ }
+
memcpy(rq->cmd, pc->c, 12);
if (drive->media == ide_tape)
rq->cmd[13] = REQ_IDETAPE_PC1;
@@ -159,6 +165,12 @@ int ide_queue_pc_tail(ide_drive_t *drive, struct gendisk *disk,
rq = blk_get_request(drive->queue, READ, __GFP_WAIT);
rq->cmd_type = REQ_TYPE_SPECIAL;
rq->buffer = (char *)pc;
+
+ if (pc->req_xfer) {
+ rq->data = pc->buf;
+ rq->data_len = pc->req_xfer;
+ }
+
memcpy(rq->cmd, pc->c, 12);
if (drive->media == ide_tape)
rq->cmd[13] = REQ_IDETAPE_PC1;
diff --git a/drivers/ide/ide-dma.c b/drivers/ide/ide-dma.c
index 72ebab0bc75..059c90bb5ad 100644
--- a/drivers/ide/ide-dma.c
+++ b/drivers/ide/ide-dma.c
@@ -128,6 +128,7 @@ int ide_build_sglist(ide_drive_t *drive, struct request *rq)
{
ide_hwif_t *hwif = drive->hwif;
struct scatterlist *sg = hwif->sg_table;
+ int i;
ide_map_sg(drive, rq);
@@ -136,8 +137,13 @@ int ide_build_sglist(ide_drive_t *drive, struct request *rq)
else
hwif->sg_dma_direction = DMA_TO_DEVICE;
- return dma_map_sg(hwif->dev, sg, hwif->sg_nents,
- hwif->sg_dma_direction);
+ i = dma_map_sg(hwif->dev, sg, hwif->sg_nents, hwif->sg_dma_direction);
+ if (i) {
+ hwif->orig_sg_nents = hwif->sg_nents;
+ hwif->sg_nents = i;
+ }
+
+ return i;
}
EXPORT_SYMBOL_GPL(ide_build_sglist);
@@ -156,7 +162,7 @@ void ide_destroy_dmatable(ide_drive_t *drive)
{
ide_hwif_t *hwif = drive->hwif;
- dma_unmap_sg(hwif->dev, hwif->sg_table, hwif->sg_nents,
+ dma_unmap_sg(hwif->dev, hwif->sg_table, hwif->orig_sg_nents,
hwif->sg_dma_direction);
}
EXPORT_SYMBOL_GPL(ide_destroy_dmatable);
diff --git a/drivers/ide/ide-floppy.c b/drivers/ide/ide-floppy.c
index 3eab1c6c9b3..317ec62c33d 100644
--- a/drivers/ide/ide-floppy.c
+++ b/drivers/ide/ide-floppy.c
@@ -327,8 +327,10 @@ static ide_startstop_t ide_floppy_do_request(ide_drive_t *drive,
return ide_stopped;
}
- ide_init_sg_cmd(drive, rq);
- ide_map_sg(drive, rq);
+ if (blk_fs_request(rq) || pc->req_xfer) {
+ ide_init_sg_cmd(drive, rq);
+ ide_map_sg(drive, rq);
+ }
pc->sg = hwif->sg_table;
pc->sg_cnt = hwif->sg_nents;
diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c
index 35bda49796f..bfefd079a95 100644
--- a/drivers/md/dm-crypt.c
+++ b/drivers/md/dm-crypt.c
@@ -60,6 +60,7 @@ struct dm_crypt_io {
};
struct dm_crypt_request {
+ struct convert_context *ctx;
struct scatterlist sg_in;
struct scatterlist sg_out;
};
@@ -335,6 +336,18 @@ static void crypt_convert_init(struct crypt_config *cc,
init_completion(&ctx->restart);
}
+static struct dm_crypt_request *dmreq_of_req(struct crypt_config *cc,
+ struct ablkcipher_request *req)
+{
+ return (struct dm_crypt_request *)((char *)req + cc->dmreq_start);
+}
+
+static struct ablkcipher_request *req_of_dmreq(struct crypt_config *cc,
+ struct dm_crypt_request *dmreq)
+{
+ return (struct ablkcipher_request *)((char *)dmreq - cc->dmreq_start);
+}
+
static int crypt_convert_block(struct crypt_config *cc,
struct convert_context *ctx,
struct ablkcipher_request *req)
@@ -345,10 +358,11 @@ static int crypt_convert_block(struct crypt_config *cc,
u8 *iv;
int r = 0;
- dmreq = (struct dm_crypt_request *)((char *)req + cc->dmreq_start);
+ dmreq = dmreq_of_req(cc, req);
iv = (u8 *)ALIGN((unsigned long)(dmreq + 1),
crypto_ablkcipher_alignmask(cc->tfm) + 1);
+ dmreq->ctx = ctx;
sg_init_table(&dmreq->sg_in, 1);
sg_set_page(&dmreq->sg_in, bv_in->bv_page, 1 << SECTOR_SHIFT,
bv_in->bv_offset + ctx->offset_in);
@@ -395,8 +409,9 @@ static void crypt_alloc_req(struct crypt_config *cc,
cc->req = mempool_alloc(cc->req_pool, GFP_NOIO);
ablkcipher_request_set_tfm(cc->req, cc->tfm);
ablkcipher_request_set_callback(cc->req, CRYPTO_TFM_REQ_MAY_BACKLOG |
- CRYPTO_TFM_REQ_MAY_SLEEP,
- kcryptd_async_done, ctx);
+ CRYPTO_TFM_REQ_MAY_SLEEP,
+ kcryptd_async_done,
+ dmreq_of_req(cc, cc->req));
}
/*
@@ -553,19 +568,22 @@ static void crypt_inc_pending(struct dm_crypt_io *io)
static void crypt_dec_pending(struct dm_crypt_io *io)
{
struct crypt_config *cc = io->target->private;
+ struct bio *base_bio = io->base_bio;
+ struct dm_crypt_io *base_io = io->base_io;
+ int error = io->error;
if (!atomic_dec_and_test(&io->pending))
return;
- if (likely(!io->base_io))
- bio_endio(io->base_bio, io->error);
+ mempool_free(io, cc->io_pool);
+
+ if (likely(!base_io))
+ bio_endio(base_bio, error);
else {
- if (io->error && !io->base_io->error)
- io->base_io->error = io->error;
- crypt_dec_pending(io->base_io);
+ if (error && !base_io->error)
+ base_io->error = error;
+ crypt_dec_pending(base_io);
}
-
- mempool_free(io, cc->io_pool);
}
/*
@@ -821,7 +839,8 @@ static void kcryptd_crypt_read_convert(struct dm_crypt_io *io)
static void kcryptd_async_done(struct crypto_async_request *async_req,
int error)
{
- struct convert_context *ctx = async_req->data;
+ struct dm_crypt_request *dmreq = async_req->data;
+ struct convert_context *ctx = dmreq->ctx;
struct dm_crypt_io *io = container_of(ctx, struct dm_crypt_io, ctx);
struct crypt_config *cc = io->target->private;
@@ -830,7 +849,7 @@ static void kcryptd_async_done(struct crypto_async_request *async_req,
return;
}
- mempool_free(ablkcipher_request_cast(async_req), cc->req_pool);
+ mempool_free(req_of_dmreq(cc, dmreq), cc->req_pool);
if (!atomic_dec_and_test(&ctx->pending))
return;
diff --git a/drivers/md/dm-io.c b/drivers/md/dm-io.c
index f14813be4ef..36e2b5e46a6 100644
--- a/drivers/md/dm-io.c
+++ b/drivers/md/dm-io.c
@@ -292,6 +292,8 @@ static void do_region(int rw, unsigned region, struct dm_io_region *where,
(PAGE_SIZE >> SECTOR_SHIFT));
num_bvecs = 1 + min_t(int, bio_get_nr_vecs(where->bdev),
num_bvecs);
+ if (unlikely(num_bvecs > BIO_MAX_PAGES))
+ num_bvecs = BIO_MAX_PAGES;
bio = bio_alloc_bioset(GFP_NOIO, num_bvecs, io->client->bios);
bio->bi_sector = where->sector + (where->count - remaining);
bio->bi_bdev = where->bdev;
diff --git a/drivers/md/dm-ioctl.c b/drivers/md/dm-ioctl.c
index 54d0588fc1f..f01096549a9 100644
--- a/drivers/md/dm-ioctl.c
+++ b/drivers/md/dm-ioctl.c
@@ -704,7 +704,8 @@ static int dev_rename(struct dm_ioctl *param, size_t param_size)
char *new_name = (char *) param + param->data_start;
if (new_name < param->data ||
- invalid_str(new_name, (void *) param + param_size)) {
+ invalid_str(new_name, (void *) param + param_size) ||
+ strlen(new_name) > DM_NAME_LEN - 1) {
DMWARN("Invalid new logical volume name supplied.");
return -EINVAL;
}
@@ -1063,7 +1064,7 @@ static int table_load(struct dm_ioctl *param, size_t param_size)
r = populate_table(t, param, param_size);
if (r) {
- dm_table_put(t);
+ dm_table_destroy(t);
goto out;
}
@@ -1071,7 +1072,7 @@ static int table_load(struct dm_ioctl *param, size_t param_size)
hc = dm_get_mdptr(md);
if (!hc || hc->md != md) {
DMWARN("device has been removed from the dev hash table.");
- dm_table_put(t);
+ dm_table_destroy(t);
up_write(&_hash_lock);
r = -ENXIO;
goto out;
diff --git a/drivers/md/dm.c b/drivers/md/dm.c
index 51ba1db4b3e..8d40f27cce8 100644
--- a/drivers/md/dm.c
+++ b/drivers/md/dm.c
@@ -525,9 +525,12 @@ static int __noflush_suspending(struct mapped_device *md)
static void dec_pending(struct dm_io *io, int error)
{
unsigned long flags;
+ int io_error;
+ struct bio *bio;
+ struct mapped_device *md = io->md;
/* Push-back supersedes any I/O errors */
- if (error && !(io->error > 0 && __noflush_suspending(io->md)))
+ if (error && !(io->error > 0 && __noflush_suspending(md)))
io->error = error;
if (atomic_dec_and_test(&io->io_count)) {
@@ -537,24 +540,27 @@ static void dec_pending(struct dm_io *io, int error)
* This must be handled before the sleeper on
* suspend queue merges the pushback list.
*/
- spin_lock_irqsave(&io->md->pushback_lock, flags);
- if (__noflush_suspending(io->md))
- bio_list_add(&io->md->pushback, io->bio);
+ spin_lock_irqsave(&md->pushback_lock, flags);
+ if (__noflush_suspending(md))
+ bio_list_add(&md->pushback, io->bio);
else
/* noflush suspend was interrupted. */
io->error = -EIO;
- spin_unlock_irqrestore(&io->md->pushback_lock, flags);
+ spin_unlock_irqrestore(&md->pushback_lock, flags);
}
end_io_acct(io);
- if (io->error != DM_ENDIO_REQUEUE) {
- trace_block_bio_complete(io->md->queue, io->bio);
+ io_error = io->error;
+ bio = io->bio;
- bio_endio(io->bio, io->error);
- }
+ free_io(md, io);
+
+ if (io_error != DM_ENDIO_REQUEUE) {
+ trace_block_bio_complete(md->queue, bio);
- free_io(io->md, io);
+ bio_endio(bio, io_error);
+ }
}
}
@@ -562,6 +568,7 @@ static void clone_endio(struct bio *bio, int error)
{
int r = 0;
struct dm_target_io *tio = bio->bi_private;
+ struct dm_io *io = tio->io;
struct mapped_device *md = tio->io->md;
dm_endio_fn endio = tio->ti->type->end_io;
@@ -585,15 +592,14 @@ static void clone_endio(struct bio *bio, int error)
}
}
- dec_pending(tio->io, error);
-
/*
* Store md for cleanup instead of tio which is about to get freed.
*/
bio->bi_private = md->bs;
- bio_put(bio);
free_tio(md, tio);
+ bio_put(bio);
+ dec_pending(io, error);
}
static sector_t max_io_len(struct mapped_device *md,
diff --git a/drivers/media/dvb/bt8xx/dst.c b/drivers/media/dvb/bt8xx/dst.c
index 29e8f1546ab..fec1d77fa85 100644
--- a/drivers/media/dvb/bt8xx/dst.c
+++ b/drivers/media/dvb/bt8xx/dst.c
@@ -1683,7 +1683,7 @@ static int dst_tune_frontend(struct dvb_frontend* fe,
static int dst_get_tuning_algo(struct dvb_frontend *fe)
{
- return dst_algo;
+ return dst_algo ? DVBFE_ALGO_HW : DVBFE_ALGO_SW;
}
static int dst_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c
index 84340778508..8dcb3fbf7ac 100644
--- a/drivers/media/dvb/dvb-core/dvb_frontend.c
+++ b/drivers/media/dvb/dvb-core/dvb_frontend.c
@@ -1290,9 +1290,6 @@ static int dtv_property_process_set(struct dvb_frontend *fe,
dprintk("%s() Finalised property cache\n", __func__);
dtv_property_cache_submit(fe);
- /* Request the search algorithm to search */
- fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN;
-
r |= dvb_frontend_ioctl_legacy(inode, file, FE_SET_FRONTEND,
&fepriv->parameters);
break;
@@ -1717,6 +1714,10 @@ static int dvb_frontend_ioctl_legacy(struct inode *inode, struct file *file,
fepriv->min_delay = (dvb_override_tune_delay * HZ) / 1000;
fepriv->state = FESTATE_RETUNE;
+
+ /* Request the search algorithm to search */
+ fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN;
+
dvb_frontend_wakeup(fe);
dvb_frontend_add_event(fe, 0);
fepriv->status = 0;
diff --git a/drivers/media/dvb/frontends/stb0899_algo.c b/drivers/media/dvb/frontends/stb0899_algo.c
index a67d1775a43..2da55ec2039 100644
--- a/drivers/media/dvb/frontends/stb0899_algo.c
+++ b/drivers/media/dvb/frontends/stb0899_algo.c
@@ -156,7 +156,7 @@ static void stb0899_first_subrange(struct stb0899_state *state)
}
if (range > 0)
- internal->sub_range = MIN(internal->srch_range, range);
+ internal->sub_range = min(internal->srch_range, range);
else
internal->sub_range = 0;
@@ -185,7 +185,7 @@ static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
timing = stb0899_read_reg(state, STB0899_RTF);
if (lock >= 42) {
- if ((lock > 48) && (ABS(timing) >= 110)) {
+ if ((lock > 48) && (abs(timing) >= 110)) {
internal->status = ANALOGCARRIER;
dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
} else {
@@ -222,7 +222,7 @@ static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
index++;
derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */
- if (ABS(derot_freq) > derot_limit)
+ if (abs(derot_freq) > derot_limit)
next_loop--;
if (next_loop) {
@@ -298,7 +298,7 @@ static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
last_derot_freq = derot_freq;
derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */
- if(ABS(derot_freq) > derot_limit)
+ if(abs(derot_freq) > derot_limit)
next_loop--;
if (next_loop) {
@@ -400,7 +400,7 @@ static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */
- if (ABS(derot_freq) > derot_limit)
+ if (abs(derot_freq) > derot_limit)
next_loop--;
if (next_loop) {
@@ -467,7 +467,7 @@ static void next_sub_range(struct stb0899_state *state)
if (internal->sub_dir > 0) {
old_sub_range = internal->sub_range;
- internal->sub_range = MIN((internal->srch_range / 2) -
+ internal->sub_range = min((internal->srch_range / 2) -
(internal->tuner_offst + internal->sub_range / 2),
internal->sub_range);
@@ -771,7 +771,7 @@ static long Log2Int(int number)
int i;
i = 0;
- while ((1 << i) <= ABS(number))
+ while ((1 << i) <= abs(number))
i++;
if (number == 0)
diff --git a/drivers/media/dvb/frontends/stb0899_drv.c b/drivers/media/dvb/frontends/stb0899_drv.c
index 10613acf18f..a04c782fff8 100644
--- a/drivers/media/dvb/frontends/stb0899_drv.c
+++ b/drivers/media/dvb/frontends/stb0899_drv.c
@@ -794,7 +794,7 @@ static int stb0899_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t
reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
old_state = reg;
/* set to burst mode */
- STB0899_SETFIELD_VAL(DISEQCMODE, reg, 0x02);
+ STB0899_SETFIELD_VAL(DISEQCMODE, reg, 0x03);
STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x01);
stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
switch (burst) {
diff --git a/drivers/media/dvb/frontends/stb0899_priv.h b/drivers/media/dvb/frontends/stb0899_priv.h
index 24619e3689d..82395b91281 100644
--- a/drivers/media/dvb/frontends/stb0899_priv.h
+++ b/drivers/media/dvb/frontends/stb0899_priv.h
@@ -59,10 +59,6 @@
#define MAKEWORD32(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
#define MAKEWORD16(a, b) (((a) << 8) | (b))
-#define MIN(x, y) ((x) <= (y) ? (x) : (y))
-#define MAX(x, y) ((x) >= (y) ? (x) : (y))
-#define ABS(x) ((x) >= 0 ? (x) : -(x))
-
#define LSB(x) ((x & 0xff))
#define MSB(y) ((y >> 8) & 0xff)
@@ -168,10 +164,10 @@ struct stb0899_internal {
u32 freq; /* Demod internal Frequency */
u32 srate; /* Demod internal Symbol rate */
enum stb0899_fec fecrate; /* Demod internal FEC rate */
- u32 srch_range; /* Demod internal Search Range */
- u32 sub_range; /* Demod current sub range (Hz) */
- u32 tuner_step; /* Tuner step (Hz) */
- u32 tuner_offst; /* Relative offset to carrier (Hz) */
+ s32 srch_range; /* Demod internal Search Range */
+ s32 sub_range; /* Demod current sub range (Hz) */
+ s32 tuner_step; /* Tuner step (Hz) */
+ s32 tuner_offst; /* Relative offset to carrier (Hz) */
u32 tuner_bw; /* Current bandwidth of the tuner (Hz) */
s32 mclk; /* Masterclock Divider factor (binary) */
diff --git a/drivers/media/dvb/frontends/stb6100.c b/drivers/media/dvb/frontends/stb6100.c
index ff39275ab49..1ed5a7db4c5 100644
--- a/drivers/media/dvb/frontends/stb6100.c
+++ b/drivers/media/dvb/frontends/stb6100.c
@@ -427,11 +427,11 @@ static int stb6100_init(struct dvb_frontend *fe)
status->refclock = 27000000; /* Hz */
status->iqsense = 1;
status->bandwidth = 36000; /* kHz */
- state->bandwidth = status->bandwidth * 1000; /* MHz */
+ state->bandwidth = status->bandwidth * 1000; /* Hz */
state->reference = status->refclock / 1000; /* kHz */
/* Set default bandwidth. */
- return stb6100_set_bandwidth(fe, status->bandwidth);
+ return stb6100_set_bandwidth(fe, state->bandwidth);
}
static int stb6100_get_state(struct dvb_frontend *fe,
diff --git a/drivers/media/dvb/frontends/zl10353.c b/drivers/media/dvb/frontends/zl10353.c
index 170720b0281..b150ed30669 100644
--- a/drivers/media/dvb/frontends/zl10353.c
+++ b/drivers/media/dvb/frontends/zl10353.c
@@ -590,7 +590,7 @@ static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
struct zl10353_state *state = fe->demodulator_priv;
u8 val = 0x0a;
- if (state->config.no_tuner) {
+ if (state->config.disable_i2c_gate_ctrl) {
/* No tuner attached to the internal I2C bus */
/* If set enable I2C bridge, the main I2C bus stopped hardly */
return 0;
diff --git a/drivers/media/dvb/frontends/zl10353.h b/drivers/media/dvb/frontends/zl10353.h
index fdbb88ff75f..2287bac4624 100644
--- a/drivers/media/dvb/frontends/zl10353.h
+++ b/drivers/media/dvb/frontends/zl10353.h
@@ -38,6 +38,9 @@ struct zl10353_config
/* set if parallel ts output is required */
int parallel_ts;
+
+ /* set if i2c_gate_ctrl disable is required */
+ u8 disable_i2c_gate_ctrl:1;
};
#if defined(CONFIG_DVB_ZL10353) || (defined(CONFIG_DVB_ZL10353_MODULE) && defined(MODULE))
diff --git a/drivers/media/video/gspca/m5602/m5602_s5k4aa.c b/drivers/media/video/gspca/m5602/m5602_s5k4aa.c
index e564a61a72d..48892b5715d 100644
--- a/drivers/media/video/gspca/m5602/m5602_s5k4aa.c
+++ b/drivers/media/video/gspca/m5602/m5602_s5k4aa.c
@@ -102,7 +102,11 @@ int s5k4aa_probe(struct sd *sd)
}
/* Test some registers, but we don't know their exact meaning yet */
- if (m5602_read_sensor(sd, 0x00, prod_id, sizeof(prod_id)))
+ if (m5602_read_sensor(sd, 0x00, prod_id, 2))
+ return -ENODEV;
+ if (m5602_read_sensor(sd, 0x02, prod_id+2, 2))
+ return -ENODEV;
+ if (m5602_read_sensor(sd, 0x04, prod_id+4, 2))
return -ENODEV;
if (memcmp(prod_id, expected_prod_id, sizeof(prod_id)))
diff --git a/drivers/media/video/saa7134/saa7134-dvb.c b/drivers/media/video/saa7134/saa7134-dvb.c
index 0776ecf56d2..b5370b3e1a3 100644
--- a/drivers/media/video/saa7134/saa7134-dvb.c
+++ b/drivers/media/video/saa7134/saa7134-dvb.c
@@ -860,6 +860,7 @@ static struct zl10353_config behold_h6_config = {
.demod_address = 0x1e>>1,
.no_tuner = 1,
.parallel_ts = 1,
+ .disable_i2c_gate_ctrl = 1,
};
/* ==================================================================
diff --git a/drivers/media/video/tvaudio.c b/drivers/media/video/tvaudio.c
index 5aeccb301ce..076ed5bf48b 100644
--- a/drivers/media/video/tvaudio.c
+++ b/drivers/media/video/tvaudio.c
@@ -54,7 +54,7 @@ MODULE_LICENSE("GPL");
/* ---------------------------------------------------------------------- */
/* our structs */
-#define MAXREGS 64
+#define MAXREGS 256
struct CHIPSTATE;
typedef int (*getvalue)(int);
diff --git a/drivers/media/video/zoran/Kconfig b/drivers/media/video/zoran/Kconfig
index 4ea5fa71de8..8666e19f31a 100644
--- a/drivers/media/video/zoran/Kconfig
+++ b/drivers/media/video/zoran/Kconfig
@@ -68,6 +68,7 @@ config VIDEO_ZORAN_AVS6EYES
tristate "AverMedia 6 Eyes support (EXPERIMENTAL)"
depends on VIDEO_ZORAN_ZR36060 && EXPERIMENTAL && VIDEO_V4L1
select VIDEO_BT856 if VIDEO_HELPER_CHIPS_AUTO
+ select VIDEO_BT866 if VIDEO_HELPER_CHIPS_AUTO
select VIDEO_KS0127 if VIDEO_HELPER_CHIPS_AUTO
help
Support for the AverMedia 6 Eyes video surveillance card.
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index a2f185fd707..435e2e3a82c 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1040,6 +1040,17 @@ config NI65
To compile this driver as a module, choose M here. The module
will be called ni65.
+config DNET
+ tristate "Dave ethernet support (DNET)"
+ depends on NET_ETHERNET
+ select PHYLIB
+ help
+ The Dave ethernet interface (DNET) is found on Qong Board FPGA.
+ Say Y to include support for the DNET chip.
+
+ To compile this driver as a module, choose M here: the module
+ will be called dnet.
+
source "drivers/net/tulip/Kconfig"
config AT1700
@@ -2619,6 +2630,8 @@ config QLGE
source "drivers/net/sfc/Kconfig"
+source "drivers/net/benet/Kconfig"
+
endif # NETDEV_10000
source "drivers/net/tokenring/Kconfig"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index aca8492db65..471baaff229 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_GIANFAR) += gianfar_driver.o
obj-$(CONFIG_TEHUTI) += tehuti.o
obj-$(CONFIG_ENIC) += enic/
obj-$(CONFIG_JME) += jme.o
+obj-$(CONFIG_BE2NET) += benet/
gianfar_driver-objs := gianfar.o \
gianfar_ethtool.o \
@@ -231,6 +232,7 @@ obj-$(CONFIG_ENC28J60) += enc28j60.o
obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
+obj-$(CONFIG_DNET) += dnet.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_ARM) += arm/
diff --git a/drivers/net/benet/Kconfig b/drivers/net/benet/Kconfig
new file mode 100644
index 00000000000..c6934f179c0
--- /dev/null
+++ b/drivers/net/benet/Kconfig
@@ -0,0 +1,7 @@
+config BE2NET
+ tristate "ServerEngines' 10Gbps NIC - BladeEngine 2"
+ depends on PCI && INET
+ select INET_LRO
+ help
+ This driver implements the NIC functionality for ServerEngines'
+ 10Gbps network adapter - BladeEngine 2.
diff --git a/drivers/net/benet/Makefile b/drivers/net/benet/Makefile
new file mode 100644
index 00000000000..a60cd805113
--- /dev/null
+++ b/drivers/net/benet/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile to build the network driver for ServerEngine's BladeEngine.
+#
+
+obj-$(CONFIG_BE2NET) += be2net.o
+
+be2net-y := be_main.o be_cmds.o be_ethtool.o
diff --git a/drivers/net/benet/be.h b/drivers/net/benet/be.h
new file mode 100644
index 00000000000..63d593d5315
--- /dev/null
+++ b/drivers/net/benet/be.h
@@ -0,0 +1,327 @@
+/*
+ * Copyright (C) 2005 - 2009 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation. The full GNU General
+ * Public License is included in this distribution in the file called COPYING.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+
+#ifndef BE_H
+#define BE_H
+
+#include <linux/pci.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <linux/delay.h>
+#include <net/tcp.h>
+#include <net/ip.h>
+#include <net/ipv6.h>
+#include <linux/if_vlan.h>
+#include <linux/workqueue.h>
+#include <linux/interrupt.h>
+#include <linux/inet_lro.h>
+
+#include "be_hw.h"
+
+#define DRV_VER "2.0.348"
+#define DRV_NAME "be2net"
+#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
+#define DRV_DESC BE_NAME "Driver"
+
+/* Number of bytes of an RX frame that are copied to skb->data */
+#define BE_HDR_LEN 64
+#define BE_MAX_JUMBO_FRAME_SIZE 9018
+#define BE_MIN_MTU 256
+
+#define BE_NUM_VLANS_SUPPORTED 64
+#define BE_MAX_EQD 96
+#define BE_MAX_TX_FRAG_COUNT 30
+
+#define EVNT_Q_LEN 1024
+#define TX_Q_LEN 2048
+#define TX_CQ_LEN 1024
+#define RX_Q_LEN 1024 /* Does not support any other value */
+#define RX_CQ_LEN 1024
+#define MCC_Q_LEN 64 /* total size not to exceed 8 pages */
+#define MCC_CQ_LEN 256
+
+#define BE_NAPI_WEIGHT 64
+#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
+#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
+
+#define BE_MAX_LRO_DESCRIPTORS 16
+#define BE_MAX_FRAGS_PER_FRAME 16
+
+struct be_dma_mem {
+ void *va;
+ dma_addr_t dma;
+ u32 size;
+};
+
+struct be_queue_info {
+ struct be_dma_mem dma_mem;
+ u16 len;
+ u16 entry_size; /* Size of an element in the queue */
+ u16 id;
+ u16 tail, head;
+ bool created;
+ atomic_t used; /* Number of valid elements in the queue */
+};
+
+struct be_ctrl_info {
+ u8 __iomem *csr;
+ u8 __iomem *db; /* Door Bell */
+ u8 __iomem *pcicfg; /* PCI config space */
+ int pci_func;
+
+ /* Mbox used for cmd request/response */
+ spinlock_t cmd_lock; /* For serializing cmds to BE card */
+ struct be_dma_mem mbox_mem;
+ /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
+ * is stored for freeing purpose */
+ struct be_dma_mem mbox_mem_alloced;
+};
+
+#include "be_cmds.h"
+
+struct be_drvr_stats {
+ u32 be_tx_reqs; /* number of TX requests initiated */
+ u32 be_tx_stops; /* number of times TX Q was stopped */
+ u32 be_fwd_reqs; /* number of send reqs through forwarding i/f */
+ u32 be_tx_wrbs; /* number of tx WRBs used */
+ u32 be_tx_events; /* number of tx completion events */
+ u32 be_tx_compl; /* number of tx completion entries processed */
+ u64 be_tx_jiffies;
+ ulong be_tx_bytes;
+ ulong be_tx_bytes_prev;
+ u32 be_tx_rate;
+
+ u32 cache_barrier[16];
+
+ u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */
+ u32 be_polls; /* number of times NAPI called poll function */
+ u32 be_rx_events; /* number of ucast rx completion events */
+ u32 be_rx_compl; /* number of rx completion entries processed */
+ u32 be_lro_hgram_data[8]; /* histogram of LRO data packets */
+ u32 be_lro_hgram_ack[8]; /* histogram of LRO ACKs */
+ u64 be_rx_jiffies;
+ ulong be_rx_bytes;
+ ulong be_rx_bytes_prev;
+ u32 be_rx_rate;
+ /* number of non ether type II frames dropped where
+ * frame len > length field of Mac Hdr */
+ u32 be_802_3_dropped_frames;
+ /* number of non ether type II frames malformed where
+ * in frame len < length field of Mac Hdr */
+ u32 be_802_3_malformed_frames;
+ u32 be_rxcp_err; /* Num rx completion entries w/ err set. */
+ ulong rx_fps_jiffies; /* jiffies at last FPS calc */
+ u32 be_rx_frags;
+ u32 be_prev_rx_frags;
+ u32 be_rx_fps; /* Rx frags per second */
+};
+
+struct be_stats_obj {
+ struct be_drvr_stats drvr_stats;
+ struct net_device_stats net_stats;
+ struct be_dma_mem cmd;
+};
+
+struct be_eq_obj {
+ struct be_queue_info q;
+ char desc[32];
+
+ /* Adaptive interrupt coalescing (AIC) info */
+ bool enable_aic;
+ u16 min_eqd; /* in usecs */
+ u16 max_eqd; /* in usecs */
+ u16 cur_eqd; /* in usecs */
+
+ struct napi_struct napi;
+};
+
+struct be_tx_obj {
+ struct be_queue_info q;
+ struct be_queue_info cq;
+ /* Remember the skbs that were transmitted */
+ struct sk_buff *sent_skb_list[TX_Q_LEN];
+};
+
+/* Struct to remember the pages posted for rx frags */
+struct be_rx_page_info {
+ struct page *page;
+ dma_addr_t bus;
+ u16 page_offset;
+ bool last_page_user;
+};
+
+struct be_rx_obj {
+ struct be_queue_info q;
+ struct be_queue_info cq;
+ struct be_rx_page_info page_info_tbl[RX_Q_LEN];
+ struct net_lro_mgr lro_mgr;
+ struct net_lro_desc lro_desc[BE_MAX_LRO_DESCRIPTORS];
+};
+
+#define BE_NUM_MSIX_VECTORS 2 /* 1 each for Tx and Rx */
+struct be_adapter {
+ struct pci_dev *pdev;
+ struct net_device *netdev;
+
+ /* Mbox, pci config, csr address information */
+ struct be_ctrl_info ctrl;
+
+ struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS];
+ bool msix_enabled;
+ bool isr_registered;
+
+ /* TX Rings */
+ struct be_eq_obj tx_eq;
+ struct be_tx_obj tx_obj;
+
+ u32 cache_line_break[8];
+
+ /* Rx rings */
+ struct be_eq_obj rx_eq;
+ struct be_rx_obj rx_obj;
+ u32 big_page_size; /* Compounded page size shared by rx wrbs */
+
+ struct vlan_group *vlan_grp;
+ u16 num_vlans;
+ u8 vlan_tag[VLAN_GROUP_ARRAY_LEN];
+
+ struct be_stats_obj stats;
+ /* Work queue used to perform periodic tasks like getting statistics */
+ struct delayed_work work;
+
+ /* Ethtool knobs and info */
+ bool rx_csum; /* BE card must perform rx-checksumming */
+ u32 max_rx_coal;
+ char fw_ver[FW_VER_LEN];
+ u32 if_handle; /* Used to configure filtering */
+ u32 pmac_id; /* MAC addr handle used by BE card */
+
+ struct be_link_info link;
+ u32 port_num;
+};
+
+extern struct ethtool_ops be_ethtool_ops;
+
+#define drvr_stats(adapter) (&adapter->stats.drvr_stats)
+
+#define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
+
+static inline u32 MODULO(u16 val, u16 limit)
+{
+ BUG_ON(limit & (limit - 1));
+ return val & (limit - 1);
+}
+
+static inline void index_adv(u16 *index, u16 val, u16 limit)
+{
+ *index = MODULO((*index + val), limit);
+}
+
+static inline void index_inc(u16 *index, u16 limit)
+{
+ *index = MODULO((*index + 1), limit);
+}
+
+#define PAGE_SHIFT_4K 12
+#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
+
+/* Returns number of pages spanned by the data starting at the given addr */
+#define PAGES_4K_SPANNED(_address, size) \
+ ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
+ (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
+
+/* Byte offset into the page corresponding to given address */
+#define OFFSET_IN_PAGE(addr) \
+ ((size_t)(addr) & (PAGE_SIZE_4K-1))
+
+/* Returns bit offset within a DWORD of a bitfield */
+#define AMAP_BIT_OFFSET(_struct, field) \
+ (((size_t)&(((_struct *)0)->field))%32)
+
+/* Returns the bit mask of the field that is NOT shifted into location. */
+static inline u32 amap_mask(u32 bitsize)
+{
+ return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
+}
+
+static inline void
+amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
+{
+ u32 *dw = (u32 *) ptr + dw_offset;
+ *dw &= ~(mask << offset);
+ *dw |= (mask & value) << offset;
+}
+
+#define AMAP_SET_BITS(_struct, field, ptr, val) \
+ amap_set(ptr, \
+ offsetof(_struct, field)/32, \
+ amap_mask(sizeof(((_struct *)0)->field)), \
+ AMAP_BIT_OFFSET(_struct, field), \
+ val)
+
+static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
+{
+ u32 *dw = (u32 *) ptr;
+ return mask & (*(dw + dw_offset) >> offset);
+}
+
+#define AMAP_GET_BITS(_struct, field, ptr) \
+ amap_get(ptr, \
+ offsetof(_struct, field)/32, \
+ amap_mask(sizeof(((_struct *)0)->field)), \
+ AMAP_BIT_OFFSET(_struct, field))
+
+#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
+#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
+static inline void swap_dws(void *wrb, int len)
+{
+#ifdef __BIG_ENDIAN
+ u32 *dw = wrb;
+ BUG_ON(len % 4);
+ do {
+ *dw = cpu_to_le32(*dw);
+ dw++;
+ len -= 4;
+ } while (len);
+#endif /* __BIG_ENDIAN */
+}
+
+static inline u8 is_tcp_pkt(struct sk_buff *skb)
+{
+ u8 val = 0;
+
+ if (ip_hdr(skb)->version == 4)
+ val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
+ else if (ip_hdr(skb)->version == 6)
+ val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
+
+ return val;
+}
+
+static inline u8 is_udp_pkt(struct sk_buff *skb)
+{
+ u8 val = 0;
+
+ if (ip_hdr(skb)->version == 4)
+ val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
+ else if (ip_hdr(skb)->version == 6)
+ val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
+
+ return val;
+}
+
+#endif /* BE_H */
diff --git a/drivers/net/benet/be_cmds.c b/drivers/net/benet/be_cmds.c
new file mode 100644
index 00000000000..d444aed962b
--- /dev/null
+++ b/drivers/net/benet/be_cmds.c
@@ -0,0 +1,861 @@
+/*
+ * Copyright (C) 2005 - 2009 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation. The full GNU General
+ * Public License is included in this distribution in the file called COPYING.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+
+#include "be.h"
+
+static int be_mbox_db_ready_wait(void __iomem *db)
+{
+ int cnt = 0, wait = 5;
+ u32 ready;
+
+ do {
+ ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
+ if (ready)
+ break;
+
+ if (cnt > 200000) {
+ printk(KERN_WARNING DRV_NAME
+ ": mbox_db poll timed out\n");
+ return -1;
+ }
+
+ if (cnt > 50)
+ wait = 200;
+ cnt += wait;
+ udelay(wait);
+ } while (true);
+
+ return 0;
+}
+
+/*
+ * Insert the mailbox address into the doorbell in two steps
+ */
+static int be_mbox_db_ring(struct be_ctrl_info *ctrl)
+{
+ int status;
+ u16 compl_status, extd_status;
+ u32 val = 0;
+ void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
+ struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
+ struct be_mcc_mailbox *mbox = mbox_mem->va;
+ struct be_mcc_cq_entry *cqe = &mbox->cqe;
+
+ memset(cqe, 0, sizeof(*cqe));
+
+ val &= ~MPU_MAILBOX_DB_RDY_MASK;
+ val |= MPU_MAILBOX_DB_HI_MASK;
+ /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
+ val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
+ iowrite32(val, db);
+
+ /* wait for ready to be set */
+ status = be_mbox_db_ready_wait(db);
+ if (status != 0)
+ return status;
+
+ val = 0;
+ val &= ~MPU_MAILBOX_DB_RDY_MASK;
+ val &= ~MPU_MAILBOX_DB_HI_MASK;
+ /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
+ val |= (u32)(mbox_mem->dma >> 4) << 2;
+ iowrite32(val, db);
+
+ status = be_mbox_db_ready_wait(db);
+ if (status != 0)
+ return status;
+
+ /* compl entry has been made now */
+ be_dws_le_to_cpu(cqe, sizeof(*cqe));
+ if (!(cqe->flags & CQE_FLAGS_VALID_MASK)) {
+ printk(KERN_WARNING DRV_NAME ": ERROR invalid mbox compl\n");
+ return -1;
+ }
+
+ compl_status = (cqe->status >> CQE_STATUS_COMPL_SHIFT) &
+ CQE_STATUS_COMPL_MASK;
+ if (compl_status != MCC_STATUS_SUCCESS) {
+ extd_status = (cqe->status >> CQE_STATUS_EXTD_SHIFT) &
+ CQE_STATUS_EXTD_MASK;
+ printk(KERN_WARNING DRV_NAME
+ ": ERROR in cmd compl. status(compl/extd)=%d/%d\n",
+ compl_status, extd_status);
+ }
+
+ return compl_status;
+}
+
+static int be_POST_stage_get(struct be_ctrl_info *ctrl, u16 *stage)
+{
+ u32 sem = ioread32(ctrl->csr + MPU_EP_SEMAPHORE_OFFSET);
+
+ *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
+ if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
+ return -1;
+ else
+ return 0;
+}
+
+static int be_POST_stage_poll(struct be_ctrl_info *ctrl, u16 poll_stage)
+{
+ u16 stage, cnt, error;
+ for (cnt = 0; cnt < 5000; cnt++) {
+ error = be_POST_stage_get(ctrl, &stage);
+ if (error)
+ return -1;
+
+ if (stage == poll_stage)
+ break;
+ udelay(1000);
+ }
+ if (stage != poll_stage)
+ return -1;
+ return 0;
+}
+
+
+int be_cmd_POST(struct be_ctrl_info *ctrl)
+{
+ u16 stage, error;
+
+ error = be_POST_stage_get(ctrl, &stage);
+ if (error)
+ goto err;
+
+ if (stage == POST_STAGE_ARMFW_RDY)
+ return 0;
+
+ if (stage != POST_STAGE_AWAITING_HOST_RDY)
+ goto err;
+
+ /* On awaiting host rdy, reset and again poll on awaiting host rdy */
+ iowrite32(POST_STAGE_BE_RESET, ctrl->csr + MPU_EP_SEMAPHORE_OFFSET);
+ error = be_POST_stage_poll(ctrl, POST_STAGE_AWAITING_HOST_RDY);
+ if (error)
+ goto err;
+
+ /* Now kickoff POST and poll on armfw ready */
+ iowrite32(POST_STAGE_HOST_RDY, ctrl->csr + MPU_EP_SEMAPHORE_OFFSET);
+ error = be_POST_stage_poll(ctrl, POST_STAGE_ARMFW_RDY);
+ if (error)
+ goto err;
+
+ return 0;
+err:
+ printk(KERN_WARNING DRV_NAME ": ERROR, stage=%d\n", stage);
+ return -1;
+}
+
+static inline void *embedded_payload(struct be_mcc_wrb *wrb)
+{
+ return wrb->payload.embedded_payload;
+}
+
+static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
+{
+ return &wrb->payload.sgl[0];
+}
+
+/* Don't touch the hdr after it's prepared */
+static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
+ bool embedded, u8 sge_cnt)
+{
+ if (embedded)
+ wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
+ else
+ wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
+ MCC_WRB_SGE_CNT_SHIFT;
+ wrb->payload_length = payload_len;
+ be_dws_cpu_to_le(wrb, 20);
+}
+
+/* Don't touch the hdr after it's prepared */
+static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
+ u8 subsystem, u8 opcode, int cmd_len)
+{
+ req_hdr->opcode = opcode;
+ req_hdr->subsystem = subsystem;
+ req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
+}
+
+static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
+ struct be_dma_mem *mem)
+{
+ int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
+ u64 dma = (u64)mem->dma;
+
+ for (i = 0; i < buf_pages; i++) {
+ pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
+ pages[i].hi = cpu_to_le32(upper_32_bits(dma));
+ dma += PAGE_SIZE_4K;
+ }
+}
+
+/* Converts interrupt delay in microseconds to multiplier value */
+static u32 eq_delay_to_mult(u32 usec_delay)
+{
+#define MAX_INTR_RATE 651042
+ const u32 round = 10;
+ u32 multiplier;
+
+ if (usec_delay == 0)
+ multiplier = 0;
+ else {
+ u32 interrupt_rate = 1000000 / usec_delay;
+ /* Max delay, corresponding to the lowest interrupt rate */
+ if (interrupt_rate == 0)
+ multiplier = 1023;
+ else {
+ multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
+ multiplier /= interrupt_rate;
+ /* Round the multiplier to the closest value.*/
+ multiplier = (multiplier + round/2) / round;
+ multiplier = min(multiplier, (u32)1023);
+ }
+ }
+ return multiplier;
+}
+
+static inline struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
+{
+ return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
+}
+
+int be_cmd_eq_create(struct be_ctrl_info *ctrl,
+ struct be_queue_info *eq, int eq_delay)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_eq_create *req = embedded_payload(wrb);
+ struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
+ struct be_dma_mem *q_mem = &eq->dma_mem;
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_EQ_CREATE, sizeof(*req));
+
+ req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
+
+ AMAP_SET_BITS(struct amap_eq_context, func, req->context,
+ ctrl->pci_func);
+ AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
+ /* 4byte eqe*/
+ AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
+ AMAP_SET_BITS(struct amap_eq_context, count, req->context,
+ __ilog2_u32(eq->len/256));
+ AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
+ eq_delay_to_mult(eq_delay));
+ be_dws_cpu_to_le(req->context, sizeof(req->context));
+
+ be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
+
+ status = be_mbox_db_ring(ctrl);
+ if (!status) {
+ eq->id = le16_to_cpu(resp->eq_id);
+ eq->created = true;
+ }
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
+
+int be_cmd_mac_addr_query(struct be_ctrl_info *ctrl, u8 *mac_addr,
+ u8 type, bool permanent, u32 if_handle)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_mac_query *req = embedded_payload(wrb);
+ struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
+
+ req->type = type;
+ if (permanent) {
+ req->permanent = 1;
+ } else {
+ req->if_id = cpu_to_le16((u16)if_handle);
+ req->permanent = 0;
+ }
+
+ status = be_mbox_db_ring(ctrl);
+ if (!status)
+ memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
+
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
+
+int be_cmd_pmac_add(struct be_ctrl_info *ctrl, u8 *mac_addr,
+ u32 if_id, u32 *pmac_id)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_pmac_add *req = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
+
+ req->if_id = cpu_to_le32(if_id);
+ memcpy(req->mac_address, mac_addr, ETH_ALEN);
+
+ status = be_mbox_db_ring(ctrl);
+ if (!status) {
+ struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
+ *pmac_id = le32_to_cpu(resp->pmac_id);
+ }
+
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
+
+int be_cmd_pmac_del(struct be_ctrl_info *ctrl, u32 if_id, u32 pmac_id)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_pmac_del *req = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
+
+ req->if_id = cpu_to_le32(if_id);
+ req->pmac_id = cpu_to_le32(pmac_id);
+
+ status = be_mbox_db_ring(ctrl);
+ spin_unlock(&ctrl->cmd_lock);
+
+ return status;
+}
+
+int be_cmd_cq_create(struct be_ctrl_info *ctrl,
+ struct be_queue_info *cq, struct be_queue_info *eq,
+ bool sol_evts, bool no_delay, int coalesce_wm)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_cq_create *req = embedded_payload(wrb);
+ struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
+ struct be_dma_mem *q_mem = &cq->dma_mem;
+ void *ctxt = &req->context;
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_CQ_CREATE, sizeof(*req));
+
+ req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
+
+ AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
+ AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
+ AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
+ __ilog2_u32(cq->len/256));
+ AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
+ AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
+ AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
+ AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
+ AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 0);
+ AMAP_SET_BITS(struct amap_cq_context, func, ctxt, ctrl->pci_func);
+ be_dws_cpu_to_le(ctxt, sizeof(req->context));
+
+ be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
+
+ status = be_mbox_db_ring(ctrl);
+ if (!status) {
+ cq->id = le16_to_cpu(resp->cq_id);
+ cq->created = true;
+ }
+ spin_unlock(&ctrl->cmd_lock);
+
+ return status;
+}
+
+int be_cmd_txq_create(struct be_ctrl_info *ctrl,
+ struct be_queue_info *txq,
+ struct be_queue_info *cq)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_eth_tx_create *req = embedded_payload(wrb);
+ struct be_dma_mem *q_mem = &txq->dma_mem;
+ void *ctxt = &req->context;
+ int status;
+ u32 len_encoded;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
+ sizeof(*req));
+
+ req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
+ req->ulp_num = BE_ULP1_NUM;
+ req->type = BE_ETH_TX_RING_TYPE_STANDARD;
+
+ len_encoded = fls(txq->len); /* log2(len) + 1 */
+ if (len_encoded == 16)
+ len_encoded = 0;
+ AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, len_encoded);
+ AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt,
+ ctrl->pci_func);
+ AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
+ AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
+
+ be_dws_cpu_to_le(ctxt, sizeof(req->context));
+
+ be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
+
+ status = be_mbox_db_ring(ctrl);
+ if (!status) {
+ struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
+ txq->id = le16_to_cpu(resp->cid);
+ txq->created = true;
+ }
+ spin_unlock(&ctrl->cmd_lock);
+
+ return status;
+}
+
+int be_cmd_rxq_create(struct be_ctrl_info *ctrl,
+ struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
+ u16 max_frame_size, u32 if_id, u32 rss)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_eth_rx_create *req = embedded_payload(wrb);
+ struct be_dma_mem *q_mem = &rxq->dma_mem;
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
+ sizeof(*req));
+
+ req->cq_id = cpu_to_le16(cq_id);
+ req->frag_size = fls(frag_size) - 1;
+ req->num_pages = 2;
+ be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
+ req->interface_id = cpu_to_le32(if_id);
+ req->max_frame_size = cpu_to_le16(max_frame_size);
+ req->rss_queue = cpu_to_le32(rss);
+
+ status = be_mbox_db_ring(ctrl);
+ if (!status) {
+ struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
+ rxq->id = le16_to_cpu(resp->id);
+ rxq->created = true;
+ }
+ spin_unlock(&ctrl->cmd_lock);
+
+ return status;
+}
+
+/* Generic destroyer function for all types of queues */
+int be_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
+ int queue_type)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
+ u8 subsys = 0, opcode = 0;
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+
+ memset(wrb, 0, sizeof(*wrb));
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ switch (queue_type) {
+ case QTYPE_EQ:
+ subsys = CMD_SUBSYSTEM_COMMON;
+ opcode = OPCODE_COMMON_EQ_DESTROY;
+ break;
+ case QTYPE_CQ:
+ subsys = CMD_SUBSYSTEM_COMMON;
+ opcode = OPCODE_COMMON_CQ_DESTROY;
+ break;
+ case QTYPE_TXQ:
+ subsys = CMD_SUBSYSTEM_ETH;
+ opcode = OPCODE_ETH_TX_DESTROY;
+ break;
+ case QTYPE_RXQ:
+ subsys = CMD_SUBSYSTEM_ETH;
+ opcode = OPCODE_ETH_RX_DESTROY;
+ break;
+ default:
+ printk(KERN_WARNING DRV_NAME ":bad Q type in Q destroy cmd\n");
+ status = -1;
+ goto err;
+ }
+ be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
+ req->id = cpu_to_le16(q->id);
+
+ status = be_mbox_db_ring(ctrl);
+err:
+ spin_unlock(&ctrl->cmd_lock);
+
+ return status;
+}
+
+/* Create an rx filtering policy configuration on an i/f */
+int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 flags, u8 *mac,
+ bool pmac_invalid, u32 *if_handle, u32 *pmac_id)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_if_create *req = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
+
+ req->capability_flags = cpu_to_le32(flags);
+ req->enable_flags = cpu_to_le32(flags);
+ if (!pmac_invalid)
+ memcpy(req->mac_addr, mac, ETH_ALEN);
+
+ status = be_mbox_db_ring(ctrl);
+ if (!status) {
+ struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
+ *if_handle = le32_to_cpu(resp->interface_id);
+ if (!pmac_invalid)
+ *pmac_id = le32_to_cpu(resp->pmac_id);
+ }
+
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
+
+int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 interface_id)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_if_destroy *req = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
+
+ req->interface_id = cpu_to_le32(interface_id);
+ status = be_mbox_db_ring(ctrl);
+
+ spin_unlock(&ctrl->cmd_lock);
+
+ return status;
+}
+
+/* Get stats is a non embedded command: the request is not embedded inside
+ * WRB but is a separate dma memory block
+ */
+int be_cmd_get_stats(struct be_ctrl_info *ctrl, struct be_dma_mem *nonemb_cmd)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_get_stats *req = nonemb_cmd->va;
+ struct be_sge *sge = nonembedded_sgl(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ memset(req, 0, sizeof(*req));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
+ OPCODE_ETH_GET_STATISTICS, sizeof(*req));
+ sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
+ sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
+ sge->len = cpu_to_le32(nonemb_cmd->size);
+
+ status = be_mbox_db_ring(ctrl);
+ if (!status) {
+ struct be_cmd_resp_get_stats *resp = nonemb_cmd->va;
+ be_dws_le_to_cpu(&resp->hw_stats, sizeof(resp->hw_stats));
+ }
+
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
+
+int be_cmd_link_status_query(struct be_ctrl_info *ctrl,
+ struct be_link_info *link)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_link_status *req = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
+
+ status = be_mbox_db_ring(ctrl);
+ if (!status) {
+ struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
+ link->speed = resp->mac_speed;
+ link->duplex = resp->mac_duplex;
+ link->fault = resp->mac_fault;
+ } else {
+ link->speed = PHY_LINK_SPEED_ZERO;
+ }
+
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
+
+int be_cmd_get_fw_ver(struct be_ctrl_info *ctrl, char *fw_ver)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_get_fw_version *req = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
+
+ status = be_mbox_db_ring(ctrl);
+ if (!status) {
+ struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
+ strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
+ }
+
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
+
+/* set the EQ delay interval of an EQ to specified value */
+int be_cmd_modify_eqd(struct be_ctrl_info *ctrl, u32 eq_id, u32 eqd)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_modify_eq_delay *req = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
+
+ req->num_eq = cpu_to_le32(1);
+ req->delay[0].eq_id = cpu_to_le32(eq_id);
+ req->delay[0].phase = 0;
+ req->delay[0].delay_multiplier = cpu_to_le32(eqd);
+
+ status = be_mbox_db_ring(ctrl);
+
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
+
+int be_cmd_vlan_config(struct be_ctrl_info *ctrl, u32 if_id, u16 *vtag_array,
+ u32 num, bool untagged, bool promiscuous)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_vlan_config *req = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
+
+ req->interface_id = if_id;
+ req->promiscuous = promiscuous;
+ req->untagged = untagged;
+ req->num_vlan = num;
+ if (!promiscuous) {
+ memcpy(req->normal_vlan, vtag_array,
+ req->num_vlan * sizeof(vtag_array[0]));
+ }
+
+ status = be_mbox_db_ring(ctrl);
+
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
+
+int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl, u8 port_num, bool en)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_promiscuous_config *req = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
+ OPCODE_ETH_PROMISCUOUS, sizeof(*req));
+
+ if (port_num)
+ req->port1_promiscuous = en;
+ else
+ req->port0_promiscuous = en;
+
+ status = be_mbox_db_ring(ctrl);
+
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
+
+int be_cmd_mcast_mac_set(struct be_ctrl_info *ctrl, u32 if_id, u8 *mac_table,
+ u32 num, bool promiscuous)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_mcast_mac_config *req = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
+
+ req->interface_id = if_id;
+ req->promiscuous = promiscuous;
+ if (!promiscuous) {
+ req->num_mac = cpu_to_le16(num);
+ if (num)
+ memcpy(req->mac, mac_table, ETH_ALEN * num);
+ }
+
+ status = be_mbox_db_ring(ctrl);
+
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
+
+int be_cmd_set_flow_control(struct be_ctrl_info *ctrl, u32 tx_fc, u32 rx_fc)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_set_flow_control *req = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
+
+ req->tx_flow_control = cpu_to_le16((u16)tx_fc);
+ req->rx_flow_control = cpu_to_le16((u16)rx_fc);
+
+ status = be_mbox_db_ring(ctrl);
+
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
+
+int be_cmd_get_flow_control(struct be_ctrl_info *ctrl, u32 *tx_fc, u32 *rx_fc)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_get_flow_control *req = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
+
+ status = be_mbox_db_ring(ctrl);
+ if (!status) {
+ struct be_cmd_resp_get_flow_control *resp =
+ embedded_payload(wrb);
+ *tx_fc = le16_to_cpu(resp->tx_flow_control);
+ *rx_fc = le16_to_cpu(resp->rx_flow_control);
+ }
+
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
+
+int be_cmd_query_fw_cfg(struct be_ctrl_info *ctrl, u32 *port_num)
+{
+ struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
+ struct be_cmd_req_query_fw_cfg *req = embedded_payload(wrb);
+ int status;
+
+ spin_lock(&ctrl->cmd_lock);
+
+ memset(wrb, 0, sizeof(*wrb));
+
+ be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
+
+ be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
+ OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
+
+ status = be_mbox_db_ring(ctrl);
+ if (!status) {
+ struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
+ *port_num = le32_to_cpu(resp->phys_port);
+ }
+
+ spin_unlock(&ctrl->cmd_lock);
+ return status;
+}
diff --git a/drivers/net/benet/be_cmds.h b/drivers/net/benet/be_cmds.h
new file mode 100644
index 00000000000..e499e2d5b8c
--- /dev/null
+++ b/drivers/net/benet/be_cmds.h
@@ -0,0 +1,688 @@
+/*
+ * Copyright (C) 2005 - 2009 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation. The full GNU General
+ * Public License is included in this distribution in the file called COPYING.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+
+/*
+ * The driver sends configuration and managements command requests to the
+ * firmware in the BE. These requests are communicated to the processor
+ * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
+ * WRB inside a MAILBOX.
+ * The commands are serviced by the ARM processor in the BladeEngine's MPU.
+ */
+
+struct be_sge {
+ u32 pa_lo;
+ u32 pa_hi;
+ u32 len;
+};
+
+#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
+#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
+#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
+struct be_mcc_wrb {
+ u32 embedded; /* dword 0 */
+ u32 payload_length; /* dword 1 */
+ u32 tag0; /* dword 2 */
+ u32 tag1; /* dword 3 */
+ u32 rsvd; /* dword 4 */
+ union {
+ u8 embedded_payload[236]; /* used by embedded cmds */
+ struct be_sge sgl[19]; /* used by non-embedded cmds */
+ } payload;
+};
+
+#define CQE_FLAGS_VALID_MASK (1 << 31)
+#define CQE_FLAGS_ASYNC_MASK (1 << 30)
+#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
+#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
+
+/* Completion Status */
+enum {
+ MCC_STATUS_SUCCESS = 0x0,
+/* The client does not have sufficient privileges to execute the command */
+ MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
+/* A parameter in the command was invalid. */
+ MCC_STATUS_INVALID_PARAMETER = 0x2,
+/* There are insufficient chip resources to execute the command */
+ MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
+/* The command is completing because the queue was getting flushed */
+ MCC_STATUS_QUEUE_FLUSHING = 0x4,
+/* The command is completing with a DMA error */
+ MCC_STATUS_DMA_FAILED = 0x5
+};
+
+#define CQE_STATUS_COMPL_MASK 0xFFFF
+#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
+#define CQE_STATUS_EXTD_MASK 0xFFFF
+#define CQE_STATUS_EXTD_SHIFT 0 /* bits 0 - 15 */
+
+struct be_mcc_cq_entry {
+ u32 status; /* dword 0 */
+ u32 tag0; /* dword 1 */
+ u32 tag1; /* dword 2 */
+ u32 flags; /* dword 3 */
+};
+
+struct be_mcc_mailbox {
+ struct be_mcc_wrb wrb;
+ struct be_mcc_cq_entry cqe;
+};
+
+#define CMD_SUBSYSTEM_COMMON 0x1
+#define CMD_SUBSYSTEM_ETH 0x3
+
+#define OPCODE_COMMON_NTWK_MAC_QUERY 1
+#define OPCODE_COMMON_NTWK_MAC_SET 2
+#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
+#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
+#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
+#define OPCODE_COMMON_CQ_CREATE 12
+#define OPCODE_COMMON_EQ_CREATE 13
+#define OPCODE_COMMON_MCC_CREATE 21
+#define OPCODE_COMMON_NTWK_RX_FILTER 34
+#define OPCODE_COMMON_GET_FW_VERSION 35
+#define OPCODE_COMMON_SET_FLOW_CONTROL 36
+#define OPCODE_COMMON_GET_FLOW_CONTROL 37
+#define OPCODE_COMMON_SET_FRAME_SIZE 39
+#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
+#define OPCODE_COMMON_FIRMWARE_CONFIG 42
+#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
+#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
+#define OPCODE_COMMON_CQ_DESTROY 54
+#define OPCODE_COMMON_EQ_DESTROY 55
+#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
+#define OPCODE_COMMON_NTWK_PMAC_ADD 59
+#define OPCODE_COMMON_NTWK_PMAC_DEL 60
+
+#define OPCODE_ETH_ACPI_CONFIG 2
+#define OPCODE_ETH_PROMISCUOUS 3
+#define OPCODE_ETH_GET_STATISTICS 4
+#define OPCODE_ETH_TX_CREATE 7
+#define OPCODE_ETH_RX_CREATE 8
+#define OPCODE_ETH_TX_DESTROY 9
+#define OPCODE_ETH_RX_DESTROY 10
+
+struct be_cmd_req_hdr {
+ u8 opcode; /* dword 0 */
+ u8 subsystem; /* dword 0 */
+ u8 port_number; /* dword 0 */
+ u8 domain; /* dword 0 */
+ u32 timeout; /* dword 1 */
+ u32 request_length; /* dword 2 */
+ u32 rsvd; /* dword 3 */
+};
+
+#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
+#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
+struct be_cmd_resp_hdr {
+ u32 info; /* dword 0 */
+ u32 status; /* dword 1 */
+ u32 response_length; /* dword 2 */
+ u32 actual_resp_len; /* dword 3 */
+};
+
+struct phys_addr {
+ u32 lo;
+ u32 hi;
+};
+
+/**************************
+ * BE Command definitions *
+ **************************/
+
+/* Pseudo amap definition in which each bit of the actual structure is defined
+ * as a byte: used to calculate offset/shift/mask of each field */
+struct amap_eq_context {
+ u8 cidx[13]; /* dword 0*/
+ u8 rsvd0[3]; /* dword 0*/
+ u8 epidx[13]; /* dword 0*/
+ u8 valid; /* dword 0*/
+ u8 rsvd1; /* dword 0*/
+ u8 size; /* dword 0*/
+ u8 pidx[13]; /* dword 1*/
+ u8 rsvd2[3]; /* dword 1*/
+ u8 pd[10]; /* dword 1*/
+ u8 count[3]; /* dword 1*/
+ u8 solevent; /* dword 1*/
+ u8 stalled; /* dword 1*/
+ u8 armed; /* dword 1*/
+ u8 rsvd3[4]; /* dword 2*/
+ u8 func[8]; /* dword 2*/
+ u8 rsvd4; /* dword 2*/
+ u8 delaymult[10]; /* dword 2*/
+ u8 rsvd5[2]; /* dword 2*/
+ u8 phase[2]; /* dword 2*/
+ u8 nodelay; /* dword 2*/
+ u8 rsvd6[4]; /* dword 2*/
+ u8 rsvd7[32]; /* dword 3*/
+} __packed;
+
+struct be_cmd_req_eq_create {
+ struct be_cmd_req_hdr hdr;
+ u16 num_pages; /* sword */
+ u16 rsvd0; /* sword */
+ u8 context[sizeof(struct amap_eq_context) / 8];
+ struct phys_addr pages[8];
+} __packed;
+
+struct be_cmd_resp_eq_create {
+ struct be_cmd_resp_hdr resp_hdr;
+ u16 eq_id; /* sword */
+ u16 rsvd0; /* sword */
+} __packed;
+
+/******************** Mac query ***************************/
+enum {
+ MAC_ADDRESS_TYPE_STORAGE = 0x0,
+ MAC_ADDRESS_TYPE_NETWORK = 0x1,
+ MAC_ADDRESS_TYPE_PD = 0x2,
+ MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
+};
+
+struct mac_addr {
+ u16 size_of_struct;
+ u8 addr[ETH_ALEN];
+} __packed;
+
+struct be_cmd_req_mac_query {
+ struct be_cmd_req_hdr hdr;
+ u8 type;
+ u8 permanent;
+ u16 if_id;
+} __packed;
+
+struct be_cmd_resp_mac_query {
+ struct be_cmd_resp_hdr hdr;
+ struct mac_addr mac;
+};
+
+/******************** PMac Add ***************************/
+struct be_cmd_req_pmac_add {
+ struct be_cmd_req_hdr hdr;
+ u32 if_id;
+ u8 mac_address[ETH_ALEN];
+ u8 rsvd0[2];
+} __packed;
+
+struct be_cmd_resp_pmac_add {
+ struct be_cmd_resp_hdr hdr;
+ u32 pmac_id;
+};
+
+/******************** PMac Del ***************************/
+struct be_cmd_req_pmac_del {
+ struct be_cmd_req_hdr hdr;
+ u32 if_id;
+ u32 pmac_id;
+};
+
+/******************** Create CQ ***************************/
+/* Pseudo amap definition in which each bit of the actual structure is defined
+ * as a byte: used to calculate offset/shift/mask of each field */
+struct amap_cq_context {
+ u8 cidx[11]; /* dword 0*/
+ u8 rsvd0; /* dword 0*/
+ u8 coalescwm[2]; /* dword 0*/
+ u8 nodelay; /* dword 0*/
+ u8 epidx[11]; /* dword 0*/
+ u8 rsvd1; /* dword 0*/
+ u8 count[2]; /* dword 0*/
+ u8 valid; /* dword 0*/
+ u8 solevent; /* dword 0*/
+ u8 eventable; /* dword 0*/
+ u8 pidx[11]; /* dword 1*/
+ u8 rsvd2; /* dword 1*/
+ u8 pd[10]; /* dword 1*/
+ u8 eqid[8]; /* dword 1*/
+ u8 stalled; /* dword 1*/
+ u8 armed; /* dword 1*/
+ u8 rsvd3[4]; /* dword 2*/
+ u8 func[8]; /* dword 2*/
+ u8 rsvd4[20]; /* dword 2*/
+ u8 rsvd5[32]; /* dword 3*/
+} __packed;
+
+struct be_cmd_req_cq_create {
+ struct be_cmd_req_hdr hdr;
+ u16 num_pages;
+ u16 rsvd0;
+ u8 context[sizeof(struct amap_cq_context) / 8];
+ struct phys_addr pages[8];
+} __packed;
+
+struct be_cmd_resp_cq_create {
+ struct be_cmd_resp_hdr hdr;
+ u16 cq_id;
+ u16 rsvd0;
+} __packed;
+
+/******************** Create TxQ ***************************/
+#define BE_ETH_TX_RING_TYPE_STANDARD 2
+#define BE_ULP1_NUM 1
+
+/* Pseudo amap definition in which each bit of the actual structure is defined
+ * as a byte: used to calculate offset/shift/mask of each field */
+struct amap_tx_context {
+ u8 rsvd0[16]; /* dword 0 */
+ u8 tx_ring_size[4]; /* dword 0 */
+ u8 rsvd1[26]; /* dword 0 */
+ u8 pci_func_id[8]; /* dword 1 */
+ u8 rsvd2[9]; /* dword 1 */
+ u8 ctx_valid; /* dword 1 */
+ u8 cq_id_send[16]; /* dword 2 */
+ u8 rsvd3[16]; /* dword 2 */
+ u8 rsvd4[32]; /* dword 3 */
+ u8 rsvd5[32]; /* dword 4 */
+ u8 rsvd6[32]; /* dword 5 */
+ u8 rsvd7[32]; /* dword 6 */
+ u8 rsvd8[32]; /* dword 7 */
+ u8 rsvd9[32]; /* dword 8 */
+ u8 rsvd10[32]; /* dword 9 */
+ u8 rsvd11[32]; /* dword 10 */
+ u8 rsvd12[32]; /* dword 11 */
+ u8 rsvd13[32]; /* dword 12 */
+ u8 rsvd14[32]; /* dword 13 */
+ u8 rsvd15[32]; /* dword 14 */
+ u8 rsvd16[32]; /* dword 15 */
+} __packed;
+
+struct be_cmd_req_eth_tx_create {
+ struct be_cmd_req_hdr hdr;
+ u8 num_pages;
+ u8 ulp_num;
+ u8 type;
+ u8 bound_port;
+ u8 context[sizeof(struct amap_tx_context) / 8];
+ struct phys_addr pages[8];
+} __packed;
+
+struct be_cmd_resp_eth_tx_create {
+ struct be_cmd_resp_hdr hdr;
+ u16 cid;
+ u16 rsvd0;
+} __packed;
+
+/******************** Create RxQ ***************************/
+struct be_cmd_req_eth_rx_create {
+ struct be_cmd_req_hdr hdr;
+ u16 cq_id;
+ u8 frag_size;
+ u8 num_pages;
+ struct phys_addr pages[2];
+ u32 interface_id;
+ u16 max_frame_size;
+ u16 rsvd0;
+ u32 rss_queue;
+} __packed;
+
+struct be_cmd_resp_eth_rx_create {
+ struct be_cmd_resp_hdr hdr;
+ u16 id;
+ u8 cpu_id;
+ u8 rsvd0;
+} __packed;
+
+/******************** Q Destroy ***************************/
+/* Type of Queue to be destroyed */
+enum {
+ QTYPE_EQ = 1,
+ QTYPE_CQ,
+ QTYPE_TXQ,
+ QTYPE_RXQ
+};
+
+struct be_cmd_req_q_destroy {
+ struct be_cmd_req_hdr hdr;
+ u16 id;
+ u16 bypass_flush; /* valid only for rx q destroy */
+} __packed;
+
+/************ I/f Create (it's actually I/f Config Create)**********/
+
+/* Capability flags for the i/f */
+enum be_if_flags {
+ BE_IF_FLAGS_RSS = 0x4,
+ BE_IF_FLAGS_PROMISCUOUS = 0x8,
+ BE_IF_FLAGS_BROADCAST = 0x10,
+ BE_IF_FLAGS_UNTAGGED = 0x20,
+ BE_IF_FLAGS_ULP = 0x40,
+ BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
+ BE_IF_FLAGS_VLAN = 0x100,
+ BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
+ BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
+ BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
+};
+
+/* An RX interface is an object with one or more MAC addresses and
+ * filtering capabilities. */
+struct be_cmd_req_if_create {
+ struct be_cmd_req_hdr hdr;
+ u32 version; /* ignore currntly */
+ u32 capability_flags;
+ u32 enable_flags;
+ u8 mac_addr[ETH_ALEN];
+ u8 rsvd0;
+ u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
+ u32 vlan_tag; /* not used currently */
+} __packed;
+
+struct be_cmd_resp_if_create {
+ struct be_cmd_resp_hdr hdr;
+ u32 interface_id;
+ u32 pmac_id;
+};
+
+/****** I/f Destroy(it's actually I/f Config Destroy )**********/
+struct be_cmd_req_if_destroy {
+ struct be_cmd_req_hdr hdr;
+ u32 interface_id;
+};
+
+/*************** HW Stats Get **********************************/
+struct be_port_rxf_stats {
+ u32 rx_bytes_lsd; /* dword 0*/
+ u32 rx_bytes_msd; /* dword 1*/
+ u32 rx_total_frames; /* dword 2*/
+ u32 rx_unicast_frames; /* dword 3*/
+ u32 rx_multicast_frames; /* dword 4*/
+ u32 rx_broadcast_frames; /* dword 5*/
+ u32 rx_crc_errors; /* dword 6*/
+ u32 rx_alignment_symbol_errors; /* dword 7*/
+ u32 rx_pause_frames; /* dword 8*/
+ u32 rx_control_frames; /* dword 9*/
+ u32 rx_in_range_errors; /* dword 10*/
+ u32 rx_out_range_errors; /* dword 11*/
+ u32 rx_frame_too_long; /* dword 12*/
+ u32 rx_address_match_errors; /* dword 13*/
+ u32 rx_vlan_mismatch; /* dword 14*/
+ u32 rx_dropped_too_small; /* dword 15*/
+ u32 rx_dropped_too_short; /* dword 16*/
+ u32 rx_dropped_header_too_small; /* dword 17*/
+ u32 rx_dropped_tcp_length; /* dword 18*/
+ u32 rx_dropped_runt; /* dword 19*/
+ u32 rx_64_byte_packets; /* dword 20*/
+ u32 rx_65_127_byte_packets; /* dword 21*/
+ u32 rx_128_256_byte_packets; /* dword 22*/
+ u32 rx_256_511_byte_packets; /* dword 23*/
+ u32 rx_512_1023_byte_packets; /* dword 24*/
+ u32 rx_1024_1518_byte_packets; /* dword 25*/
+ u32 rx_1519_2047_byte_packets; /* dword 26*/
+ u32 rx_2048_4095_byte_packets; /* dword 27*/
+ u32 rx_4096_8191_byte_packets; /* dword 28*/
+ u32 rx_8192_9216_byte_packets; /* dword 29*/
+ u32 rx_ip_checksum_errs; /* dword 30*/
+ u32 rx_tcp_checksum_errs; /* dword 31*/
+ u32 rx_udp_checksum_errs; /* dword 32*/
+ u32 rx_non_rss_packets; /* dword 33*/
+ u32 rx_ipv4_packets; /* dword 34*/
+ u32 rx_ipv6_packets; /* dword 35*/
+ u32 rx_ipv4_bytes_lsd; /* dword 36*/
+ u32 rx_ipv4_bytes_msd; /* dword 37*/
+ u32 rx_ipv6_bytes_lsd; /* dword 38*/
+ u32 rx_ipv6_bytes_msd; /* dword 39*/
+ u32 rx_chute1_packets; /* dword 40*/
+ u32 rx_chute2_packets; /* dword 41*/
+ u32 rx_chute3_packets; /* dword 42*/
+ u32 rx_management_packets; /* dword 43*/
+ u32 rx_switched_unicast_packets; /* dword 44*/
+ u32 rx_switched_multicast_packets; /* dword 45*/
+ u32 rx_switched_broadcast_packets; /* dword 46*/
+ u32 tx_bytes_lsd; /* dword 47*/
+ u32 tx_bytes_msd; /* dword 48*/
+ u32 tx_unicastframes; /* dword 49*/
+ u32 tx_multicastframes; /* dword 50*/
+ u32 tx_broadcastframes; /* dword 51*/
+ u32 tx_pauseframes; /* dword 52*/
+ u32 tx_controlframes; /* dword 53*/
+ u32 tx_64_byte_packets; /* dword 54*/
+ u32 tx_65_127_byte_packets; /* dword 55*/
+ u32 tx_128_256_byte_packets; /* dword 56*/
+ u32 tx_256_511_byte_packets; /* dword 57*/
+ u32 tx_512_1023_byte_packets; /* dword 58*/
+ u32 tx_1024_1518_byte_packets; /* dword 59*/
+ u32 tx_1519_2047_byte_packets; /* dword 60*/
+ u32 tx_2048_4095_byte_packets; /* dword 61*/
+ u32 tx_4096_8191_byte_packets; /* dword 62*/
+ u32 tx_8192_9216_byte_packets; /* dword 63*/
+ u32 rx_fifo_overflow; /* dword 64*/
+ u32 rx_input_fifo_overflow; /* dword 65*/
+};
+
+struct be_rxf_stats {
+ struct be_port_rxf_stats port[2];
+ u32 rx_drops_no_pbuf; /* dword 132*/
+ u32 rx_drops_no_txpb; /* dword 133*/
+ u32 rx_drops_no_erx_descr; /* dword 134*/
+ u32 rx_drops_no_tpre_descr; /* dword 135*/
+ u32 management_rx_port_packets; /* dword 136*/
+ u32 management_rx_port_bytes; /* dword 137*/
+ u32 management_rx_port_pause_frames; /* dword 138*/
+ u32 management_rx_port_errors; /* dword 139*/
+ u32 management_tx_port_packets; /* dword 140*/
+ u32 management_tx_port_bytes; /* dword 141*/
+ u32 management_tx_port_pause; /* dword 142*/
+ u32 management_rx_port_rxfifo_overflow; /* dword 143*/
+ u32 rx_drops_too_many_frags; /* dword 144*/
+ u32 rx_drops_invalid_ring; /* dword 145*/
+ u32 forwarded_packets; /* dword 146*/
+ u32 rx_drops_mtu; /* dword 147*/
+ u32 rsvd0[15];
+};
+
+struct be_erx_stats {
+ u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
+ u32 debug_wdma_sent_hold; /* dword 44*/
+ u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
+ u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
+ u32 debug_pmem_pbuf_dealloc; /* dword 47*/
+};
+
+struct be_hw_stats {
+ struct be_rxf_stats rxf;
+ u32 rsvd[48];
+ struct be_erx_stats erx;
+};
+
+struct be_cmd_req_get_stats {
+ struct be_cmd_req_hdr hdr;
+ u8 rsvd[sizeof(struct be_hw_stats)];
+};
+
+struct be_cmd_resp_get_stats {
+ struct be_cmd_resp_hdr hdr;
+ struct be_hw_stats hw_stats;
+};
+
+struct be_cmd_req_vlan_config {
+ struct be_cmd_req_hdr hdr;
+ u8 interface_id;
+ u8 promiscuous;
+ u8 untagged;
+ u8 num_vlan;
+ u16 normal_vlan[64];
+} __packed;
+
+struct be_cmd_req_promiscuous_config {
+ struct be_cmd_req_hdr hdr;
+ u8 port0_promiscuous;
+ u8 port1_promiscuous;
+ u16 rsvd0;
+} __packed;
+
+struct macaddr {
+ u8 byte[ETH_ALEN];
+};
+
+struct be_cmd_req_mcast_mac_config {
+ struct be_cmd_req_hdr hdr;
+ u16 num_mac;
+ u8 promiscuous;
+ u8 interface_id;
+ struct macaddr mac[32];
+} __packed;
+
+static inline struct be_hw_stats *
+hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
+{
+ return &cmd->hw_stats;
+}
+
+/******************** Link Status Query *******************/
+struct be_cmd_req_link_status {
+ struct be_cmd_req_hdr hdr;
+ u32 rsvd;
+};
+
+struct be_link_info {
+ u8 duplex;
+ u8 speed;
+ u8 fault;
+};
+
+enum {
+ PHY_LINK_DUPLEX_NONE = 0x0,
+ PHY_LINK_DUPLEX_HALF = 0x1,
+ PHY_LINK_DUPLEX_FULL = 0x2
+};
+
+enum {
+ PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
+ PHY_LINK_SPEED_10MBPS = 0x1,
+ PHY_LINK_SPEED_100MBPS = 0x2,
+ PHY_LINK_SPEED_1GBPS = 0x3,
+ PHY_LINK_SPEED_10GBPS = 0x4
+};
+
+struct be_cmd_resp_link_status {
+ struct be_cmd_resp_hdr hdr;
+ u8 physical_port;
+ u8 mac_duplex;
+ u8 mac_speed;
+ u8 mac_fault;
+ u8 mgmt_mac_duplex;
+ u8 mgmt_mac_speed;
+ u16 rsvd0;
+} __packed;
+
+/******************** Get FW Version *******************/
+#define FW_VER_LEN 32
+struct be_cmd_req_get_fw_version {
+ struct be_cmd_req_hdr hdr;
+ u8 rsvd0[FW_VER_LEN];
+ u8 rsvd1[FW_VER_LEN];
+} __packed;
+
+struct be_cmd_resp_get_fw_version {
+ struct be_cmd_resp_hdr hdr;
+ u8 firmware_version_string[FW_VER_LEN];
+ u8 fw_on_flash_version_string[FW_VER_LEN];
+} __packed;
+
+/******************** Set Flow Contrl *******************/
+struct be_cmd_req_set_flow_control {
+ struct be_cmd_req_hdr hdr;
+ u16 tx_flow_control;
+ u16 rx_flow_control;
+} __packed;
+
+/******************** Get Flow Contrl *******************/
+struct be_cmd_req_get_flow_control {
+ struct be_cmd_req_hdr hdr;
+ u32 rsvd;
+};
+
+struct be_cmd_resp_get_flow_control {
+ struct be_cmd_resp_hdr hdr;
+ u16 tx_flow_control;
+ u16 rx_flow_control;
+} __packed;
+
+/******************** Modify EQ Delay *******************/
+struct be_cmd_req_modify_eq_delay {
+ struct be_cmd_req_hdr hdr;
+ u32 num_eq;
+ struct {
+ u32 eq_id;
+ u32 phase;
+ u32 delay_multiplier;
+ } delay[8];
+} __packed;
+
+struct be_cmd_resp_modify_eq_delay {
+ struct be_cmd_resp_hdr hdr;
+ u32 rsvd0;
+} __packed;
+
+/******************** Get FW Config *******************/
+struct be_cmd_req_query_fw_cfg {
+ struct be_cmd_req_hdr hdr;
+ u32 rsvd[30];
+};
+
+struct be_cmd_resp_query_fw_cfg {
+ struct be_cmd_resp_hdr hdr;
+ u32 be_config_number;
+ u32 asic_revision;
+ u32 phys_port;
+ u32 function_mode;
+ u32 rsvd[26];
+};
+
+extern int be_pci_fnum_get(struct be_ctrl_info *ctrl);
+extern int be_cmd_POST(struct be_ctrl_info *ctrl);
+extern int be_cmd_mac_addr_query(struct be_ctrl_info *ctrl, u8 *mac_addr,
+ u8 type, bool permanent, u32 if_handle);
+extern int be_cmd_pmac_add(struct be_ctrl_info *ctrl, u8 *mac_addr,
+ u32 if_id, u32 *pmac_id);
+extern int be_cmd_pmac_del(struct be_ctrl_info *ctrl, u32 if_id, u32 pmac_id);
+extern int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 if_flags, u8 *mac,
+ bool pmac_invalid, u32 *if_handle, u32 *pmac_id);
+extern int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 if_handle);
+extern int be_cmd_eq_create(struct be_ctrl_info *ctrl,
+ struct be_queue_info *eq, int eq_delay);
+extern int be_cmd_cq_create(struct be_ctrl_info *ctrl,
+ struct be_queue_info *cq, struct be_queue_info *eq,
+ bool sol_evts, bool no_delay,
+ int num_cqe_dma_coalesce);
+extern int be_cmd_txq_create(struct be_ctrl_info *ctrl,
+ struct be_queue_info *txq,
+ struct be_queue_info *cq);
+extern int be_cmd_rxq_create(struct be_ctrl_info *ctrl,
+ struct be_queue_info *rxq, u16 cq_id,
+ u16 frag_size, u16 max_frame_size, u32 if_id,
+ u32 rss);
+extern int be_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
+ int type);
+extern int be_cmd_link_status_query(struct be_ctrl_info *ctrl,
+ struct be_link_info *link);
+extern int be_cmd_reset(struct be_ctrl_info *ctrl);
+extern int be_cmd_get_stats(struct be_ctrl_info *ctrl,
+ struct be_dma_mem *nonemb_cmd);
+extern int be_cmd_get_fw_ver(struct be_ctrl_info *ctrl, char *fw_ver);
+
+extern int be_cmd_modify_eqd(struct be_ctrl_info *ctrl, u32 eq_id, u32 eqd);
+extern int be_cmd_vlan_config(struct be_ctrl_info *ctrl, u32 if_id,
+ u16 *vtag_array, u32 num, bool untagged,
+ bool promiscuous);
+extern int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl,
+ u8 port_num, bool en);
+extern int be_cmd_mcast_mac_set(struct be_ctrl_info *ctrl, u32 if_id,
+ u8 *mac_table, u32 num, bool promiscuous);
+extern int be_cmd_set_flow_control(struct be_ctrl_info *ctrl,
+ u32 tx_fc, u32 rx_fc);
+extern int be_cmd_get_flow_control(struct be_ctrl_info *ctrl,
+ u32 *tx_fc, u32 *rx_fc);
+extern int be_cmd_query_fw_cfg(struct be_ctrl_info *ctrl, u32 *port_num);
diff --git a/drivers/net/benet/be_ethtool.c b/drivers/net/benet/be_ethtool.c
new file mode 100644
index 00000000000..04f4b73fa8d
--- /dev/null
+++ b/drivers/net/benet/be_ethtool.c
@@ -0,0 +1,362 @@
+/*
+ * Copyright (C) 2005 - 2009 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation. The full GNU General
+ * Public License is included in this distribution in the file called COPYING.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+
+#include "be.h"
+#include <linux/ethtool.h>
+
+struct be_ethtool_stat {
+ char desc[ETH_GSTRING_LEN];
+ int type;
+ int size;
+ int offset;
+};
+
+enum {NETSTAT, PORTSTAT, MISCSTAT, DRVSTAT, ERXSTAT};
+#define FIELDINFO(_struct, field) FIELD_SIZEOF(_struct, field), \
+ offsetof(_struct, field)
+#define NETSTAT_INFO(field) #field, NETSTAT,\
+ FIELDINFO(struct net_device_stats,\
+ field)
+#define DRVSTAT_INFO(field) #field, DRVSTAT,\
+ FIELDINFO(struct be_drvr_stats, field)
+#define MISCSTAT_INFO(field) #field, MISCSTAT,\
+ FIELDINFO(struct be_rxf_stats, field)
+#define PORTSTAT_INFO(field) #field, PORTSTAT,\
+ FIELDINFO(struct be_port_rxf_stats, \
+ field)
+#define ERXSTAT_INFO(field) #field, ERXSTAT,\
+ FIELDINFO(struct be_erx_stats, field)
+
+static const struct be_ethtool_stat et_stats[] = {
+ {NETSTAT_INFO(rx_packets)},
+ {NETSTAT_INFO(tx_packets)},
+ {NETSTAT_INFO(rx_bytes)},
+ {NETSTAT_INFO(tx_bytes)},
+ {NETSTAT_INFO(rx_errors)},
+ {NETSTAT_INFO(tx_errors)},
+ {NETSTAT_INFO(rx_dropped)},
+ {NETSTAT_INFO(tx_dropped)},
+ {DRVSTAT_INFO(be_tx_reqs)},
+ {DRVSTAT_INFO(be_tx_stops)},
+ {DRVSTAT_INFO(be_fwd_reqs)},
+ {DRVSTAT_INFO(be_tx_wrbs)},
+ {DRVSTAT_INFO(be_polls)},
+ {DRVSTAT_INFO(be_tx_events)},
+ {DRVSTAT_INFO(be_rx_events)},
+ {DRVSTAT_INFO(be_tx_compl)},
+ {DRVSTAT_INFO(be_rx_compl)},
+ {DRVSTAT_INFO(be_ethrx_post_fail)},
+ {DRVSTAT_INFO(be_802_3_dropped_frames)},
+ {DRVSTAT_INFO(be_802_3_malformed_frames)},
+ {DRVSTAT_INFO(be_tx_rate)},
+ {DRVSTAT_INFO(be_rx_rate)},
+ {PORTSTAT_INFO(rx_unicast_frames)},
+ {PORTSTAT_INFO(rx_multicast_frames)},
+ {PORTSTAT_INFO(rx_broadcast_frames)},
+ {PORTSTAT_INFO(rx_crc_errors)},
+ {PORTSTAT_INFO(rx_alignment_symbol_errors)},
+ {PORTSTAT_INFO(rx_pause_frames)},
+ {PORTSTAT_INFO(rx_control_frames)},
+ {PORTSTAT_INFO(rx_in_range_errors)},
+ {PORTSTAT_INFO(rx_out_range_errors)},
+ {PORTSTAT_INFO(rx_frame_too_long)},
+ {PORTSTAT_INFO(rx_address_match_errors)},
+ {PORTSTAT_INFO(rx_vlan_mismatch)},
+ {PORTSTAT_INFO(rx_dropped_too_small)},
+ {PORTSTAT_INFO(rx_dropped_too_short)},
+ {PORTSTAT_INFO(rx_dropped_header_too_small)},
+ {PORTSTAT_INFO(rx_dropped_tcp_length)},
+ {PORTSTAT_INFO(rx_dropped_runt)},
+ {PORTSTAT_INFO(rx_fifo_overflow)},
+ {PORTSTAT_INFO(rx_input_fifo_overflow)},
+ {PORTSTAT_INFO(rx_ip_checksum_errs)},
+ {PORTSTAT_INFO(rx_tcp_checksum_errs)},
+ {PORTSTAT_INFO(rx_udp_checksum_errs)},
+ {PORTSTAT_INFO(rx_non_rss_packets)},
+ {PORTSTAT_INFO(rx_ipv4_packets)},
+ {PORTSTAT_INFO(rx_ipv6_packets)},
+ {PORTSTAT_INFO(tx_unicastframes)},
+ {PORTSTAT_INFO(tx_multicastframes)},
+ {PORTSTAT_INFO(tx_broadcastframes)},
+ {PORTSTAT_INFO(tx_pauseframes)},
+ {PORTSTAT_INFO(tx_controlframes)},
+ {MISCSTAT_INFO(rx_drops_no_pbuf)},
+ {MISCSTAT_INFO(rx_drops_no_txpb)},
+ {MISCSTAT_INFO(rx_drops_no_erx_descr)},
+ {MISCSTAT_INFO(rx_drops_no_tpre_descr)},
+ {MISCSTAT_INFO(rx_drops_too_many_frags)},
+ {MISCSTAT_INFO(rx_drops_invalid_ring)},
+ {MISCSTAT_INFO(forwarded_packets)},
+ {MISCSTAT_INFO(rx_drops_mtu)},
+ {ERXSTAT_INFO(rx_drops_no_fragments)},
+};
+#define ETHTOOL_STATS_NUM ARRAY_SIZE(et_stats)
+
+static void
+be_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+
+ strcpy(drvinfo->driver, DRV_NAME);
+ strcpy(drvinfo->version, DRV_VER);
+ strncpy(drvinfo->fw_version, adapter->fw_ver, FW_VER_LEN);
+ strcpy(drvinfo->bus_info, pci_name(adapter->pdev));
+ drvinfo->testinfo_len = 0;
+ drvinfo->regdump_len = 0;
+ drvinfo->eedump_len = 0;
+}
+
+static int
+be_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+ struct be_eq_obj *rx_eq = &adapter->rx_eq;
+ struct be_eq_obj *tx_eq = &adapter->tx_eq;
+
+ coalesce->rx_max_coalesced_frames = adapter->max_rx_coal;
+
+ coalesce->rx_coalesce_usecs = rx_eq->cur_eqd;
+ coalesce->rx_coalesce_usecs_high = rx_eq->max_eqd;
+ coalesce->rx_coalesce_usecs_low = rx_eq->min_eqd;
+
+ coalesce->tx_coalesce_usecs = tx_eq->cur_eqd;
+ coalesce->tx_coalesce_usecs_high = tx_eq->max_eqd;
+ coalesce->tx_coalesce_usecs_low = tx_eq->min_eqd;
+
+ coalesce->use_adaptive_rx_coalesce = rx_eq->enable_aic;
+ coalesce->use_adaptive_tx_coalesce = tx_eq->enable_aic;
+
+ return 0;
+}
+
+/*
+ * This routine is used to set interrup coalescing delay *as well as*
+ * the number of pkts to coalesce for LRO.
+ */
+static int
+be_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+ struct be_ctrl_info *ctrl = &adapter->ctrl;
+ struct be_eq_obj *rx_eq = &adapter->rx_eq;
+ struct be_eq_obj *tx_eq = &adapter->tx_eq;
+ u32 tx_max, tx_min, tx_cur;
+ u32 rx_max, rx_min, rx_cur;
+ int status = 0;
+
+ if (coalesce->use_adaptive_tx_coalesce == 1)
+ return -EINVAL;
+
+ adapter->max_rx_coal = coalesce->rx_max_coalesced_frames;
+ if (adapter->max_rx_coal > MAX_SKB_FRAGS)
+ adapter->max_rx_coal = MAX_SKB_FRAGS - 1;
+
+ /* if AIC is being turned on now, start with an EQD of 0 */
+ if (rx_eq->enable_aic == 0 &&
+ coalesce->use_adaptive_rx_coalesce == 1) {
+ rx_eq->cur_eqd = 0;
+ }
+ rx_eq->enable_aic = coalesce->use_adaptive_rx_coalesce;
+
+ rx_max = coalesce->rx_coalesce_usecs_high;
+ rx_min = coalesce->rx_coalesce_usecs_low;
+ rx_cur = coalesce->rx_coalesce_usecs;
+
+ tx_max = coalesce->tx_coalesce_usecs_high;
+ tx_min = coalesce->tx_coalesce_usecs_low;
+ tx_cur = coalesce->tx_coalesce_usecs;
+
+ if (tx_cur > BE_MAX_EQD)
+ tx_cur = BE_MAX_EQD;
+ if (tx_eq->cur_eqd != tx_cur) {
+ status = be_cmd_modify_eqd(ctrl, tx_eq->q.id, tx_cur);
+ if (!status)
+ tx_eq->cur_eqd = tx_cur;
+ }
+
+ if (rx_eq->enable_aic) {
+ if (rx_max > BE_MAX_EQD)
+ rx_max = BE_MAX_EQD;
+ if (rx_min > rx_max)
+ rx_min = rx_max;
+ rx_eq->max_eqd = rx_max;
+ rx_eq->min_eqd = rx_min;
+ if (rx_eq->cur_eqd > rx_max)
+ rx_eq->cur_eqd = rx_max;
+ if (rx_eq->cur_eqd < rx_min)
+ rx_eq->cur_eqd = rx_min;
+ } else {
+ if (rx_cur > BE_MAX_EQD)
+ rx_cur = BE_MAX_EQD;
+ if (rx_eq->cur_eqd != rx_cur) {
+ status = be_cmd_modify_eqd(ctrl, rx_eq->q.id, rx_cur);
+ if (!status)
+ rx_eq->cur_eqd = rx_cur;
+ }
+ }
+ return 0;
+}
+
+static u32 be_get_rx_csum(struct net_device *netdev)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+
+ return adapter->rx_csum;
+}
+
+static int be_set_rx_csum(struct net_device *netdev, uint32_t data)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+
+ if (data)
+ adapter->rx_csum = true;
+ else
+ adapter->rx_csum = false;
+
+ return 0;
+}
+
+static void
+be_get_ethtool_stats(struct net_device *netdev,
+ struct ethtool_stats *stats, uint64_t *data)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+ struct be_drvr_stats *drvr_stats = &adapter->stats.drvr_stats;
+ struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
+ struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
+ struct be_port_rxf_stats *port_stats =
+ &rxf_stats->port[adapter->port_num];
+ struct net_device_stats *net_stats = &adapter->stats.net_stats;
+ struct be_erx_stats *erx_stats = &hw_stats->erx;
+ void *p = NULL;
+ int i;
+
+ for (i = 0; i < ETHTOOL_STATS_NUM; i++) {
+ switch (et_stats[i].type) {
+ case NETSTAT:
+ p = net_stats;
+ break;
+ case DRVSTAT:
+ p = drvr_stats;
+ break;
+ case PORTSTAT:
+ p = port_stats;
+ break;
+ case MISCSTAT:
+ p = rxf_stats;
+ break;
+ case ERXSTAT: /* Currently only one ERX stat is provided */
+ p = (u32 *)erx_stats + adapter->rx_obj.q.id;
+ break;
+ }
+
+ p = (u8 *)p + et_stats[i].offset;
+ data[i] = (et_stats[i].size == sizeof(u64)) ?
+ *(u64 *)p: *(u32 *)p;
+ }
+
+ return;
+}
+
+static void
+be_get_stat_strings(struct net_device *netdev, uint32_t stringset,
+ uint8_t *data)
+{
+ int i;
+ switch (stringset) {
+ case ETH_SS_STATS:
+ for (i = 0; i < ETHTOOL_STATS_NUM; i++) {
+ memcpy(data, et_stats[i].desc, ETH_GSTRING_LEN);
+ data += ETH_GSTRING_LEN;
+ }
+ break;
+ }
+}
+
+static int be_get_stats_count(struct net_device *netdev)
+{
+ return ETHTOOL_STATS_NUM;
+}
+
+static int be_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
+{
+ ecmd->speed = SPEED_10000;
+ ecmd->duplex = DUPLEX_FULL;
+ ecmd->autoneg = AUTONEG_DISABLE;
+ return 0;
+}
+
+static void
+be_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+
+ ring->rx_max_pending = adapter->rx_obj.q.len;
+ ring->tx_max_pending = adapter->tx_obj.q.len;
+
+ ring->rx_pending = atomic_read(&adapter->rx_obj.q.used);
+ ring->tx_pending = atomic_read(&adapter->tx_obj.q.used);
+}
+
+static void
+be_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *ecmd)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+
+ be_cmd_get_flow_control(&adapter->ctrl, &ecmd->tx_pause,
+ &ecmd->rx_pause);
+ ecmd->autoneg = AUTONEG_ENABLE;
+}
+
+static int
+be_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *ecmd)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+ int status;
+
+ if (ecmd->autoneg != AUTONEG_ENABLE)
+ return -EINVAL;
+
+ status = be_cmd_set_flow_control(&adapter->ctrl, ecmd->tx_pause,
+ ecmd->rx_pause);
+ if (!status)
+ dev_warn(&adapter->pdev->dev, "Pause param set failed.\n");
+
+ return status;
+}
+
+struct ethtool_ops be_ethtool_ops = {
+ .get_settings = be_get_settings,
+ .get_drvinfo = be_get_drvinfo,
+ .get_link = ethtool_op_get_link,
+ .get_coalesce = be_get_coalesce,
+ .set_coalesce = be_set_coalesce,
+ .get_ringparam = be_get_ringparam,
+ .get_pauseparam = be_get_pauseparam,
+ .set_pauseparam = be_set_pauseparam,
+ .get_rx_csum = be_get_rx_csum,
+ .set_rx_csum = be_set_rx_csum,
+ .get_tx_csum = ethtool_op_get_tx_csum,
+ .set_tx_csum = ethtool_op_set_tx_csum,
+ .get_sg = ethtool_op_get_sg,
+ .set_sg = ethtool_op_set_sg,
+ .get_tso = ethtool_op_get_tso,
+ .set_tso = ethtool_op_set_tso,
+ .get_strings = be_get_stat_strings,
+ .get_stats_count = be_get_stats_count,
+ .get_ethtool_stats = be_get_ethtool_stats,
+};
diff --git a/drivers/net/benet/be_hw.h b/drivers/net/benet/be_hw.h
new file mode 100644
index 00000000000..b132aa4893c
--- /dev/null
+++ b/drivers/net/benet/be_hw.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2005 - 2009 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation. The full GNU General
+ * Public License is included in this distribution in the file called COPYING.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+
+/********* Mailbox door bell *************/
+/* Used for driver communication with the FW.
+ * The software must write this register twice to post any command. First,
+ * it writes the register with hi=1 and the upper bits of the physical address
+ * for the MAILBOX structure. Software must poll the ready bit until this
+ * is acknowledged. Then, sotware writes the register with hi=0 with the lower
+ * bits in the address. It must poll the ready bit until the command is
+ * complete. Upon completion, the MAILBOX will contain a valid completion
+ * queue entry.
+ */
+#define MPU_MAILBOX_DB_OFFSET 0x160
+#define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
+#define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
+
+#define MPU_EP_CONTROL 0
+
+/********** MPU semphore ******************/
+#define MPU_EP_SEMAPHORE_OFFSET 0xac
+#define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
+#define EP_SEMAPHORE_POST_ERR_MASK 0x1
+#define EP_SEMAPHORE_POST_ERR_SHIFT 31
+/* MPU semphore POST stage values */
+#define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
+#define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
+#define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
+#define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
+
+/********* Memory BAR register ************/
+#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
+/* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
+ * Disable" may still globally block interrupts in addition to individual
+ * interrupt masks; a mechanism for the device driver to block all interrupts
+ * atomically without having to arbitrate for the PCI Interrupt Disable bit
+ * with the OS.
+ */
+#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
+/* PCI physical function number */
+#define MEMBAR_CTRL_INT_CTRL_PFUNC_MASK 0x7 /* bits 26 - 28 */
+#define MEMBAR_CTRL_INT_CTRL_PFUNC_SHIFT 26
+
+/********* Event Q door bell *************/
+#define DB_EQ_OFFSET DB_CQ_OFFSET
+#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
+/* Clear the interrupt for this eq */
+#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
+/* Must be 1 */
+#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
+/* Number of event entries processed */
+#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
+/* Rearm bit */
+#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
+
+/********* Compl Q door bell *************/
+#define DB_CQ_OFFSET 0x120
+#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
+/* Number of event entries processed */
+#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
+/* Rearm bit */
+#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
+
+/********** TX ULP door bell *************/
+#define DB_TXULP1_OFFSET 0x60
+#define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
+/* Number of tx entries posted */
+#define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
+#define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
+
+/********** RQ(erx) door bell ************/
+#define DB_RQ_OFFSET 0x100
+#define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
+/* Number of rx frags posted */
+#define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
+
+/*
+ * BE descriptors: host memory data structures whose formats
+ * are hardwired in BE silicon.
+ */
+/* Event Queue Descriptor */
+#define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
+#define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
+#define EQ_ENTRY_RES_ID_SHIFT 16
+struct be_eq_entry {
+ u32 evt;
+};
+
+/* TX Queue Descriptor */
+#define ETH_WRB_FRAG_LEN_MASK 0xFFFF
+struct be_eth_wrb {
+ u32 frag_pa_hi; /* dword 0 */
+ u32 frag_pa_lo; /* dword 1 */
+ u32 rsvd0; /* dword 2 */
+ u32 frag_len; /* dword 3: bits 0 - 15 */
+} __packed;
+
+/* Pseudo amap definition for eth_hdr_wrb in which each bit of the
+ * actual structure is defined as a byte : used to calculate
+ * offset/shift/mask of each field */
+struct amap_eth_hdr_wrb {
+ u8 rsvd0[32]; /* dword 0 */
+ u8 rsvd1[32]; /* dword 1 */
+ u8 complete; /* dword 2 */
+ u8 event;
+ u8 crc;
+ u8 forward;
+ u8 ipsec;
+ u8 mgmt;
+ u8 ipcs;
+ u8 udpcs;
+ u8 tcpcs;
+ u8 lso;
+ u8 vlan;
+ u8 gso[2];
+ u8 num_wrb[5];
+ u8 lso_mss[14];
+ u8 len[16]; /* dword 3 */
+ u8 vlan_tag[16];
+} __packed;
+
+struct be_eth_hdr_wrb {
+ u32 dw[4];
+};
+
+/* TX Compl Queue Descriptor */
+
+/* Pseudo amap definition for eth_tx_compl in which each bit of the
+ * actual structure is defined as a byte: used to calculate
+ * offset/shift/mask of each field */
+struct amap_eth_tx_compl {
+ u8 wrb_index[16]; /* dword 0 */
+ u8 ct[2]; /* dword 0 */
+ u8 port[2]; /* dword 0 */
+ u8 rsvd0[8]; /* dword 0 */
+ u8 status[4]; /* dword 0 */
+ u8 user_bytes[16]; /* dword 1 */
+ u8 nwh_bytes[8]; /* dword 1 */
+ u8 lso; /* dword 1 */
+ u8 cast_enc[2]; /* dword 1 */
+ u8 rsvd1[5]; /* dword 1 */
+ u8 rsvd2[32]; /* dword 2 */
+ u8 pkts[16]; /* dword 3 */
+ u8 ringid[11]; /* dword 3 */
+ u8 hash_val[4]; /* dword 3 */
+ u8 valid; /* dword 3 */
+} __packed;
+
+struct be_eth_tx_compl {
+ u32 dw[4];
+};
+
+/* RX Queue Descriptor */
+struct be_eth_rx_d {
+ u32 fragpa_hi;
+ u32 fragpa_lo;
+};
+
+/* RX Compl Queue Descriptor */
+
+/* Pseudo amap definition for eth_rx_compl in which each bit of the
+ * actual structure is defined as a byte: used to calculate
+ * offset/shift/mask of each field */
+struct amap_eth_rx_compl {
+ u8 vlan_tag[16]; /* dword 0 */
+ u8 pktsize[14]; /* dword 0 */
+ u8 port; /* dword 0 */
+ u8 ip_opt; /* dword 0 */
+ u8 err; /* dword 1 */
+ u8 rsshp; /* dword 1 */
+ u8 ipf; /* dword 1 */
+ u8 tcpf; /* dword 1 */
+ u8 udpf; /* dword 1 */
+ u8 ipcksm; /* dword 1 */
+ u8 l4_cksm; /* dword 1 */
+ u8 ip_version; /* dword 1 */
+ u8 macdst[6]; /* dword 1 */
+ u8 vtp; /* dword 1 */
+ u8 rsvd0; /* dword 1 */
+ u8 fragndx[10]; /* dword 1 */
+ u8 ct[2]; /* dword 1 */
+ u8 sw; /* dword 1 */
+ u8 numfrags[3]; /* dword 1 */
+ u8 rss_flush; /* dword 2 */
+ u8 cast_enc[2]; /* dword 2 */
+ u8 qnq; /* dword 2 */
+ u8 rss_bank; /* dword 2 */
+ u8 rsvd1[23]; /* dword 2 */
+ u8 lro_pkt; /* dword 2 */
+ u8 rsvd2[2]; /* dword 2 */
+ u8 valid; /* dword 2 */
+ u8 rsshash[32]; /* dword 3 */
+} __packed;
+
+struct be_eth_rx_compl {
+ u32 dw[4];
+};
diff --git a/drivers/net/benet/be_main.c b/drivers/net/benet/be_main.c
new file mode 100644
index 00000000000..897a63de5bd
--- /dev/null
+++ b/drivers/net/benet/be_main.c
@@ -0,0 +1,1903 @@
+/*
+ * Copyright (C) 2005 - 2009 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation. The full GNU General
+ * Public License is included in this distribution in the file called COPYING.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+
+#include "be.h"
+
+MODULE_VERSION(DRV_VER);
+MODULE_DEVICE_TABLE(pci, be_dev_ids);
+MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
+MODULE_AUTHOR("ServerEngines Corporation");
+MODULE_LICENSE("GPL");
+
+static unsigned int rx_frag_size = 2048;
+module_param(rx_frag_size, uint, S_IRUGO);
+MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
+
+#define BE_VENDOR_ID 0x19a2
+#define BE2_DEVICE_ID_1 0x0211
+static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
+ { PCI_DEVICE(BE_VENDOR_ID, BE2_DEVICE_ID_1) },
+ { 0 }
+};
+MODULE_DEVICE_TABLE(pci, be_dev_ids);
+
+static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
+{
+ struct be_dma_mem *mem = &q->dma_mem;
+ if (mem->va)
+ pci_free_consistent(adapter->pdev, mem->size,
+ mem->va, mem->dma);
+}
+
+static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
+ u16 len, u16 entry_size)
+{
+ struct be_dma_mem *mem = &q->dma_mem;
+
+ memset(q, 0, sizeof(*q));
+ q->len = len;
+ q->entry_size = entry_size;
+ mem->size = len * entry_size;
+ mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
+ if (!mem->va)
+ return -1;
+ memset(mem->va, 0, mem->size);
+ return 0;
+}
+
+static inline void *queue_head_node(struct be_queue_info *q)
+{
+ return q->dma_mem.va + q->head * q->entry_size;
+}
+
+static inline void *queue_tail_node(struct be_queue_info *q)
+{
+ return q->dma_mem.va + q->tail * q->entry_size;
+}
+
+static inline void queue_head_inc(struct be_queue_info *q)
+{
+ index_inc(&q->head, q->len);
+}
+
+static inline void queue_tail_inc(struct be_queue_info *q)
+{
+ index_inc(&q->tail, q->len);
+}
+
+static void be_intr_set(struct be_ctrl_info *ctrl, bool enable)
+{
+ u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
+ u32 reg = ioread32(addr);
+ u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
+ if (!enabled && enable) {
+ reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
+ } else if (enabled && !enable) {
+ reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
+ } else {
+ printk(KERN_WARNING DRV_NAME
+ ": bad value in membar_int_ctrl reg=0x%x\n", reg);
+ return;
+ }
+ iowrite32(reg, addr);
+}
+
+static void be_rxq_notify(struct be_ctrl_info *ctrl, u16 qid, u16 posted)
+{
+ u32 val = 0;
+ val |= qid & DB_RQ_RING_ID_MASK;
+ val |= posted << DB_RQ_NUM_POSTED_SHIFT;
+ iowrite32(val, ctrl->db + DB_RQ_OFFSET);
+}
+
+static void be_txq_notify(struct be_ctrl_info *ctrl, u16 qid, u16 posted)
+{
+ u32 val = 0;
+ val |= qid & DB_TXULP_RING_ID_MASK;
+ val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
+ iowrite32(val, ctrl->db + DB_TXULP1_OFFSET);
+}
+
+static void be_eq_notify(struct be_ctrl_info *ctrl, u16 qid,
+ bool arm, bool clear_int, u16 num_popped)
+{
+ u32 val = 0;
+ val |= qid & DB_EQ_RING_ID_MASK;
+ if (arm)
+ val |= 1 << DB_EQ_REARM_SHIFT;
+ if (clear_int)
+ val |= 1 << DB_EQ_CLR_SHIFT;
+ val |= 1 << DB_EQ_EVNT_SHIFT;
+ val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
+ iowrite32(val, ctrl->db + DB_EQ_OFFSET);
+}
+
+static void be_cq_notify(struct be_ctrl_info *ctrl, u16 qid,
+ bool arm, u16 num_popped)
+{
+ u32 val = 0;
+ val |= qid & DB_CQ_RING_ID_MASK;
+ if (arm)
+ val |= 1 << DB_CQ_REARM_SHIFT;
+ val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
+ iowrite32(val, ctrl->db + DB_CQ_OFFSET);
+}
+
+
+static int be_mac_addr_set(struct net_device *netdev, void *p)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+ struct sockaddr *addr = p;
+ int status = 0;
+
+ if (netif_running(netdev)) {
+ status = be_cmd_pmac_del(&adapter->ctrl, adapter->if_handle,
+ adapter->pmac_id);
+ if (status)
+ return status;
+
+ status = be_cmd_pmac_add(&adapter->ctrl, (u8 *)addr->sa_data,
+ adapter->if_handle, &adapter->pmac_id);
+ }
+
+ if (!status)
+ memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
+
+ return status;
+}
+
+static void netdev_stats_update(struct be_adapter *adapter)
+{
+ struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
+ struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
+ struct be_port_rxf_stats *port_stats =
+ &rxf_stats->port[adapter->port_num];
+ struct net_device_stats *dev_stats = &adapter->stats.net_stats;
+
+ dev_stats->rx_packets = port_stats->rx_total_frames;
+ dev_stats->tx_packets = port_stats->tx_unicastframes +
+ port_stats->tx_multicastframes + port_stats->tx_broadcastframes;
+ dev_stats->rx_bytes = (u64) port_stats->rx_bytes_msd << 32 |
+ (u64) port_stats->rx_bytes_lsd;
+ dev_stats->tx_bytes = (u64) port_stats->tx_bytes_msd << 32 |
+ (u64) port_stats->tx_bytes_lsd;
+
+ /* bad pkts received */
+ dev_stats->rx_errors = port_stats->rx_crc_errors +
+ port_stats->rx_alignment_symbol_errors +
+ port_stats->rx_in_range_errors +
+ port_stats->rx_out_range_errors + port_stats->rx_frame_too_long;
+
+ /* packet transmit problems */
+ dev_stats->tx_errors = 0;
+
+ /* no space in linux buffers */
+ dev_stats->rx_dropped = 0;
+
+ /* no space available in linux */
+ dev_stats->tx_dropped = 0;
+
+ dev_stats->multicast = port_stats->tx_multicastframes;
+ dev_stats->collisions = 0;
+
+ /* detailed rx errors */
+ dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
+ port_stats->rx_out_range_errors + port_stats->rx_frame_too_long;
+ /* receive ring buffer overflow */
+ dev_stats->rx_over_errors = 0;
+ dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
+
+ /* frame alignment errors */
+ dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
+ /* receiver fifo overrun */
+ /* drops_no_pbuf is no per i/f, it's per BE card */
+ dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
+ port_stats->rx_input_fifo_overflow +
+ rxf_stats->rx_drops_no_pbuf;
+ /* receiver missed packetd */
+ dev_stats->rx_missed_errors = 0;
+ /* detailed tx_errors */
+ dev_stats->tx_aborted_errors = 0;
+ dev_stats->tx_carrier_errors = 0;
+ dev_stats->tx_fifo_errors = 0;
+ dev_stats->tx_heartbeat_errors = 0;
+ dev_stats->tx_window_errors = 0;
+}
+
+static void be_link_status_update(struct be_adapter *adapter)
+{
+ struct be_link_info *prev = &adapter->link;
+ struct be_link_info now = { 0 };
+ struct net_device *netdev = adapter->netdev;
+
+ be_cmd_link_status_query(&adapter->ctrl, &now);
+
+ /* If link came up or went down */
+ if (now.speed != prev->speed && (now.speed == PHY_LINK_SPEED_ZERO ||
+ prev->speed == PHY_LINK_SPEED_ZERO)) {
+ if (now.speed == PHY_LINK_SPEED_ZERO) {
+ netif_stop_queue(netdev);
+ netif_carrier_off(netdev);
+ printk(KERN_INFO "%s: Link down\n", netdev->name);
+ } else {
+ netif_start_queue(netdev);
+ netif_carrier_on(netdev);
+ printk(KERN_INFO "%s: Link up\n", netdev->name);
+ }
+ }
+ *prev = now;
+}
+
+/* Update the EQ delay n BE based on the RX frags consumed / sec */
+static void be_rx_eqd_update(struct be_adapter *adapter)
+{
+ u32 eqd;
+ struct be_ctrl_info *ctrl = &adapter->ctrl;
+ struct be_eq_obj *rx_eq = &adapter->rx_eq;
+ struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
+
+ /* Update once a second */
+ if (((jiffies - stats->rx_fps_jiffies) < HZ) || rx_eq->enable_aic == 0)
+ return;
+
+ stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
+ ((jiffies - stats->rx_fps_jiffies) / HZ);
+
+ stats->rx_fps_jiffies = jiffies;
+ stats->be_prev_rx_frags = stats->be_rx_frags;
+ eqd = stats->be_rx_fps / 110000;
+ eqd = eqd << 3;
+ if (eqd > rx_eq->max_eqd)
+ eqd = rx_eq->max_eqd;
+ if (eqd < rx_eq->min_eqd)
+ eqd = rx_eq->min_eqd;
+ if (eqd < 10)
+ eqd = 0;
+ if (eqd != rx_eq->cur_eqd)
+ be_cmd_modify_eqd(ctrl, rx_eq->q.id, eqd);
+
+ rx_eq->cur_eqd = eqd;
+}
+
+static void be_worker(struct work_struct *work)
+{
+ struct be_adapter *adapter =
+ container_of(work, struct be_adapter, work.work);
+ int status;
+
+ /* Check link */
+ be_link_status_update(adapter);
+
+ /* Get Stats */
+ status = be_cmd_get_stats(&adapter->ctrl, &adapter->stats.cmd);
+ if (!status)
+ netdev_stats_update(adapter);
+
+ /* Set EQ delay */
+ be_rx_eqd_update(adapter);
+
+ schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
+}
+
+static struct net_device_stats *be_get_stats(struct net_device *dev)
+{
+ struct be_adapter *adapter = netdev_priv(dev);
+
+ return &adapter->stats.net_stats;
+}
+
+static void be_tx_stats_update(struct be_adapter *adapter,
+ u32 wrb_cnt, u32 copied, bool stopped)
+{
+ struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
+ stats->be_tx_reqs++;
+ stats->be_tx_wrbs += wrb_cnt;
+ stats->be_tx_bytes += copied;
+ if (stopped)
+ stats->be_tx_stops++;
+
+ /* Update tx rate once in two seconds */
+ if ((jiffies - stats->be_tx_jiffies) > 2 * HZ) {
+ u32 r;
+ r = (stats->be_tx_bytes - stats->be_tx_bytes_prev) /
+ ((u32) (jiffies - stats->be_tx_jiffies) / HZ);
+ r = (r / 1000000); /* M bytes/s */
+ stats->be_tx_rate = (r * 8); /* M bits/s */
+ stats->be_tx_jiffies = jiffies;
+ stats->be_tx_bytes_prev = stats->be_tx_bytes;
+ }
+}
+
+/* Determine number of WRB entries needed to xmit data in an skb */
+static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
+{
+ int cnt = 0;
+ while (skb) {
+ if (skb->len > skb->data_len)
+ cnt++;
+ cnt += skb_shinfo(skb)->nr_frags;
+ skb = skb_shinfo(skb)->frag_list;
+ }
+ /* to account for hdr wrb */
+ cnt++;
+ if (cnt & 1) {
+ /* add a dummy to make it an even num */
+ cnt++;
+ *dummy = true;
+ } else
+ *dummy = false;
+ BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
+ return cnt;
+}
+
+static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
+{
+ wrb->frag_pa_hi = upper_32_bits(addr);
+ wrb->frag_pa_lo = addr & 0xFFFFFFFF;
+ wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
+}
+
+static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
+ bool vlan, u32 wrb_cnt, u32 len)
+{
+ memset(hdr, 0, sizeof(*hdr));
+
+ AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
+
+ if (skb_shinfo(skb)->gso_segs > 1 && skb_shinfo(skb)->gso_size) {
+ AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
+ AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
+ hdr, skb_shinfo(skb)->gso_size);
+ } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
+ if (is_tcp_pkt(skb))
+ AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
+ else if (is_udp_pkt(skb))
+ AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
+ }
+
+ if (vlan && vlan_tx_tag_present(skb)) {
+ AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
+ AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
+ hdr, vlan_tx_tag_get(skb));
+ }
+
+ AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
+ AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
+ AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
+ AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
+}
+
+
+static int make_tx_wrbs(struct be_adapter *adapter,
+ struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
+{
+ u64 busaddr;
+ u32 i, copied = 0;
+ struct pci_dev *pdev = adapter->pdev;
+ struct sk_buff *first_skb = skb;
+ struct be_queue_info *txq = &adapter->tx_obj.q;
+ struct be_eth_wrb *wrb;
+ struct be_eth_hdr_wrb *hdr;
+
+ atomic_add(wrb_cnt, &txq->used);
+ hdr = queue_head_node(txq);
+ queue_head_inc(txq);
+
+ while (skb) {
+ if (skb->len > skb->data_len) {
+ int len = skb->len - skb->data_len;
+ busaddr = pci_map_single(pdev, skb->data, len,
+ PCI_DMA_TODEVICE);
+ wrb = queue_head_node(txq);
+ wrb_fill(wrb, busaddr, len);
+ be_dws_cpu_to_le(wrb, sizeof(*wrb));
+ queue_head_inc(txq);
+ copied += len;
+ }
+
+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+ struct skb_frag_struct *frag =
+ &skb_shinfo(skb)->frags[i];
+ busaddr = pci_map_page(pdev, frag->page,
+ frag->page_offset,
+ frag->size, PCI_DMA_TODEVICE);
+ wrb = queue_head_node(txq);
+ wrb_fill(wrb, busaddr, frag->size);
+ be_dws_cpu_to_le(wrb, sizeof(*wrb));
+ queue_head_inc(txq);
+ copied += frag->size;
+ }
+ skb = skb_shinfo(skb)->frag_list;
+ }
+
+ if (dummy_wrb) {
+ wrb = queue_head_node(txq);
+ wrb_fill(wrb, 0, 0);
+ be_dws_cpu_to_le(wrb, sizeof(*wrb));
+ queue_head_inc(txq);
+ }
+
+ wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
+ wrb_cnt, copied);
+ be_dws_cpu_to_le(hdr, sizeof(*hdr));
+
+ return copied;
+}
+
+static int be_xmit(struct sk_buff *skb, struct net_device *netdev)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+ struct be_tx_obj *tx_obj = &adapter->tx_obj;
+ struct be_queue_info *txq = &tx_obj->q;
+ u32 wrb_cnt = 0, copied = 0;
+ u32 start = txq->head;
+ bool dummy_wrb, stopped = false;
+
+ wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
+
+ copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
+
+ /* record the sent skb in the sent_skb table */
+ BUG_ON(tx_obj->sent_skb_list[start]);
+ tx_obj->sent_skb_list[start] = skb;
+
+ /* Ensure that txq has space for the next skb; Else stop the queue
+ * *BEFORE* ringing the tx doorbell, so that we serialze the
+ * tx compls of the current transmit which'll wake up the queue
+ */
+ if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >= txq->len) {
+ netif_stop_queue(netdev);
+ stopped = true;
+ }
+
+ be_txq_notify(&adapter->ctrl, txq->id, wrb_cnt);
+
+ netdev->trans_start = jiffies;
+
+ be_tx_stats_update(adapter, wrb_cnt, copied, stopped);
+ return NETDEV_TX_OK;
+}
+
+static int be_change_mtu(struct net_device *netdev, int new_mtu)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+ if (new_mtu < BE_MIN_MTU ||
+ new_mtu > BE_MAX_JUMBO_FRAME_SIZE) {
+ dev_info(&adapter->pdev->dev,
+ "MTU must be between %d and %d bytes\n",
+ BE_MIN_MTU, BE_MAX_JUMBO_FRAME_SIZE);
+ return -EINVAL;
+ }
+ dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
+ netdev->mtu, new_mtu);
+ netdev->mtu = new_mtu;
+ return 0;
+}
+
+/*
+ * if there are BE_NUM_VLANS_SUPPORTED or lesser number of VLANS configured,
+ * program them in BE. If more than BE_NUM_VLANS_SUPPORTED are configured,
+ * set the BE in promiscuous VLAN mode.
+ */
+static void be_vids_config(struct net_device *netdev)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+ u16 vtag[BE_NUM_VLANS_SUPPORTED];
+ u16 ntags = 0, i;
+
+ if (adapter->num_vlans <= BE_NUM_VLANS_SUPPORTED) {
+ /* Construct VLAN Table to give to HW */
+ for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
+ if (adapter->vlan_tag[i]) {
+ vtag[ntags] = cpu_to_le16(i);
+ ntags++;
+ }
+ }
+ be_cmd_vlan_config(&adapter->ctrl, adapter->if_handle,
+ vtag, ntags, 1, 0);
+ } else {
+ be_cmd_vlan_config(&adapter->ctrl, adapter->if_handle,
+ NULL, 0, 1, 1);
+ }
+}
+
+static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+ struct be_eq_obj *rx_eq = &adapter->rx_eq;
+ struct be_eq_obj *tx_eq = &adapter->tx_eq;
+ struct be_ctrl_info *ctrl = &adapter->ctrl;
+
+ be_eq_notify(ctrl, rx_eq->q.id, false, false, 0);
+ be_eq_notify(ctrl, tx_eq->q.id, false, false, 0);
+ adapter->vlan_grp = grp;
+ be_eq_notify(ctrl, rx_eq->q.id, true, false, 0);
+ be_eq_notify(ctrl, tx_eq->q.id, true, false, 0);
+}
+
+static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+
+ adapter->num_vlans++;
+ adapter->vlan_tag[vid] = 1;
+
+ be_vids_config(netdev);
+}
+
+static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+
+ adapter->num_vlans--;
+ adapter->vlan_tag[vid] = 0;
+
+ vlan_group_set_device(adapter->vlan_grp, vid, NULL);
+ be_vids_config(netdev);
+}
+
+static void be_set_multicast_filter(struct net_device *netdev)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+ struct dev_mc_list *mc_ptr;
+ u8 mac_addr[32][ETH_ALEN];
+ int i = 0;
+
+ if (netdev->flags & IFF_ALLMULTI) {
+ /* set BE in Multicast promiscuous */
+ be_cmd_mcast_mac_set(&adapter->ctrl,
+ adapter->if_handle, NULL, 0, true);
+ return;
+ }
+
+ for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
+ memcpy(&mac_addr[i][0], mc_ptr->dmi_addr, ETH_ALEN);
+ if (++i >= 32) {
+ be_cmd_mcast_mac_set(&adapter->ctrl,
+ adapter->if_handle, &mac_addr[0][0], i, false);
+ i = 0;
+ }
+
+ }
+
+ if (i) {
+ /* reset the promiscuous mode also. */
+ be_cmd_mcast_mac_set(&adapter->ctrl,
+ adapter->if_handle, &mac_addr[0][0], i, false);
+ }
+}
+
+static void be_set_multicast_list(struct net_device *netdev)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+
+ if (netdev->flags & IFF_PROMISC) {
+ be_cmd_promiscuous_config(&adapter->ctrl, adapter->port_num, 1);
+ } else {
+ be_cmd_promiscuous_config(&adapter->ctrl, adapter->port_num, 0);
+ be_set_multicast_filter(netdev);
+ }
+}
+
+static void be_rx_rate_update(struct be_adapter *adapter, u32 pktsize,
+ u16 numfrags)
+{
+ struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
+ u32 rate;
+
+ stats->be_rx_compl++;
+ stats->be_rx_frags += numfrags;
+ stats->be_rx_bytes += pktsize;
+
+ /* Update the rate once in two seconds */
+ if ((jiffies - stats->be_rx_jiffies) < 2 * HZ)
+ return;
+
+ rate = (stats->be_rx_bytes - stats->be_rx_bytes_prev) /
+ ((u32) (jiffies - stats->be_rx_jiffies) / HZ);
+ rate = (rate / 1000000); /* MB/Sec */
+ stats->be_rx_rate = (rate * 8); /* Mega Bits/Sec */
+ stats->be_rx_jiffies = jiffies;
+ stats->be_rx_bytes_prev = stats->be_rx_bytes;
+}
+
+static struct be_rx_page_info *
+get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
+{
+ struct be_rx_page_info *rx_page_info;
+ struct be_queue_info *rxq = &adapter->rx_obj.q;
+
+ rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
+ BUG_ON(!rx_page_info->page);
+
+ if (rx_page_info->last_page_user)
+ pci_unmap_page(adapter->pdev, pci_unmap_addr(rx_page_info, bus),
+ adapter->big_page_size, PCI_DMA_FROMDEVICE);
+
+ atomic_dec(&rxq->used);
+ return rx_page_info;
+}
+
+/* Throwaway the data in the Rx completion */
+static void be_rx_compl_discard(struct be_adapter *adapter,
+ struct be_eth_rx_compl *rxcp)
+{
+ struct be_queue_info *rxq = &adapter->rx_obj.q;
+ struct be_rx_page_info *page_info;
+ u16 rxq_idx, i, num_rcvd;
+
+ rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
+ num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
+
+ for (i = 0; i < num_rcvd; i++) {
+ page_info = get_rx_page_info(adapter, rxq_idx);
+ put_page(page_info->page);
+ memset(page_info, 0, sizeof(*page_info));
+ index_inc(&rxq_idx, rxq->len);
+ }
+}
+
+/*
+ * skb_fill_rx_data forms a complete skb for an ether frame
+ * indicated by rxcp.
+ */
+static void skb_fill_rx_data(struct be_adapter *adapter,
+ struct sk_buff *skb, struct be_eth_rx_compl *rxcp)
+{
+ struct be_queue_info *rxq = &adapter->rx_obj.q;
+ struct be_rx_page_info *page_info;
+ u16 rxq_idx, i, num_rcvd;
+ u32 pktsize, hdr_len, curr_frag_len;
+ u8 *start;
+
+ rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
+ pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
+ num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
+
+ page_info = get_rx_page_info(adapter, rxq_idx);
+
+ start = page_address(page_info->page) + page_info->page_offset;
+ prefetch(start);
+
+ /* Copy data in the first descriptor of this completion */
+ curr_frag_len = min(pktsize, rx_frag_size);
+
+ /* Copy the header portion into skb_data */
+ hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
+ memcpy(skb->data, start, hdr_len);
+ skb->len = curr_frag_len;
+ if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
+ /* Complete packet has now been moved to data */
+ put_page(page_info->page);
+ skb->data_len = 0;
+ skb->tail += curr_frag_len;
+ } else {
+ skb_shinfo(skb)->nr_frags = 1;
+ skb_shinfo(skb)->frags[0].page = page_info->page;
+ skb_shinfo(skb)->frags[0].page_offset =
+ page_info->page_offset + hdr_len;
+ skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
+ skb->data_len = curr_frag_len - hdr_len;
+ skb->tail += hdr_len;
+ }
+ memset(page_info, 0, sizeof(*page_info));
+
+ if (pktsize <= rx_frag_size) {
+ BUG_ON(num_rcvd != 1);
+ return;
+ }
+
+ /* More frags present for this completion */
+ pktsize -= curr_frag_len; /* account for above copied frag */
+ for (i = 1; i < num_rcvd; i++) {
+ index_inc(&rxq_idx, rxq->len);
+ page_info = get_rx_page_info(adapter, rxq_idx);
+
+ curr_frag_len = min(pktsize, rx_frag_size);
+
+ skb_shinfo(skb)->frags[i].page = page_info->page;
+ skb_shinfo(skb)->frags[i].page_offset = page_info->page_offset;
+ skb_shinfo(skb)->frags[i].size = curr_frag_len;
+ skb->len += curr_frag_len;
+ skb->data_len += curr_frag_len;
+ skb_shinfo(skb)->nr_frags++;
+ pktsize -= curr_frag_len;
+
+ memset(page_info, 0, sizeof(*page_info));
+ }
+
+ be_rx_rate_update(adapter, pktsize, num_rcvd);
+ return;
+}
+
+/* Process the RX completion indicated by rxcp when LRO is disabled */
+static void be_rx_compl_process(struct be_adapter *adapter,
+ struct be_eth_rx_compl *rxcp)
+{
+ struct sk_buff *skb;
+ u32 vtp, vid;
+ int l4_cksm;
+
+ l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
+ vtp = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
+
+ skb = netdev_alloc_skb(adapter->netdev, BE_HDR_LEN + NET_IP_ALIGN);
+ if (!skb) {
+ if (net_ratelimit())
+ dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
+ be_rx_compl_discard(adapter, rxcp);
+ return;
+ }
+
+ skb_reserve(skb, NET_IP_ALIGN);
+
+ skb_fill_rx_data(adapter, skb, rxcp);
+
+ if (l4_cksm && adapter->rx_csum)
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ else
+ skb->ip_summed = CHECKSUM_NONE;
+
+ skb->truesize = skb->len + sizeof(struct sk_buff);
+ skb->protocol = eth_type_trans(skb, adapter->netdev);
+ skb->dev = adapter->netdev;
+
+ if (vtp) {
+ if (!adapter->vlan_grp || adapter->num_vlans == 0) {
+ kfree_skb(skb);
+ return;
+ }
+ vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
+ vid = be16_to_cpu(vid);
+ vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
+ } else {
+ netif_receive_skb(skb);
+ }
+
+ adapter->netdev->last_rx = jiffies;
+
+ return;
+}
+
+/* Process the RX completion indicated by rxcp when LRO is enabled */
+static void be_rx_compl_process_lro(struct be_adapter *adapter,
+ struct be_eth_rx_compl *rxcp)
+{
+ struct be_rx_page_info *page_info;
+ struct skb_frag_struct rx_frags[BE_MAX_FRAGS_PER_FRAME];
+ struct be_queue_info *rxq = &adapter->rx_obj.q;
+ u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
+ u16 i, rxq_idx = 0, vid;
+
+ num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
+ pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
+ vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
+ rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
+
+ remaining = pkt_size;
+ for (i = 0; i < num_rcvd; i++) {
+ page_info = get_rx_page_info(adapter, rxq_idx);
+
+ curr_frag_len = min(remaining, rx_frag_size);
+
+ rx_frags[i].page = page_info->page;
+ rx_frags[i].page_offset = page_info->page_offset;
+ rx_frags[i].size = curr_frag_len;
+ remaining -= curr_frag_len;
+
+ index_inc(&rxq_idx, rxq->len);
+
+ memset(page_info, 0, sizeof(*page_info));
+ }
+
+ if (likely(!vlanf)) {
+ lro_receive_frags(&adapter->rx_obj.lro_mgr, rx_frags, pkt_size,
+ pkt_size, NULL, 0);
+ } else {
+ vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
+ vid = be16_to_cpu(vid);
+
+ if (!adapter->vlan_grp || adapter->num_vlans == 0)
+ return;
+
+ lro_vlan_hwaccel_receive_frags(&adapter->rx_obj.lro_mgr,
+ rx_frags, pkt_size, pkt_size, adapter->vlan_grp,
+ vid, NULL, 0);
+ }
+
+ be_rx_rate_update(adapter, pkt_size, num_rcvd);
+ return;
+}
+
+static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
+{
+ struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
+
+ if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
+ return NULL;
+
+ be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
+
+ rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
+
+ queue_tail_inc(&adapter->rx_obj.cq);
+ return rxcp;
+}
+
+static inline struct page *be_alloc_pages(u32 size)
+{
+ gfp_t alloc_flags = GFP_ATOMIC;
+ u32 order = get_order(size);
+ if (order > 0)
+ alloc_flags |= __GFP_COMP;
+ return alloc_pages(alloc_flags, order);
+}
+
+/*
+ * Allocate a page, split it to fragments of size rx_frag_size and post as
+ * receive buffers to BE
+ */
+static void be_post_rx_frags(struct be_adapter *adapter)
+{
+ struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
+ struct be_rx_page_info *page_info = NULL;
+ struct be_queue_info *rxq = &adapter->rx_obj.q;
+ struct page *pagep = NULL;
+ struct be_eth_rx_d *rxd;
+ u64 page_dmaaddr = 0, frag_dmaaddr;
+ u32 posted, page_offset = 0;
+
+
+ page_info = &page_info_tbl[rxq->head];
+ for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
+ if (!pagep) {
+ pagep = be_alloc_pages(adapter->big_page_size);
+ if (unlikely(!pagep)) {
+ drvr_stats(adapter)->be_ethrx_post_fail++;
+ break;
+ }
+ page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
+ adapter->big_page_size,
+ PCI_DMA_FROMDEVICE);
+ page_info->page_offset = 0;
+ } else {
+ get_page(pagep);
+ page_info->page_offset = page_offset + rx_frag_size;
+ }
+ page_offset = page_info->page_offset;
+ page_info->page = pagep;
+ pci_unmap_addr_set(page_info, bus, page_dmaaddr);
+ frag_dmaaddr = page_dmaaddr + page_info->page_offset;
+
+ rxd = queue_head_node(rxq);
+ rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
+ rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
+ queue_head_inc(rxq);
+
+ /* Any space left in the current big page for another frag? */
+ if ((page_offset + rx_frag_size + rx_frag_size) >
+ adapter->big_page_size) {
+ pagep = NULL;
+ page_info->last_page_user = true;
+ }
+ page_info = &page_info_tbl[rxq->head];
+ }
+ if (pagep)
+ page_info->last_page_user = true;
+
+ if (posted) {
+ be_rxq_notify(&adapter->ctrl, rxq->id, posted);
+ atomic_add(posted, &rxq->used);
+ }
+
+ return;
+}
+
+static struct be_eth_tx_compl *
+be_tx_compl_get(struct be_adapter *adapter)
+{
+ struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
+ struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
+
+ if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
+ return NULL;
+
+ be_dws_le_to_cpu(txcp, sizeof(*txcp));
+
+ txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
+
+ queue_tail_inc(tx_cq);
+ return txcp;
+}
+
+static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
+{
+ struct be_queue_info *txq = &adapter->tx_obj.q;
+ struct be_eth_wrb *wrb;
+ struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
+ struct sk_buff *sent_skb;
+ u64 busaddr;
+ u16 cur_index, num_wrbs = 0;
+
+ cur_index = txq->tail;
+ sent_skb = sent_skbs[cur_index];
+ BUG_ON(!sent_skb);
+ sent_skbs[cur_index] = NULL;
+
+ do {
+ cur_index = txq->tail;
+ wrb = queue_tail_node(txq);
+ be_dws_le_to_cpu(wrb, sizeof(*wrb));
+ busaddr = ((u64)wrb->frag_pa_hi << 32) | (u64)wrb->frag_pa_lo;
+ if (busaddr != 0) {
+ pci_unmap_single(adapter->pdev, busaddr,
+ wrb->frag_len, PCI_DMA_TODEVICE);
+ }
+ num_wrbs++;
+ queue_tail_inc(txq);
+ } while (cur_index != last_index);
+
+ atomic_sub(num_wrbs, &txq->used);
+
+ kfree_skb(sent_skb);
+}
+
+static void be_rx_q_clean(struct be_adapter *adapter)
+{
+ struct be_rx_page_info *page_info;
+ struct be_queue_info *rxq = &adapter->rx_obj.q;
+ struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
+ struct be_eth_rx_compl *rxcp;
+ u16 tail;
+
+ /* First cleanup pending rx completions */
+ while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
+ be_rx_compl_discard(adapter, rxcp);
+ be_cq_notify(&adapter->ctrl, rx_cq->id, true, 1);
+ }
+
+ /* Then free posted rx buffer that were not used */
+ tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
+ for (; tail != rxq->head; index_inc(&tail, rxq->len)) {
+ page_info = get_rx_page_info(adapter, tail);
+ put_page(page_info->page);
+ memset(page_info, 0, sizeof(*page_info));
+ }
+ BUG_ON(atomic_read(&rxq->used));
+}
+
+static void be_tx_q_clean(struct be_adapter *adapter)
+{
+ struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
+ struct sk_buff *sent_skb;
+ struct be_queue_info *txq = &adapter->tx_obj.q;
+ u16 last_index;
+ bool dummy_wrb;
+
+ while (atomic_read(&txq->used)) {
+ sent_skb = sent_skbs[txq->tail];
+ last_index = txq->tail;
+ index_adv(&last_index,
+ wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
+ be_tx_compl_process(adapter, last_index);
+ }
+}
+
+static void be_tx_queues_destroy(struct be_adapter *adapter)
+{
+ struct be_queue_info *q;
+
+ q = &adapter->tx_obj.q;
+ if (q->created)
+ be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_TXQ);
+ be_queue_free(adapter, q);
+
+ q = &adapter->tx_obj.cq;
+ if (q->created)
+ be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_CQ);
+ be_queue_free(adapter, q);
+
+ /* No more tx completions can be rcvd now; clean up if there are
+ * any pending completions or pending tx requests */
+ be_tx_q_clean(adapter);
+
+ q = &adapter->tx_eq.q;
+ if (q->created)
+ be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_EQ);
+ be_queue_free(adapter, q);
+}
+
+static int be_tx_queues_create(struct be_adapter *adapter)
+{
+ struct be_queue_info *eq, *q, *cq;
+
+ adapter->tx_eq.max_eqd = 0;
+ adapter->tx_eq.min_eqd = 0;
+ adapter->tx_eq.cur_eqd = 96;
+ adapter->tx_eq.enable_aic = false;
+ /* Alloc Tx Event queue */
+ eq = &adapter->tx_eq.q;
+ if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
+ return -1;
+
+ /* Ask BE to create Tx Event queue */
+ if (be_cmd_eq_create(&adapter->ctrl, eq, adapter->tx_eq.cur_eqd))
+ goto tx_eq_free;
+ /* Alloc TX eth compl queue */
+ cq = &adapter->tx_obj.cq;
+ if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
+ sizeof(struct be_eth_tx_compl)))
+ goto tx_eq_destroy;
+
+ /* Ask BE to create Tx eth compl queue */
+ if (be_cmd_cq_create(&adapter->ctrl, cq, eq, false, false, 3))
+ goto tx_cq_free;
+
+ /* Alloc TX eth queue */
+ q = &adapter->tx_obj.q;
+ if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
+ goto tx_cq_destroy;
+
+ /* Ask BE to create Tx eth queue */
+ if (be_cmd_txq_create(&adapter->ctrl, q, cq))
+ goto tx_q_free;
+ return 0;
+
+tx_q_free:
+ be_queue_free(adapter, q);
+tx_cq_destroy:
+ be_cmd_q_destroy(&adapter->ctrl, cq, QTYPE_CQ);
+tx_cq_free:
+ be_queue_free(adapter, cq);
+tx_eq_destroy:
+ be_cmd_q_destroy(&adapter->ctrl, eq, QTYPE_EQ);
+tx_eq_free:
+ be_queue_free(adapter, eq);
+ return -1;
+}
+
+static void be_rx_queues_destroy(struct be_adapter *adapter)
+{
+ struct be_queue_info *q;
+
+ q = &adapter->rx_obj.q;
+ if (q->created) {
+ be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_RXQ);
+ be_rx_q_clean(adapter);
+ }
+ be_queue_free(adapter, q);
+
+ q = &adapter->rx_obj.cq;
+ if (q->created)
+ be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_CQ);
+ be_queue_free(adapter, q);
+
+ q = &adapter->rx_eq.q;
+ if (q->created)
+ be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_EQ);
+ be_queue_free(adapter, q);
+}
+
+static int be_rx_queues_create(struct be_adapter *adapter)
+{
+ struct be_queue_info *eq, *q, *cq;
+ int rc;
+
+ adapter->max_rx_coal = BE_MAX_FRAGS_PER_FRAME;
+ adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
+ adapter->rx_eq.max_eqd = BE_MAX_EQD;
+ adapter->rx_eq.min_eqd = 0;
+ adapter->rx_eq.cur_eqd = 0;
+ adapter->rx_eq.enable_aic = true;
+
+ /* Alloc Rx Event queue */
+ eq = &adapter->rx_eq.q;
+ rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
+ sizeof(struct be_eq_entry));
+ if (rc)
+ return rc;
+
+ /* Ask BE to create Rx Event queue */
+ rc = be_cmd_eq_create(&adapter->ctrl, eq, adapter->rx_eq.cur_eqd);
+ if (rc)
+ goto rx_eq_free;
+
+ /* Alloc RX eth compl queue */
+ cq = &adapter->rx_obj.cq;
+ rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
+ sizeof(struct be_eth_rx_compl));
+ if (rc)
+ goto rx_eq_destroy;
+
+ /* Ask BE to create Rx eth compl queue */
+ rc = be_cmd_cq_create(&adapter->ctrl, cq, eq, false, false, 3);
+ if (rc)
+ goto rx_cq_free;
+
+ /* Alloc RX eth queue */
+ q = &adapter->rx_obj.q;
+ rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
+ if (rc)
+ goto rx_cq_destroy;
+
+ /* Ask BE to create Rx eth queue */
+ rc = be_cmd_rxq_create(&adapter->ctrl, q, cq->id, rx_frag_size,
+ BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
+ if (rc)
+ goto rx_q_free;
+
+ return 0;
+rx_q_free:
+ be_queue_free(adapter, q);
+rx_cq_destroy:
+ be_cmd_q_destroy(&adapter->ctrl, cq, QTYPE_CQ);
+rx_cq_free:
+ be_queue_free(adapter, cq);
+rx_eq_destroy:
+ be_cmd_q_destroy(&adapter->ctrl, eq, QTYPE_EQ);
+rx_eq_free:
+ be_queue_free(adapter, eq);
+ return rc;
+}
+static bool event_get(struct be_eq_obj *eq_obj, u16 *rid)
+{
+ struct be_eq_entry *entry = queue_tail_node(&eq_obj->q);
+ u32 evt = entry->evt;
+
+ if (!evt)
+ return false;
+
+ evt = le32_to_cpu(evt);
+ *rid = (evt >> EQ_ENTRY_RES_ID_SHIFT) & EQ_ENTRY_RES_ID_MASK;
+ entry->evt = 0;
+ queue_tail_inc(&eq_obj->q);
+ return true;
+}
+
+static int event_handle(struct be_ctrl_info *ctrl,
+ struct be_eq_obj *eq_obj)
+{
+ u16 rid = 0, num = 0;
+
+ while (event_get(eq_obj, &rid))
+ num++;
+
+ /* We can see an interrupt and no event */
+ be_eq_notify(ctrl, eq_obj->q.id, true, true, num);
+ if (num)
+ napi_schedule(&eq_obj->napi);
+
+ return num;
+}
+
+static irqreturn_t be_intx(int irq, void *dev)
+{
+ struct be_adapter *adapter = dev;
+ struct be_ctrl_info *ctrl = &adapter->ctrl;
+ int rx, tx;
+
+ tx = event_handle(ctrl, &adapter->tx_eq);
+ rx = event_handle(ctrl, &adapter->rx_eq);
+
+ if (rx || tx)
+ return IRQ_HANDLED;
+ else
+ return IRQ_NONE;
+}
+
+static irqreturn_t be_msix_rx(int irq, void *dev)
+{
+ struct be_adapter *adapter = dev;
+
+ event_handle(&adapter->ctrl, &adapter->rx_eq);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t be_msix_tx(int irq, void *dev)
+{
+ struct be_adapter *adapter = dev;
+
+ event_handle(&adapter->ctrl, &adapter->tx_eq);
+
+ return IRQ_HANDLED;
+}
+
+static inline bool do_lro(struct be_adapter *adapter,
+ struct be_eth_rx_compl *rxcp)
+{
+ int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
+ int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
+
+ if (err)
+ drvr_stats(adapter)->be_rxcp_err++;
+
+ return (!tcp_frame || err || (adapter->max_rx_coal <= 1)) ?
+ false : true;
+}
+
+int be_poll_rx(struct napi_struct *napi, int budget)
+{
+ struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
+ struct be_adapter *adapter =
+ container_of(rx_eq, struct be_adapter, rx_eq);
+ struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
+ struct be_eth_rx_compl *rxcp;
+ u32 work_done;
+
+ for (work_done = 0; work_done < budget; work_done++) {
+ rxcp = be_rx_compl_get(adapter);
+ if (!rxcp)
+ break;
+
+ if (do_lro(adapter, rxcp))
+ be_rx_compl_process_lro(adapter, rxcp);
+ else
+ be_rx_compl_process(adapter, rxcp);
+ }
+
+ lro_flush_all(&adapter->rx_obj.lro_mgr);
+
+ /* Refill the queue */
+ if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
+ be_post_rx_frags(adapter);
+
+ /* All consumed */
+ if (work_done < budget) {
+ napi_complete(napi);
+ be_cq_notify(&adapter->ctrl, rx_cq->id, true, work_done);
+ } else {
+ /* More to be consumed; continue with interrupts disabled */
+ be_cq_notify(&adapter->ctrl, rx_cq->id, false, work_done);
+ }
+ return work_done;
+}
+
+/* For TX we don't honour budget; consume everything */
+int be_poll_tx(struct napi_struct *napi, int budget)
+{
+ struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
+ struct be_adapter *adapter =
+ container_of(tx_eq, struct be_adapter, tx_eq);
+ struct be_tx_obj *tx_obj = &adapter->tx_obj;
+ struct be_queue_info *tx_cq = &tx_obj->cq;
+ struct be_queue_info *txq = &tx_obj->q;
+ struct be_eth_tx_compl *txcp;
+ u32 num_cmpl = 0;
+ u16 end_idx;
+
+ while ((txcp = be_tx_compl_get(adapter))) {
+ end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
+ wrb_index, txcp);
+ be_tx_compl_process(adapter, end_idx);
+ num_cmpl++;
+ }
+
+ /* As Tx wrbs have been freed up, wake up netdev queue if
+ * it was stopped due to lack of tx wrbs.
+ */
+ if (netif_queue_stopped(adapter->netdev) &&
+ atomic_read(&txq->used) < txq->len / 2) {
+ netif_wake_queue(adapter->netdev);
+ }
+
+ napi_complete(napi);
+
+ be_cq_notify(&adapter->ctrl, tx_cq->id, true, num_cmpl);
+
+ drvr_stats(adapter)->be_tx_events++;
+ drvr_stats(adapter)->be_tx_compl += num_cmpl;
+
+ return 1;
+}
+
+static void be_msix_enable(struct be_adapter *adapter)
+{
+ int i, status;
+
+ for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
+ adapter->msix_entries[i].entry = i;
+
+ status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
+ BE_NUM_MSIX_VECTORS);
+ if (status == 0)
+ adapter->msix_enabled = true;
+ return;
+}
+
+static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
+{
+ return adapter->msix_entries[eq_id -
+ 8 * adapter->ctrl.pci_func].vector;
+}
+
+static int be_msix_register(struct be_adapter *adapter)
+{
+ struct net_device *netdev = adapter->netdev;
+ struct be_eq_obj *tx_eq = &adapter->tx_eq;
+ struct be_eq_obj *rx_eq = &adapter->rx_eq;
+ int status, vec;
+
+ sprintf(tx_eq->desc, "%s-tx", netdev->name);
+ vec = be_msix_vec_get(adapter, tx_eq->q.id);
+ status = request_irq(vec, be_msix_tx, 0, tx_eq->desc, adapter);
+ if (status)
+ goto err;
+
+ sprintf(rx_eq->desc, "%s-rx", netdev->name);
+ vec = be_msix_vec_get(adapter, rx_eq->q.id);
+ status = request_irq(vec, be_msix_rx, 0, rx_eq->desc, adapter);
+ if (status) { /* Free TX IRQ */
+ vec = be_msix_vec_get(adapter, tx_eq->q.id);
+ free_irq(vec, adapter);
+ goto err;
+ }
+ return 0;
+err:
+ dev_warn(&adapter->pdev->dev,
+ "MSIX Request IRQ failed - err %d\n", status);
+ pci_disable_msix(adapter->pdev);
+ adapter->msix_enabled = false;
+ return status;
+}
+
+static int be_irq_register(struct be_adapter *adapter)
+{
+ struct net_device *netdev = adapter->netdev;
+ int status;
+
+ if (adapter->msix_enabled) {
+ status = be_msix_register(adapter);
+ if (status == 0)
+ goto done;
+ }
+
+ /* INTx */
+ netdev->irq = adapter->pdev->irq;
+ status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
+ adapter);
+ if (status) {
+ dev_err(&adapter->pdev->dev,
+ "INTx request IRQ failed - err %d\n", status);
+ return status;
+ }
+done:
+ adapter->isr_registered = true;
+ return 0;
+}
+
+static void be_irq_unregister(struct be_adapter *adapter)
+{
+ struct net_device *netdev = adapter->netdev;
+ int vec;
+
+ if (!adapter->isr_registered)
+ return;
+
+ /* INTx */
+ if (!adapter->msix_enabled) {
+ free_irq(netdev->irq, adapter);
+ goto done;
+ }
+
+ /* MSIx */
+ vec = be_msix_vec_get(adapter, adapter->tx_eq.q.id);
+ free_irq(vec, adapter);
+ vec = be_msix_vec_get(adapter, adapter->rx_eq.q.id);
+ free_irq(vec, adapter);
+done:
+ adapter->isr_registered = false;
+ return;
+}
+
+static int be_open(struct net_device *netdev)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+ struct be_ctrl_info *ctrl = &adapter->ctrl;
+ struct be_eq_obj *rx_eq = &adapter->rx_eq;
+ struct be_eq_obj *tx_eq = &adapter->tx_eq;
+ u32 if_flags;
+ int status;
+
+ if_flags = BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_PROMISCUOUS |
+ BE_IF_FLAGS_MCAST_PROMISCUOUS | BE_IF_FLAGS_UNTAGGED |
+ BE_IF_FLAGS_PASS_L3L4_ERRORS;
+ status = be_cmd_if_create(ctrl, if_flags, netdev->dev_addr,
+ false/* pmac_invalid */, &adapter->if_handle,
+ &adapter->pmac_id);
+ if (status != 0)
+ goto do_none;
+
+ status = be_cmd_set_flow_control(ctrl, true, true);
+ if (status != 0)
+ goto if_destroy;
+
+ status = be_tx_queues_create(adapter);
+ if (status != 0)
+ goto if_destroy;
+
+ status = be_rx_queues_create(adapter);
+ if (status != 0)
+ goto tx_qs_destroy;
+
+ /* First time posting */
+ be_post_rx_frags(adapter);
+
+ napi_enable(&rx_eq->napi);
+ napi_enable(&tx_eq->napi);
+
+ be_irq_register(adapter);
+
+ be_intr_set(ctrl, true);
+
+ /* The evt queues are created in the unarmed state; arm them */
+ be_eq_notify(ctrl, rx_eq->q.id, true, false, 0);
+ be_eq_notify(ctrl, tx_eq->q.id, true, false, 0);
+
+ /* The compl queues are created in the unarmed state; arm them */
+ be_cq_notify(ctrl, adapter->rx_obj.cq.id, true, 0);
+ be_cq_notify(ctrl, adapter->tx_obj.cq.id, true, 0);
+
+ be_link_status_update(adapter);
+
+ schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
+ return 0;
+
+tx_qs_destroy:
+ be_tx_queues_destroy(adapter);
+if_destroy:
+ be_cmd_if_destroy(ctrl, adapter->if_handle);
+do_none:
+ return status;
+}
+
+static int be_close(struct net_device *netdev)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+ struct be_ctrl_info *ctrl = &adapter->ctrl;
+ struct be_eq_obj *rx_eq = &adapter->rx_eq;
+ struct be_eq_obj *tx_eq = &adapter->tx_eq;
+ int vec;
+
+ cancel_delayed_work(&adapter->work);
+
+ netif_stop_queue(netdev);
+ netif_carrier_off(netdev);
+ adapter->link.speed = PHY_LINK_SPEED_ZERO;
+
+ be_intr_set(ctrl, false);
+
+ if (adapter->msix_enabled) {
+ vec = be_msix_vec_get(adapter, tx_eq->q.id);
+ synchronize_irq(vec);
+ vec = be_msix_vec_get(adapter, rx_eq->q.id);
+ synchronize_irq(vec);
+ } else {
+ synchronize_irq(netdev->irq);
+ }
+ be_irq_unregister(adapter);
+
+ napi_disable(&rx_eq->napi);
+ napi_disable(&tx_eq->napi);
+
+ be_rx_queues_destroy(adapter);
+ be_tx_queues_destroy(adapter);
+
+ be_cmd_if_destroy(ctrl, adapter->if_handle);
+ return 0;
+}
+
+static int be_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
+ void **ip_hdr, void **tcpudp_hdr,
+ u64 *hdr_flags, void *priv)
+{
+ struct ethhdr *eh;
+ struct vlan_ethhdr *veh;
+ struct iphdr *iph;
+ u8 *va = page_address(frag->page) + frag->page_offset;
+ unsigned long ll_hlen;
+
+ prefetch(va);
+ eh = (struct ethhdr *)va;
+ *mac_hdr = eh;
+ ll_hlen = ETH_HLEN;
+ if (eh->h_proto != htons(ETH_P_IP)) {
+ if (eh->h_proto == htons(ETH_P_8021Q)) {
+ veh = (struct vlan_ethhdr *)va;
+ if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
+ return -1;
+
+ ll_hlen += VLAN_HLEN;
+ } else {
+ return -1;
+ }
+ }
+ *hdr_flags = LRO_IPV4;
+ iph = (struct iphdr *)(va + ll_hlen);
+ *ip_hdr = iph;
+ if (iph->protocol != IPPROTO_TCP)
+ return -1;
+ *hdr_flags |= LRO_TCP;
+ *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
+
+ return 0;
+}
+
+static void be_lro_init(struct be_adapter *adapter, struct net_device *netdev)
+{
+ struct net_lro_mgr *lro_mgr;
+
+ lro_mgr = &adapter->rx_obj.lro_mgr;
+ lro_mgr->dev = netdev;
+ lro_mgr->features = LRO_F_NAPI;
+ lro_mgr->ip_summed = CHECKSUM_UNNECESSARY;
+ lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
+ lro_mgr->max_desc = BE_MAX_LRO_DESCRIPTORS;
+ lro_mgr->lro_arr = adapter->rx_obj.lro_desc;
+ lro_mgr->get_frag_header = be_get_frag_header;
+ lro_mgr->max_aggr = BE_MAX_FRAGS_PER_FRAME;
+}
+
+static struct net_device_ops be_netdev_ops = {
+ .ndo_open = be_open,
+ .ndo_stop = be_close,
+ .ndo_start_xmit = be_xmit,
+ .ndo_get_stats = be_get_stats,
+ .ndo_set_rx_mode = be_set_multicast_list,
+ .ndo_set_mac_address = be_mac_addr_set,
+ .ndo_change_mtu = be_change_mtu,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_vlan_rx_register = be_vlan_register,
+ .ndo_vlan_rx_add_vid = be_vlan_add_vid,
+ .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
+};
+
+static void be_netdev_init(struct net_device *netdev)
+{
+ struct be_adapter *adapter = netdev_priv(netdev);
+
+ netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
+ NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_IP_CSUM |
+ NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
+
+ netdev->flags |= IFF_MULTICAST;
+
+ BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
+
+ SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
+
+ be_lro_init(adapter, netdev);
+
+ netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
+ BE_NAPI_WEIGHT);
+ netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx,
+ BE_NAPI_WEIGHT);
+
+ netif_carrier_off(netdev);
+ netif_stop_queue(netdev);
+}
+
+static void be_unmap_pci_bars(struct be_adapter *adapter)
+{
+ struct be_ctrl_info *ctrl = &adapter->ctrl;
+ if (ctrl->csr)
+ iounmap(ctrl->csr);
+ if (ctrl->db)
+ iounmap(ctrl->db);
+ if (ctrl->pcicfg)
+ iounmap(ctrl->pcicfg);
+}
+
+static int be_map_pci_bars(struct be_adapter *adapter)
+{
+ u8 __iomem *addr;
+
+ addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
+ pci_resource_len(adapter->pdev, 2));
+ if (addr == NULL)
+ return -ENOMEM;
+ adapter->ctrl.csr = addr;
+
+ addr = ioremap_nocache(pci_resource_start(adapter->pdev, 4),
+ 128 * 1024);
+ if (addr == NULL)
+ goto pci_map_err;
+ adapter->ctrl.db = addr;
+
+ addr = ioremap_nocache(pci_resource_start(adapter->pdev, 1),
+ pci_resource_len(adapter->pdev, 1));
+ if (addr == NULL)
+ goto pci_map_err;
+ adapter->ctrl.pcicfg = addr;
+
+ return 0;
+pci_map_err:
+ be_unmap_pci_bars(adapter);
+ return -ENOMEM;
+}
+
+
+static void be_ctrl_cleanup(struct be_adapter *adapter)
+{
+ struct be_dma_mem *mem = &adapter->ctrl.mbox_mem_alloced;
+
+ be_unmap_pci_bars(adapter);
+
+ if (mem->va)
+ pci_free_consistent(adapter->pdev, mem->size,
+ mem->va, mem->dma);
+}
+
+/* Initialize the mbox required to send cmds to BE */
+static int be_ctrl_init(struct be_adapter *adapter)
+{
+ struct be_ctrl_info *ctrl = &adapter->ctrl;
+ struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
+ struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
+ int status;
+ u32 val;
+
+ status = be_map_pci_bars(adapter);
+ if (status)
+ return status;
+
+ mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
+ mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
+ mbox_mem_alloc->size, &mbox_mem_alloc->dma);
+ if (!mbox_mem_alloc->va) {
+ be_unmap_pci_bars(adapter);
+ return -1;
+ }
+ mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
+ mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
+ mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
+ memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
+ spin_lock_init(&ctrl->cmd_lock);
+
+ val = ioread32(ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
+ ctrl->pci_func = (val >> MEMBAR_CTRL_INT_CTRL_PFUNC_SHIFT) &
+ MEMBAR_CTRL_INT_CTRL_PFUNC_MASK;
+ return 0;
+}
+
+static void be_stats_cleanup(struct be_adapter *adapter)
+{
+ struct be_stats_obj *stats = &adapter->stats;
+ struct be_dma_mem *cmd = &stats->cmd;
+
+ if (cmd->va)
+ pci_free_consistent(adapter->pdev, cmd->size,
+ cmd->va, cmd->dma);
+}
+
+static int be_stats_init(struct be_adapter *adapter)
+{
+ struct be_stats_obj *stats = &adapter->stats;
+ struct be_dma_mem *cmd = &stats->cmd;
+
+ cmd->size = sizeof(struct be_cmd_req_get_stats);
+ cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
+ if (cmd->va == NULL)
+ return -1;
+ return 0;
+}
+
+static void __devexit be_remove(struct pci_dev *pdev)
+{
+ struct be_adapter *adapter = pci_get_drvdata(pdev);
+ if (!adapter)
+ return;
+
+ unregister_netdev(adapter->netdev);
+
+ be_stats_cleanup(adapter);
+
+ be_ctrl_cleanup(adapter);
+
+ if (adapter->msix_enabled) {
+ pci_disable_msix(adapter->pdev);
+ adapter->msix_enabled = false;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+
+ free_netdev(adapter->netdev);
+}
+
+static int be_hw_up(struct be_adapter *adapter)
+{
+ struct be_ctrl_info *ctrl = &adapter->ctrl;
+ int status;
+
+ status = be_cmd_POST(ctrl);
+ if (status)
+ return status;
+
+ status = be_cmd_get_fw_ver(ctrl, adapter->fw_ver);
+ if (status)
+ return status;
+
+ status = be_cmd_query_fw_cfg(ctrl, &adapter->port_num);
+ return status;
+}
+
+static int __devinit be_probe(struct pci_dev *pdev,
+ const struct pci_device_id *pdev_id)
+{
+ int status = 0;
+ struct be_adapter *adapter;
+ struct net_device *netdev;
+ struct be_ctrl_info *ctrl;
+ u8 mac[ETH_ALEN];
+
+ status = pci_enable_device(pdev);
+ if (status)
+ goto do_none;
+
+ status = pci_request_regions(pdev, DRV_NAME);
+ if (status)
+ goto disable_dev;
+ pci_set_master(pdev);
+
+ netdev = alloc_etherdev(sizeof(struct be_adapter));
+ if (netdev == NULL) {
+ status = -ENOMEM;
+ goto rel_reg;
+ }
+ adapter = netdev_priv(netdev);
+ adapter->pdev = pdev;
+ pci_set_drvdata(pdev, adapter);
+ adapter->netdev = netdev;
+
+ be_msix_enable(adapter);
+
+ status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
+ if (!status) {
+ netdev->features |= NETIF_F_HIGHDMA;
+ } else {
+ status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
+ if (status) {
+ dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
+ goto free_netdev;
+ }
+ }
+
+ ctrl = &adapter->ctrl;
+ status = be_ctrl_init(adapter);
+ if (status)
+ goto free_netdev;
+
+ status = be_stats_init(adapter);
+ if (status)
+ goto ctrl_clean;
+
+ status = be_hw_up(adapter);
+ if (status)
+ goto stats_clean;
+
+ status = be_cmd_mac_addr_query(ctrl, mac, MAC_ADDRESS_TYPE_NETWORK,
+ true /* permanent */, 0);
+ if (status)
+ goto stats_clean;
+ memcpy(netdev->dev_addr, mac, ETH_ALEN);
+
+ INIT_DELAYED_WORK(&adapter->work, be_worker);
+ be_netdev_init(netdev);
+ SET_NETDEV_DEV(netdev, &adapter->pdev->dev);
+
+ status = register_netdev(netdev);
+ if (status != 0)
+ goto stats_clean;
+
+ dev_info(&pdev->dev, BE_NAME " port %d\n", adapter->port_num);
+ return 0;
+
+stats_clean:
+ be_stats_cleanup(adapter);
+ctrl_clean:
+ be_ctrl_cleanup(adapter);
+free_netdev:
+ free_netdev(adapter->netdev);
+rel_reg:
+ pci_release_regions(pdev);
+disable_dev:
+ pci_disable_device(pdev);
+do_none:
+ dev_warn(&pdev->dev, BE_NAME " initialization failed\n");
+ return status;
+}
+
+static int be_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ struct be_adapter *adapter = pci_get_drvdata(pdev);
+ struct net_device *netdev = adapter->netdev;
+
+ netif_device_detach(netdev);
+ if (netif_running(netdev)) {
+ rtnl_lock();
+ be_close(netdev);
+ rtnl_unlock();
+ }
+
+ pci_save_state(pdev);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+ return 0;
+}
+
+static int be_resume(struct pci_dev *pdev)
+{
+ int status = 0;
+ struct be_adapter *adapter = pci_get_drvdata(pdev);
+ struct net_device *netdev = adapter->netdev;
+
+ netif_device_detach(netdev);
+
+ status = pci_enable_device(pdev);
+ if (status)
+ return status;
+
+ pci_set_power_state(pdev, 0);
+ pci_restore_state(pdev);
+
+ be_vids_config(netdev);
+
+ if (netif_running(netdev)) {
+ rtnl_lock();
+ be_open(netdev);
+ rtnl_unlock();
+ }
+ netif_device_attach(netdev);
+ return 0;
+}
+
+static struct pci_driver be_driver = {
+ .name = DRV_NAME,
+ .id_table = be_dev_ids,
+ .probe = be_probe,
+ .remove = be_remove,
+ .suspend = be_suspend,
+ .resume = be_resume
+};
+
+static int __init be_init_module(void)
+{
+ if (rx_frag_size != 8192 && rx_frag_size != 4096
+ && rx_frag_size != 2048) {
+ printk(KERN_WARNING DRV_NAME
+ " : Module param rx_frag_size must be 2048/4096/8192."
+ " Using 2048\n");
+ rx_frag_size = 2048;
+ }
+ /* Ensure rx_frag_size is aligned to chache line */
+ if (SKB_DATA_ALIGN(rx_frag_size) != rx_frag_size) {
+ printk(KERN_WARNING DRV_NAME
+ " : Bad module param rx_frag_size. Using 2048\n");
+ rx_frag_size = 2048;
+ }
+
+ return pci_register_driver(&be_driver);
+}
+module_init(be_init_module);
+
+static void __exit be_exit_module(void)
+{
+ pci_unregister_driver(&be_driver);
+}
+module_exit(be_exit_module);
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 15a5cf0f676..3cf2b92eef3 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -152,7 +152,7 @@ struct sw_rx_page {
#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
#define SGE_PAGE_SIZE PAGE_SIZE
#define SGE_PAGE_SHIFT PAGE_SHIFT
-#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN(addr)
+#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))addr)
#define BCM_RX_ETH_PAYLOAD_ALIGN 64
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index a6c0b3abba2..3b0c2499ef1 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -150,7 +150,6 @@ static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
{
-#ifdef USE_DMAE
int offset = 0;
if (bp->dmae_ready) {
@@ -164,9 +163,6 @@ static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
addr + offset, len);
} else
bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
-#else
- bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
-#endif
}
static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index d3e7775a9cc..2e346a5e98c 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -57,7 +57,7 @@
#include "bnx2x.h"
#include "bnx2x_init.h"
-#define DRV_MODULE_VERSION "1.45.26"
+#define DRV_MODULE_VERSION "1.45.27"
#define DRV_MODULE_RELDATE "2009/01/26"
#define BNX2X_BC_VER 0x040200
@@ -4035,10 +4035,10 @@ static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
{
int port = BP_PORT(bp);
- bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
+ bnx2x_init_fill(bp, USTORM_INTMEM_ADDR +
USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
sizeof(struct ustorm_status_block)/4);
- bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
+ bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR +
CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
sizeof(struct cstorm_status_block)/4);
}
@@ -4092,18 +4092,18 @@ static void bnx2x_zero_def_sb(struct bnx2x *bp)
{
int func = BP_FUNC(bp);
- bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
+ bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR +
+ TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
+ sizeof(struct tstorm_def_status_block)/4);
+ bnx2x_init_fill(bp, USTORM_INTMEM_ADDR +
USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
sizeof(struct ustorm_def_status_block)/4);
- bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
+ bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR +
CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
sizeof(struct cstorm_def_status_block)/4);
- bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM +
+ bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR +
XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
sizeof(struct xstorm_def_status_block)/4);
- bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM +
- TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
- sizeof(struct tstorm_def_status_block)/4);
}
static void bnx2x_init_def_sb(struct bnx2x *bp,
@@ -4518,7 +4518,8 @@ static void bnx2x_init_context(struct bnx2x *bp)
(USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA |
USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING);
context->ustorm_st_context.common.sge_buff_size =
- (u16)(BCM_PAGE_SIZE*PAGES_PER_SGE);
+ (u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE,
+ (u32)0xffff);
context->ustorm_st_context.common.sge_page_base_hi =
U64_HI(fp->rx_sge_mapping);
context->ustorm_st_context.common.sge_page_base_lo =
diff --git a/drivers/net/dnet.c b/drivers/net/dnet.c
new file mode 100644
index 00000000000..5c347f70cb6
--- /dev/null
+++ b/drivers/net/dnet.c
@@ -0,0 +1,994 @@
+/*
+ * Dave DNET Ethernet Controller driver
+ *
+ * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
+ * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+
+#include "dnet.h"
+
+#undef DEBUG
+
+/* function for reading internal MAC register */
+u16 dnet_readw_mac(struct dnet *bp, u16 reg)
+{
+ u16 data_read;
+
+ /* issue a read */
+ dnet_writel(bp, reg, MACREG_ADDR);
+
+ /* since a read/write op to the MAC is very slow,
+ * we must wait before reading the data */
+ ndelay(500);
+
+ /* read data read from the MAC register */
+ data_read = dnet_readl(bp, MACREG_DATA);
+
+ /* all done */
+ return data_read;
+}
+
+/* function for writing internal MAC register */
+void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val)
+{
+ /* load data to write */
+ dnet_writel(bp, val, MACREG_DATA);
+
+ /* issue a write */
+ dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR);
+
+ /* since a read/write op to the MAC is very slow,
+ * we must wait before exiting */
+ ndelay(500);
+}
+
+static void __dnet_set_hwaddr(struct dnet *bp)
+{
+ u16 tmp;
+
+ tmp = cpu_to_be16(*((u16 *) bp->dev->dev_addr));
+ dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
+ tmp = cpu_to_be16(*((u16 *) (bp->dev->dev_addr + 2)));
+ dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
+ tmp = cpu_to_be16(*((u16 *) (bp->dev->dev_addr + 4)));
+ dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
+}
+
+static void __devinit dnet_get_hwaddr(struct dnet *bp)
+{
+ u16 tmp;
+ u8 addr[6];
+
+ /*
+ * from MAC docs:
+ * "Note that the MAC address is stored in the registers in Hexadecimal
+ * form. For example, to set the MAC Address to: AC-DE-48-00-00-80
+ * would require writing 0xAC (octet 0) to address 0x0B (high byte of
+ * Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of
+ * Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of
+ * Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of
+ * Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of
+ * Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of
+ * Mac_addr[15:0]).
+ */
+ tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG);
+ *((u16 *) addr) = be16_to_cpu(tmp);
+ tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG);
+ *((u16 *) (addr + 2)) = be16_to_cpu(tmp);
+ tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG);
+ *((u16 *) (addr + 4)) = be16_to_cpu(tmp);
+
+ if (is_valid_ether_addr(addr))
+ memcpy(bp->dev->dev_addr, addr, sizeof(addr));
+}
+
+static int dnet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+ struct dnet *bp = bus->priv;
+ u16 value;
+
+ while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
+ & DNET_INTERNAL_GMII_MNG_CMD_FIN))
+ cpu_relax();
+
+ /* only 5 bits allowed for phy-addr and reg_offset */
+ mii_id &= 0x1f;
+ regnum &= 0x1f;
+
+ /* prepare reg_value for a read */
+ value = (mii_id << 8);
+ value |= regnum;
+
+ /* write control word */
+ dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
+
+ /* wait for end of transfer */
+ while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
+ & DNET_INTERNAL_GMII_MNG_CMD_FIN))
+ cpu_relax();
+
+ value = dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG);
+
+ pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id, regnum, value);
+
+ return value;
+}
+
+static int dnet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
+ u16 value)
+{
+ struct dnet *bp = bus->priv;
+ u16 tmp;
+
+ pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id, regnum, value);
+
+ while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
+ & DNET_INTERNAL_GMII_MNG_CMD_FIN))
+ cpu_relax();
+
+ /* prepare for a write operation */
+ tmp = (1 << 13);
+
+ /* only 5 bits allowed for phy-addr and reg_offset */
+ mii_id &= 0x1f;
+ regnum &= 0x1f;
+
+ /* only 16 bits on data */
+ value &= 0xffff;
+
+ /* prepare reg_value for a write */
+ tmp |= (mii_id << 8);
+ tmp |= regnum;
+
+ /* write data to write first */
+ dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
+
+ /* write control word */
+ dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
+
+ while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
+ & DNET_INTERNAL_GMII_MNG_CMD_FIN))
+ cpu_relax();
+
+ return 0;
+}
+
+static int dnet_mdio_reset(struct mii_bus *bus)
+{
+ return 0;
+}
+
+static void dnet_handle_link_change(struct net_device *dev)
+{
+ struct dnet *bp = netdev_priv(dev);
+ struct phy_device *phydev = bp->phy_dev;
+ unsigned long flags;
+ u32 mode_reg, ctl_reg;
+
+ int status_change = 0;
+
+ spin_lock_irqsave(&bp->lock, flags);
+
+ mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG);
+ ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
+
+ if (phydev->link) {
+ if (bp->duplex != phydev->duplex) {
+ if (phydev->duplex)
+ ctl_reg &=
+ ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
+ else
+ ctl_reg |=
+ DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
+
+ bp->duplex = phydev->duplex;
+ status_change = 1;
+ }
+
+ if (bp->speed != phydev->speed) {
+ status_change = 1;
+ switch (phydev->speed) {
+ case 1000:
+ mode_reg |= DNET_INTERNAL_MODE_GBITEN;
+ break;
+ case 100:
+ case 10:
+ mode_reg &= ~DNET_INTERNAL_MODE_GBITEN;
+ break;
+ default:
+ printk(KERN_WARNING
+ "%s: Ack! Speed (%d) is not "
+ "10/100/1000!\n", dev->name,
+ phydev->speed);
+ break;
+ }
+ bp->speed = phydev->speed;
+ }
+ }
+
+ if (phydev->link != bp->link) {
+ if (phydev->link) {
+ mode_reg |=
+ (DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
+ } else {
+ mode_reg &=
+ ~(DNET_INTERNAL_MODE_RXEN |
+ DNET_INTERNAL_MODE_TXEN);
+ bp->speed = 0;
+ bp->duplex = -1;
+ }
+ bp->link = phydev->link;
+
+ status_change = 1;
+ }
+
+ if (status_change) {
+ dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
+ dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg);
+ }
+
+ spin_unlock_irqrestore(&bp->lock, flags);
+
+ if (status_change) {
+ if (phydev->link)
+ printk(KERN_INFO "%s: link up (%d/%s)\n",
+ dev->name, phydev->speed,
+ DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
+ else
+ printk(KERN_INFO "%s: link down\n", dev->name);
+ }
+}
+
+static int dnet_mii_probe(struct net_device *dev)
+{
+ struct dnet *bp = netdev_priv(dev);
+ struct phy_device *phydev = NULL;
+ int phy_addr;
+
+ /* find the first phy */
+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
+ if (bp->mii_bus->phy_map[phy_addr]) {
+ phydev = bp->mii_bus->phy_map[phy_addr];
+ break;
+ }
+ }
+
+ if (!phydev) {
+ printk(KERN_ERR "%s: no PHY found\n", dev->name);
+ return -ENODEV;
+ }
+
+ /* TODO : add pin_irq */
+
+ /* attach the mac to the phy */
+ if (bp->capabilities & DNET_HAS_RMII) {
+ phydev = phy_connect(dev, phydev->dev.bus_id,
+ &dnet_handle_link_change, 0,
+ PHY_INTERFACE_MODE_RMII);
+ } else {
+ phydev = phy_connect(dev, phydev->dev.bus_id,
+ &dnet_handle_link_change, 0,
+ PHY_INTERFACE_MODE_MII);
+ }
+
+ if (IS_ERR(phydev)) {
+ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
+ return PTR_ERR(phydev);
+ }
+
+ /* mask with MAC supported features */
+ if (bp->capabilities & DNET_HAS_GIGABIT)
+ phydev->supported &= PHY_GBIT_FEATURES;
+ else
+ phydev->supported &= PHY_BASIC_FEATURES;
+
+ phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause;
+
+ phydev->advertising = phydev->supported;
+
+ bp->link = 0;
+ bp->speed = 0;
+ bp->duplex = -1;
+ bp->phy_dev = phydev;
+
+ return 0;
+}
+
+static int dnet_mii_init(struct dnet *bp)
+{
+ int err, i;
+
+ bp->mii_bus = mdiobus_alloc();
+ if (bp->mii_bus == NULL)
+ return -ENOMEM;
+
+ bp->mii_bus->name = "dnet_mii_bus";
+ bp->mii_bus->read = &dnet_mdio_read;
+ bp->mii_bus->write = &dnet_mdio_write;
+ bp->mii_bus->reset = &dnet_mdio_reset;
+
+ snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
+
+ bp->mii_bus->priv = bp;
+
+ bp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+ if (!bp->mii_bus->irq) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ for (i = 0; i < PHY_MAX_ADDR; i++)
+ bp->mii_bus->irq[i] = PHY_POLL;
+
+ platform_set_drvdata(bp->dev, bp->mii_bus);
+
+ if (mdiobus_register(bp->mii_bus)) {
+ err = -ENXIO;
+ goto err_out_free_mdio_irq;
+ }
+
+ if (dnet_mii_probe(bp->dev) != 0) {
+ err = -ENXIO;
+ goto err_out_unregister_bus;
+ }
+
+ return 0;
+
+err_out_unregister_bus:
+ mdiobus_unregister(bp->mii_bus);
+err_out_free_mdio_irq:
+ kfree(bp->mii_bus->irq);
+err_out:
+ mdiobus_free(bp->mii_bus);
+ return err;
+}
+
+/* For Neptune board: LINK1000 as Link LED and TX as activity LED */
+int dnet_phy_marvell_fixup(struct phy_device *phydev)
+{
+ return phy_write(phydev, 0x18, 0x4148);
+}
+
+static void dnet_update_stats(struct dnet *bp)
+{
+ u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT;
+ u32 *p = &bp->hw_stats.rx_pkt_ignr;
+ u32 *end = &bp->hw_stats.rx_byte + 1;
+
+ WARN_ON((unsigned long)(end - p - 1) !=
+ (DNET_RX_BYTE_CNT - DNET_RX_PKT_IGNR_CNT) / 4);
+
+ for (; p < end; p++, reg++)
+ *p += readl(reg);
+
+ reg = bp->regs + DNET_TX_UNICAST_CNT;
+ p = &bp->hw_stats.tx_unicast;
+ end = &bp->hw_stats.tx_byte + 1;
+
+ WARN_ON((unsigned long)(end - p - 1) !=
+ (DNET_TX_BYTE_CNT - DNET_TX_UNICAST_CNT) / 4);
+
+ for (; p < end; p++, reg++)
+ *p += readl(reg);
+}
+
+static int dnet_poll(struct napi_struct *napi, int budget)
+{
+ struct dnet *bp = container_of(napi, struct dnet, napi);
+ struct net_device *dev = bp->dev;
+ int npackets = 0;
+ unsigned int pkt_len;
+ struct sk_buff *skb;
+ unsigned int *data_ptr;
+ u32 int_enable;
+ u32 cmd_word;
+ int i;
+
+ while (npackets < budget) {
+ /*
+ * break out of while loop if there are no more
+ * packets waiting
+ */
+ if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16)) {
+ napi_complete(napi);
+ int_enable = dnet_readl(bp, INTR_ENB);
+ int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF;
+ dnet_writel(bp, int_enable, INTR_ENB);
+ return 0;
+ }
+
+ cmd_word = dnet_readl(bp, RX_LEN_FIFO);
+ pkt_len = cmd_word & 0xFFFF;
+
+ if (cmd_word & 0xDF180000)
+ printk(KERN_ERR "%s packet receive error %x\n",
+ __func__, cmd_word);
+
+ skb = dev_alloc_skb(pkt_len + 5);
+ if (skb != NULL) {
+ /* Align IP on 16 byte boundaries */
+ skb_reserve(skb, 2);
+ /*
+ * 'skb_put()' points to the start of sk_buff
+ * data area.
+ */
+ data_ptr = (unsigned int *)skb_put(skb, pkt_len);
+ for (i = 0; i < (pkt_len + 3) >> 2; i++)
+ *data_ptr++ = dnet_readl(bp, RX_DATA_FIFO);
+ skb->protocol = eth_type_trans(skb, dev);
+ netif_receive_skb(skb);
+ npackets++;
+ } else
+ printk(KERN_NOTICE
+ "%s: No memory to allocate a sk_buff of "
+ "size %u.\n", dev->name, pkt_len);
+ }
+
+ budget -= npackets;
+
+ if (npackets < budget) {
+ /* We processed all packets available. Tell NAPI it can
+ * stop polling then re-enable rx interrupts */
+ napi_complete(napi);
+ int_enable = dnet_readl(bp, INTR_ENB);
+ int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF;
+ dnet_writel(bp, int_enable, INTR_ENB);
+ return 0;
+ }
+
+ /* There are still packets waiting */
+ return 1;
+}
+
+static irqreturn_t dnet_interrupt(int irq, void *dev_id)
+{
+ struct net_device *dev = dev_id;
+ struct dnet *bp = netdev_priv(dev);
+ u32 int_src, int_enable, int_current;
+ unsigned long flags;
+ unsigned int handled = 0;
+
+ spin_lock_irqsave(&bp->lock, flags);
+
+ /* read and clear the DNET irq (clear on read) */
+ int_src = dnet_readl(bp, INTR_SRC);
+ int_enable = dnet_readl(bp, INTR_ENB);
+ int_current = int_src & int_enable;
+
+ /* restart the queue if we had stopped it for TX fifo almost full */
+ if (int_current & DNET_INTR_SRC_TX_FIFOAE) {
+ int_enable = dnet_readl(bp, INTR_ENB);
+ int_enable &= ~DNET_INTR_ENB_TX_FIFOAE;
+ dnet_writel(bp, int_enable, INTR_ENB);
+ netif_wake_queue(dev);
+ handled = 1;
+ }
+
+ /* RX FIFO error checking */
+ if (int_current &
+ (DNET_INTR_SRC_RX_CMDFIFOFF | DNET_INTR_SRC_RX_DATAFIFOFF)) {
+ printk(KERN_ERR "%s: RX fifo error %x, irq %x\n", __func__,
+ dnet_readl(bp, RX_STATUS), int_current);
+ /* we can only flush the RX FIFOs */
+ dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH, SYS_CTL);
+ ndelay(500);
+ dnet_writel(bp, 0, SYS_CTL);
+ handled = 1;
+ }
+
+ /* TX FIFO error checking */
+ if (int_current &
+ (DNET_INTR_SRC_TX_FIFOFULL | DNET_INTR_SRC_TX_DISCFRM)) {
+ printk(KERN_ERR "%s: TX fifo error %x, irq %x\n", __func__,
+ dnet_readl(bp, TX_STATUS), int_current);
+ /* we can only flush the TX FIFOs */
+ dnet_writel(bp, DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL);
+ ndelay(500);
+ dnet_writel(bp, 0, SYS_CTL);
+ handled = 1;
+ }
+
+ if (int_current & DNET_INTR_SRC_RX_CMDFIFOAF) {
+ if (napi_schedule_prep(&bp->napi)) {
+ /*
+ * There's no point taking any more interrupts
+ * until we have processed the buffers
+ */
+ /* Disable Rx interrupts and schedule NAPI poll */
+ int_enable = dnet_readl(bp, INTR_ENB);
+ int_enable &= ~DNET_INTR_SRC_RX_CMDFIFOAF;
+ dnet_writel(bp, int_enable, INTR_ENB);
+ __napi_schedule(&bp->napi);
+ }
+ handled = 1;
+ }
+
+ if (!handled)
+ pr_debug("%s: irq %x remains\n", __func__, int_current);
+
+ spin_unlock_irqrestore(&bp->lock, flags);
+
+ return IRQ_RETVAL(handled);
+}
+
+#ifdef DEBUG
+static inline void dnet_print_skb(struct sk_buff *skb)
+{
+ int k;
+ printk(KERN_DEBUG PFX "data:");
+ for (k = 0; k < skb->len; k++)
+ printk(" %02x", (unsigned int)skb->data[k]);
+ printk("\n");
+}
+#else
+#define dnet_print_skb(skb) do {} while (0)
+#endif
+
+static int dnet_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+
+ struct dnet *bp = netdev_priv(dev);
+ u32 tx_status, irq_enable;
+ unsigned int len, i, tx_cmd, wrsz;
+ unsigned long flags;
+ unsigned int *bufp;
+
+ tx_status = dnet_readl(bp, TX_STATUS);
+
+ pr_debug("start_xmit: len %u head %p data %p\n",
+ skb->len, skb->head, skb->data);
+ dnet_print_skb(skb);
+
+ /* frame size (words) */
+ len = (skb->len + 3) >> 2;
+
+ spin_lock_irqsave(&bp->lock, flags);
+
+ tx_status = dnet_readl(bp, TX_STATUS);
+
+ bufp = (unsigned int *)(((unsigned long) skb->data) & ~0x3UL);
+ wrsz = (u32) skb->len + 3;
+ wrsz += ((unsigned long) skb->data) & 0x3;
+ wrsz >>= 2;
+ tx_cmd = ((((unsigned long)(skb->data)) & 0x03) << 16) | (u32) skb->len;
+
+ /* check if there is enough room for the current frame */
+ if (wrsz < (DNET_FIFO_SIZE - dnet_readl(bp, TX_FIFO_WCNT))) {
+ for (i = 0; i < wrsz; i++)
+ dnet_writel(bp, *bufp++, TX_DATA_FIFO);
+
+ /*
+ * inform MAC that a packet's written and ready to be
+ * shipped out
+ */
+ dnet_writel(bp, tx_cmd, TX_LEN_FIFO);
+ }
+
+ if (dnet_readl(bp, TX_FIFO_WCNT) > DNET_FIFO_TX_DATA_AF_TH) {
+ netif_stop_queue(dev);
+ tx_status = dnet_readl(bp, INTR_SRC);
+ irq_enable = dnet_readl(bp, INTR_ENB);
+ irq_enable |= DNET_INTR_ENB_TX_FIFOAE;
+ dnet_writel(bp, irq_enable, INTR_ENB);
+ }
+
+ /* free the buffer */
+ dev_kfree_skb(skb);
+
+ spin_unlock_irqrestore(&bp->lock, flags);
+
+ dev->trans_start = jiffies;
+
+ return 0;
+}
+
+static void dnet_reset_hw(struct dnet *bp)
+{
+ /* put ts_mac in IDLE state i.e. disable rx/tx */
+ dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, DNET_INTERNAL_MODE_FCEN);
+
+ /*
+ * RX FIFO almost full threshold: only cmd FIFO almost full is
+ * implemented for RX side
+ */
+ dnet_writel(bp, DNET_FIFO_RX_CMD_AF_TH, RX_FIFO_TH);
+ /*
+ * TX FIFO almost empty threshold: only data FIFO almost empty
+ * is implemented for TX side
+ */
+ dnet_writel(bp, DNET_FIFO_TX_DATA_AE_TH, TX_FIFO_TH);
+
+ /* flush rx/tx fifos */
+ dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
+ SYS_CTL);
+ msleep(1);
+ dnet_writel(bp, 0, SYS_CTL);
+}
+
+static void dnet_init_hw(struct dnet *bp)
+{
+ u32 config;
+
+ dnet_reset_hw(bp);
+ __dnet_set_hwaddr(bp);
+
+ config = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
+
+ if (bp->dev->flags & IFF_PROMISC)
+ /* Copy All Frames */
+ config |= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC;
+ if (!(bp->dev->flags & IFF_BROADCAST))
+ /* No BroadCast */
+ config |= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST;
+
+ config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
+ DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
+ DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
+ DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
+
+ dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, config);
+
+ /* clear irq before enabling them */
+ config = dnet_readl(bp, INTR_SRC);
+
+ /* enable RX/TX interrupt, recv packet ready interrupt */
+ dnet_writel(bp, DNET_INTR_ENB_GLOBAL_ENABLE | DNET_INTR_ENB_RX_SUMMARY |
+ DNET_INTR_ENB_TX_SUMMARY | DNET_INTR_ENB_RX_FIFOERR |
+ DNET_INTR_ENB_RX_ERROR | DNET_INTR_ENB_RX_FIFOFULL |
+ DNET_INTR_ENB_TX_FIFOFULL | DNET_INTR_ENB_TX_DISCFRM |
+ DNET_INTR_ENB_RX_PKTRDY, INTR_ENB);
+}
+
+static int dnet_open(struct net_device *dev)
+{
+ struct dnet *bp = netdev_priv(dev);
+
+ /* if the phy is not yet register, retry later */
+ if (!bp->phy_dev)
+ return -EAGAIN;
+
+ if (!is_valid_ether_addr(dev->dev_addr))
+ return -EADDRNOTAVAIL;
+
+ napi_enable(&bp->napi);
+ dnet_init_hw(bp);
+
+ phy_start_aneg(bp->phy_dev);
+
+ /* schedule a link state check */
+ phy_start(bp->phy_dev);
+
+ netif_start_queue(dev);
+
+ return 0;
+}
+
+static int dnet_close(struct net_device *dev)
+{
+ struct dnet *bp = netdev_priv(dev);
+
+ netif_stop_queue(dev);
+ napi_disable(&bp->napi);
+
+ if (bp->phy_dev)
+ phy_stop(bp->phy_dev);
+
+ dnet_reset_hw(bp);
+ netif_carrier_off(dev);
+
+ return 0;
+}
+
+static inline void dnet_print_pretty_hwstats(struct dnet_stats *hwstat)
+{
+ pr_debug("%s\n", __func__);
+ pr_debug("----------------------------- RX statistics "
+ "-------------------------------\n");
+ pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat->rx_pkt_ignr);
+ pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat->rx_len_chk_err);
+ pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat->rx_lng_frm);
+ pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat->rx_shrt_frm);
+ pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat->rx_ipg_viol);
+ pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat->rx_crc_err);
+ pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat->rx_ok_pkt);
+ pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat->rx_ctl_frm);
+ pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat->rx_pause_frm);
+ pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat->rx_multicast);
+ pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat->rx_broadcast);
+ pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat->rx_vlan_tag);
+ pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat->rx_pre_shrink);
+ pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat->rx_drib_nib);
+ pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat->rx_unsup_opcd);
+ pr_debug("RX_BYTE_CNT %-8x\n", hwstat->rx_byte);
+ pr_debug("----------------------------- TX statistics "
+ "-------------------------------\n");
+ pr_debug("TX_UNICAST_CNT %-8x\n", hwstat->tx_unicast);
+ pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat->tx_pause_frm);
+ pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat->tx_multicast);
+ pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat->tx_brdcast);
+ pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat->tx_vlan_tag);
+ pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat->tx_bad_fcs);
+ pr_debug("TX_JUMBO_CNT %-8x\n", hwstat->tx_jumbo);
+ pr_debug("TX_BYTE_CNT %-8x\n", hwstat->tx_byte);
+}
+
+static struct net_device_stats *dnet_get_stats(struct net_device *dev)
+{
+
+ struct dnet *bp = netdev_priv(dev);
+ struct net_device_stats *nstat = &dev->stats;
+ struct dnet_stats *hwstat = &bp->hw_stats;
+
+ /* read stats from hardware */
+ dnet_update_stats(bp);
+
+ /* Convert HW stats into netdevice stats */
+ nstat->rx_errors = (hwstat->rx_len_chk_err +
+ hwstat->rx_lng_frm + hwstat->rx_shrt_frm +
+ /* ignore IGP violation error
+ hwstat->rx_ipg_viol + */
+ hwstat->rx_crc_err +
+ hwstat->rx_pre_shrink +
+ hwstat->rx_drib_nib + hwstat->rx_unsup_opcd);
+ nstat->tx_errors = hwstat->tx_bad_fcs;
+ nstat->rx_length_errors = (hwstat->rx_len_chk_err +
+ hwstat->rx_lng_frm +
+ hwstat->rx_shrt_frm + hwstat->rx_pre_shrink);
+ nstat->rx_crc_errors = hwstat->rx_crc_err;
+ nstat->rx_frame_errors = hwstat->rx_pre_shrink + hwstat->rx_drib_nib;
+ nstat->rx_packets = hwstat->rx_ok_pkt;
+ nstat->tx_packets = (hwstat->tx_unicast +
+ hwstat->tx_multicast + hwstat->tx_brdcast);
+ nstat->rx_bytes = hwstat->rx_byte;
+ nstat->tx_bytes = hwstat->tx_byte;
+ nstat->multicast = hwstat->rx_multicast;
+ nstat->rx_missed_errors = hwstat->rx_pkt_ignr;
+
+ dnet_print_pretty_hwstats(hwstat);
+
+ return nstat;
+}
+
+static int dnet_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+ struct dnet *bp = netdev_priv(dev);
+ struct phy_device *phydev = bp->phy_dev;
+
+ if (!phydev)
+ return -ENODEV;
+
+ return phy_ethtool_gset(phydev, cmd);
+}
+
+static int dnet_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+ struct dnet *bp = netdev_priv(dev);
+ struct phy_device *phydev = bp->phy_dev;
+
+ if (!phydev)
+ return -ENODEV;
+
+ return phy_ethtool_sset(phydev, cmd);
+}
+
+static int dnet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+ struct dnet *bp = netdev_priv(dev);
+ struct phy_device *phydev = bp->phy_dev;
+
+ if (!netif_running(dev))
+ return -EINVAL;
+
+ if (!phydev)
+ return -ENODEV;
+
+ return phy_mii_ioctl(phydev, if_mii(rq), cmd);
+}
+
+static void dnet_get_drvinfo(struct net_device *dev,
+ struct ethtool_drvinfo *info)
+{
+ strcpy(info->driver, DRV_NAME);
+ strcpy(info->version, DRV_VERSION);
+ strcpy(info->bus_info, "0");
+}
+
+static const struct ethtool_ops dnet_ethtool_ops = {
+ .get_settings = dnet_get_settings,
+ .set_settings = dnet_set_settings,
+ .get_drvinfo = dnet_get_drvinfo,
+ .get_link = ethtool_op_get_link,
+};
+
+static const struct net_device_ops dnet_netdev_ops = {
+ .ndo_open = dnet_open,
+ .ndo_stop = dnet_close,
+ .ndo_get_stats = dnet_get_stats,
+ .ndo_start_xmit = dnet_start_xmit,
+ .ndo_do_ioctl = dnet_ioctl,
+ .ndo_set_mac_address = eth_mac_addr,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_change_mtu = eth_change_mtu,
+};
+
+static int __devinit dnet_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct net_device *dev;
+ struct dnet *bp;
+ struct phy_device *phydev;
+ int err = -ENXIO;
+ unsigned int mem_base, mem_size, irq;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "no mmio resource defined\n");
+ goto err_out;
+ }
+ mem_base = res->start;
+ mem_size = resource_size(res);
+ irq = platform_get_irq(pdev, 0);
+
+ if (!request_mem_region(mem_base, mem_size, DRV_NAME)) {
+ dev_err(&pdev->dev, "no memory region available\n");
+ err = -EBUSY;
+ goto err_out;
+ }
+
+ err = -ENOMEM;
+ dev = alloc_etherdev(sizeof(*bp));
+ if (!dev) {
+ dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
+ goto err_out;
+ }
+
+ /* TODO: Actually, we have some interesting features... */
+ dev->features |= 0;
+
+ bp = netdev_priv(dev);
+ bp->dev = dev;
+
+ SET_NETDEV_DEV(dev, &pdev->dev);
+
+ spin_lock_init(&bp->lock);
+
+ bp->regs = ioremap(mem_base, mem_size);
+ if (!bp->regs) {
+ dev_err(&pdev->dev, "failed to map registers, aborting.\n");
+ err = -ENOMEM;
+ goto err_out_free_dev;
+ }
+
+ dev->irq = irq;
+ err = request_irq(dev->irq, dnet_interrupt, 0, DRV_NAME, dev);
+ if (err) {
+ dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
+ irq, err);
+ goto err_out_iounmap;
+ }
+
+ dev->netdev_ops = &dnet_netdev_ops;
+ netif_napi_add(dev, &bp->napi, dnet_poll, 64);
+ dev->ethtool_ops = &dnet_ethtool_ops;
+
+ dev->base_addr = (unsigned long)bp->regs;
+
+ bp->capabilities = dnet_readl(bp, VERCAPS) & DNET_CAPS_MASK;
+
+ dnet_get_hwaddr(bp);
+
+ if (!is_valid_ether_addr(dev->dev_addr)) {
+ /* choose a random ethernet address */
+ random_ether_addr(dev->dev_addr);
+ __dnet_set_hwaddr(bp);
+ }
+
+ err = register_netdev(dev);
+ if (err) {
+ dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
+ goto err_out_free_irq;
+ }
+
+ /* register the PHY board fixup (for Marvell 88E1111) */
+ err = phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0,
+ dnet_phy_marvell_fixup);
+ /* we can live without it, so just issue a warning */
+ if (err)
+ dev_warn(&pdev->dev, "Cannot register PHY board fixup.\n");
+
+ if (dnet_mii_init(bp) != 0)
+ goto err_out_unregister_netdev;
+
+ dev_info(&pdev->dev, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n",
+ bp->regs, mem_base, dev->irq, dev->dev_addr);
+ dev_info(&pdev->dev, "has %smdio, %sirq, %sgigabit, %sdma \n",
+ (bp->capabilities & DNET_HAS_MDIO) ? "" : "no ",
+ (bp->capabilities & DNET_HAS_IRQ) ? "" : "no ",
+ (bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ",
+ (bp->capabilities & DNET_HAS_DMA) ? "" : "no ");
+ phydev = bp->phy_dev;
+ dev_info(&pdev->dev, "attached PHY driver [%s] "
+ "(mii_bus:phy_addr=%s, irq=%d)\n",
+ phydev->drv->name, phydev->dev.bus_id, phydev->irq);
+
+ return 0;
+
+err_out_unregister_netdev:
+ unregister_netdev(dev);
+err_out_free_irq:
+ free_irq(dev->irq, dev);
+err_out_iounmap:
+ iounmap(bp->regs);
+err_out_free_dev:
+ free_netdev(dev);
+err_out:
+ return err;
+}
+
+static int __devexit dnet_remove(struct platform_device *pdev)
+{
+
+ struct net_device *dev;
+ struct dnet *bp;
+
+ dev = platform_get_drvdata(pdev);
+
+ if (dev) {
+ bp = netdev_priv(dev);
+ if (bp->phy_dev)
+ phy_disconnect(bp->phy_dev);
+ mdiobus_unregister(bp->mii_bus);
+ kfree(bp->mii_bus->irq);
+ mdiobus_free(bp->mii_bus);
+ unregister_netdev(dev);
+ free_irq(dev->irq, dev);
+ iounmap(bp->regs);
+ free_netdev(dev);
+ }
+
+ return 0;
+}
+
+static struct platform_driver dnet_driver = {
+ .probe = dnet_probe,
+ .remove = __devexit_p(dnet_remove),
+ .driver = {
+ .name = "dnet",
+ },
+};
+
+static int __init dnet_init(void)
+{
+ return platform_driver_register(&dnet_driver);
+}
+
+static void __exit dnet_exit(void)
+{
+ platform_driver_unregister(&dnet_driver);
+}
+
+module_init(dnet_init);
+module_exit(dnet_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Dave DNET Ethernet driver");
+MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, "
+ "Matteo Vit <matteo.vit@dave.eu>");
diff --git a/drivers/net/dnet.h b/drivers/net/dnet.h
new file mode 100644
index 00000000000..37f5b30fa78
--- /dev/null
+++ b/drivers/net/dnet.h
@@ -0,0 +1,225 @@
+/*
+ * Dave DNET Ethernet Controller driver
+ *
+ * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _DNET_H
+#define _DNET_H
+
+#define DRV_NAME "dnet"
+#define DRV_VERSION "0.9.1"
+#define PFX DRV_NAME ": "
+
+/* Register access macros */
+#define dnet_writel(port, value, reg) \
+ writel((value), (port)->regs + DNET_##reg)
+#define dnet_readl(port, reg) readl((port)->regs + DNET_##reg)
+
+/* ALL DNET FIFO REGISTERS */
+#define DNET_RX_LEN_FIFO 0x000 /* RX_LEN_FIFO */
+#define DNET_RX_DATA_FIFO 0x004 /* RX_DATA_FIFO */
+#define DNET_TX_LEN_FIFO 0x008 /* TX_LEN_FIFO */
+#define DNET_TX_DATA_FIFO 0x00C /* TX_DATA_FIFO */
+
+/* ALL DNET CONTROL/STATUS REGISTERS OFFSETS */
+#define DNET_VERCAPS 0x100 /* VERCAPS */
+#define DNET_INTR_SRC 0x104 /* INTR_SRC */
+#define DNET_INTR_ENB 0x108 /* INTR_ENB */
+#define DNET_RX_STATUS 0x10C /* RX_STATUS */
+#define DNET_TX_STATUS 0x110 /* TX_STATUS */
+#define DNET_RX_FRAMES_CNT 0x114 /* RX_FRAMES_CNT */
+#define DNET_TX_FRAMES_CNT 0x118 /* TX_FRAMES_CNT */
+#define DNET_RX_FIFO_TH 0x11C /* RX_FIFO_TH */
+#define DNET_TX_FIFO_TH 0x120 /* TX_FIFO_TH */
+#define DNET_SYS_CTL 0x124 /* SYS_CTL */
+#define DNET_PAUSE_TMR 0x128 /* PAUSE_TMR */
+#define DNET_RX_FIFO_WCNT 0x12C /* RX_FIFO_WCNT */
+#define DNET_TX_FIFO_WCNT 0x130 /* TX_FIFO_WCNT */
+
+/* ALL DNET MAC REGISTERS */
+#define DNET_MACREG_DATA 0x200 /* Mac-Reg Data */
+#define DNET_MACREG_ADDR 0x204 /* Mac-Reg Addr */
+
+/* ALL DNET RX STATISTICS COUNTERS */
+#define DNET_RX_PKT_IGNR_CNT 0x300
+#define DNET_RX_LEN_CHK_ERR_CNT 0x304
+#define DNET_RX_LNG_FRM_CNT 0x308
+#define DNET_RX_SHRT_FRM_CNT 0x30C
+#define DNET_RX_IPG_VIOL_CNT 0x310
+#define DNET_RX_CRC_ERR_CNT 0x314
+#define DNET_RX_OK_PKT_CNT 0x318
+#define DNET_RX_CTL_FRM_CNT 0x31C
+#define DNET_RX_PAUSE_FRM_CNT 0x320
+#define DNET_RX_MULTICAST_CNT 0x324
+#define DNET_RX_BROADCAST_CNT 0x328
+#define DNET_RX_VLAN_TAG_CNT 0x32C
+#define DNET_RX_PRE_SHRINK_CNT 0x330
+#define DNET_RX_DRIB_NIB_CNT 0x334
+#define DNET_RX_UNSUP_OPCD_CNT 0x338
+#define DNET_RX_BYTE_CNT 0x33C
+
+/* DNET TX STATISTICS COUNTERS */
+#define DNET_TX_UNICAST_CNT 0x400
+#define DNET_TX_PAUSE_FRM_CNT 0x404
+#define DNET_TX_MULTICAST_CNT 0x408
+#define DNET_TX_BRDCAST_CNT 0x40C
+#define DNET_TX_VLAN_TAG_CNT 0x410
+#define DNET_TX_BAD_FCS_CNT 0x414
+#define DNET_TX_JUMBO_CNT 0x418
+#define DNET_TX_BYTE_CNT 0x41C
+
+/* SOME INTERNAL MAC-CORE REGISTER */
+#define DNET_INTERNAL_MODE_REG 0x0
+#define DNET_INTERNAL_RXTX_CONTROL_REG 0x2
+#define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4
+#define DNET_INTERNAL_IGP_REG 0x8
+#define DNET_INTERNAL_MAC_ADDR_0_REG 0xa
+#define DNET_INTERNAL_MAC_ADDR_1_REG 0xc
+#define DNET_INTERNAL_MAC_ADDR_2_REG 0xe
+#define DNET_INTERNAL_TX_RX_STS_REG 0x12
+#define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14
+#define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16
+
+#define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14)
+
+#define DNET_INTERNAL_WRITE (1 << 31)
+
+/* MAC-CORE REGISTER FIELDS */
+
+/* MAC-CORE MODE REGISTER FIELDS */
+#define DNET_INTERNAL_MODE_GBITEN (1 << 0)
+#define DNET_INTERNAL_MODE_FCEN (1 << 1)
+#define DNET_INTERNAL_MODE_RXEN (1 << 2)
+#define DNET_INTERNAL_MODE_TXEN (1 << 3)
+
+/* MAC-CORE RXTX CONTROL REGISTER FIELDS */
+#define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8)
+#define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7)
+#define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4)
+#define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3)
+#define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2)
+#define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1)
+#define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0)
+#define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6)
+#define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5)
+
+/* SYSTEM CONTROL REGISTER FIELDS */
+#define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0)
+#define DNET_SYS_CTL_SENDPAUSE (1 << 2)
+#define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3)
+#define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4)
+
+/* TX STATUS REGISTER FIELDS */
+#define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2)
+#define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1)
+
+/* INTERRUPT SOURCE REGISTER FIELDS */
+#define DNET_INTR_SRC_TX_PKTSENT (1 << 0)
+#define DNET_INTR_SRC_TX_FIFOAF (1 << 1)
+#define DNET_INTR_SRC_TX_FIFOAE (1 << 2)
+#define DNET_INTR_SRC_TX_DISCFRM (1 << 3)
+#define DNET_INTR_SRC_TX_FIFOFULL (1 << 4)
+#define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8)
+#define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9)
+#define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10)
+#define DNET_INTR_SRC_TX_SUMMARY (1 << 16)
+#define DNET_INTR_SRC_RX_SUMMARY (1 << 17)
+#define DNET_INTR_SRC_PHY (1 << 19)
+
+/* INTERRUPT ENABLE REGISTER FIELDS */
+#define DNET_INTR_ENB_TX_PKTSENT (1 << 0)
+#define DNET_INTR_ENB_TX_FIFOAF (1 << 1)
+#define DNET_INTR_ENB_TX_FIFOAE (1 << 2)
+#define DNET_INTR_ENB_TX_DISCFRM (1 << 3)
+#define DNET_INTR_ENB_TX_FIFOFULL (1 << 4)
+#define DNET_INTR_ENB_RX_PKTRDY (1 << 8)
+#define DNET_INTR_ENB_RX_FIFOAF (1 << 9)
+#define DNET_INTR_ENB_RX_FIFOERR (1 << 10)
+#define DNET_INTR_ENB_RX_ERROR (1 << 11)
+#define DNET_INTR_ENB_RX_FIFOFULL (1 << 12)
+#define DNET_INTR_ENB_RX_FIFOAE (1 << 13)
+#define DNET_INTR_ENB_TX_SUMMARY (1 << 16)
+#define DNET_INTR_ENB_RX_SUMMARY (1 << 17)
+#define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18)
+
+/* default values:
+ * almost empty = less than one full sized ethernet frame (no jumbo) inside
+ * the fifo almost full = can write less than one full sized ethernet frame
+ * (no jumbo) inside the fifo
+ */
+#define DNET_CFG_TX_FIFO_FULL_THRES 25
+#define DNET_CFG_RX_FIFO_FULL_THRES 20
+
+/*
+ * Capabilities. Used by the driver to know the capabilities that the ethernet
+ * controller inside the FPGA have.
+ */
+
+#define DNET_HAS_MDIO (1 << 0)
+#define DNET_HAS_IRQ (1 << 1)
+#define DNET_HAS_GIGABIT (1 << 2)
+#define DNET_HAS_DMA (1 << 3)
+
+#define DNET_HAS_MII (1 << 4) /* or GMII */
+#define DNET_HAS_RMII (1 << 5) /* or RGMII */
+
+#define DNET_CAPS_MASK 0xFFFF
+
+#define DNET_FIFO_SIZE 1024 /* 1K x 32 bit */
+#define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */
+#define DNET_FIFO_TX_DATA_AE_TH 384
+
+#define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */
+
+/*
+ * Hardware-collected statistics.
+ */
+struct dnet_stats {
+ u32 rx_pkt_ignr;
+ u32 rx_len_chk_err;
+ u32 rx_lng_frm;
+ u32 rx_shrt_frm;
+ u32 rx_ipg_viol;
+ u32 rx_crc_err;
+ u32 rx_ok_pkt;
+ u32 rx_ctl_frm;
+ u32 rx_pause_frm;
+ u32 rx_multicast;
+ u32 rx_broadcast;
+ u32 rx_vlan_tag;
+ u32 rx_pre_shrink;
+ u32 rx_drib_nib;
+ u32 rx_unsup_opcd;
+ u32 rx_byte;
+ u32 tx_unicast;
+ u32 tx_pause_frm;
+ u32 tx_multicast;
+ u32 tx_brdcast;
+ u32 tx_vlan_tag;
+ u32 tx_bad_fcs;
+ u32 tx_jumbo;
+ u32 tx_byte;
+};
+
+struct dnet {
+ void __iomem *regs;
+ spinlock_t lock;
+ struct platform_device *pdev;
+ struct net_device *dev;
+ struct dnet_stats hw_stats;
+ unsigned int capabilities; /* read from FPGA */
+ struct napi_struct napi;
+
+ /* PHY stuff */
+ struct mii_bus *mii_bus;
+ struct phy_device *phy_dev;
+ unsigned int link;
+ unsigned int speed;
+ unsigned int duplex;
+};
+
+#endif /* _DNET_H */
diff --git a/drivers/net/ibm_newemac/core.c b/drivers/net/ibm_newemac/core.c
index 87a706694fb..6fd7aa61736 100644
--- a/drivers/net/ibm_newemac/core.c
+++ b/drivers/net/ibm_newemac/core.c
@@ -2594,6 +2594,9 @@ static int __devinit emac_init_config(struct emac_instance *dev)
if (of_device_is_compatible(np, "ibm,emac-460ex") ||
of_device_is_compatible(np, "ibm,emac-460gt"))
dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
+ if (of_device_is_compatible(np, "ibm,emac-405ex") ||
+ of_device_is_compatible(np, "ibm,emac-405exr"))
+ dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
} else if (of_device_is_compatible(np, "ibm,emac4")) {
dev->features |= EMAC_FTR_EMAC4;
if (of_device_is_compatible(np, "ibm,emac-440gx"))
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index a50db5398fa..9dd13ad12ce 100644
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -1023,11 +1023,10 @@ static int __devinit igb_probe(struct pci_dev *pdev,
struct net_device *netdev;
struct igb_adapter *adapter;
struct e1000_hw *hw;
- struct pci_dev *us_dev;
const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
unsigned long mmio_start, mmio_len;
- int i, err, pci_using_dac, pos;
- u16 eeprom_data = 0, state = 0;
+ int i, err, pci_using_dac;
+ u16 eeprom_data = 0;
u16 eeprom_apme_mask = IGB_EEPROM_APME;
u32 part_num;
int bars, need_ioport;
@@ -1062,27 +1061,6 @@ static int __devinit igb_probe(struct pci_dev *pdev,
}
}
- /* 82575 requires that the pci-e link partner disable the L0s state */
- switch (pdev->device) {
- case E1000_DEV_ID_82575EB_COPPER:
- case E1000_DEV_ID_82575EB_FIBER_SERDES:
- case E1000_DEV_ID_82575GB_QUAD_COPPER:
- us_dev = pdev->bus->self;
- pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
- if (pos) {
- pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
- &state);
- state &= ~PCIE_LINK_STATE_L0S;
- pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
- state);
- dev_info(&pdev->dev,
- "Disabling ASPM L0s upstream switch port %s\n",
- pci_name(us_dev));
- }
- default:
- break;
- }
-
err = pci_request_selected_regions(pdev, bars, igb_driver_name);
if (err)
goto err_pci_reg;
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index d2f4d5f508b..5d364a96e35 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -3973,6 +3973,7 @@ static const struct net_device_ops ixgbe_netdev_ops = {
.ndo_stop = ixgbe_close,
.ndo_start_xmit = ixgbe_xmit_frame,
.ndo_get_stats = ixgbe_get_stats,
+ .ndo_set_rx_mode = ixgbe_set_rx_mode,
.ndo_set_multicast_list = ixgbe_set_rx_mode,
.ndo_validate_addr = eth_validate_addr,
.ndo_set_mac_address = ixgbe_set_mac,
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index 13f11f402a9..b0bc3bc18e9 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -2030,11 +2030,6 @@ static void port_start(struct mv643xx_eth_private *mp)
}
/*
- * Add configured unicast address to address filter table.
- */
- mv643xx_eth_program_unicast_filter(mp->dev);
-
- /*
* Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
* frames to RX queue #0, and include the pseudo-header when
* calculating receive checksums.
@@ -2047,6 +2042,11 @@ static void port_start(struct mv643xx_eth_private *mp)
wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
/*
+ * Add configured unicast addresses to address filter table.
+ */
+ mv643xx_eth_program_unicast_filter(mp->dev);
+
+ /*
* Enable the receive queues.
*/
for (i = 0; i < mp->rxq_count; i++) {
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h
index f4dd9acb687..1ff066b2281 100644
--- a/drivers/net/netxen/netxen_nic.h
+++ b/drivers/net/netxen/netxen_nic.h
@@ -1595,7 +1595,6 @@ dma_watchdog_wakeup(struct netxen_adapter *adapter)
}
-int netxen_is_flash_supported(struct netxen_adapter *adapter);
int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
extern void netxen_change_ringparam(struct netxen_adapter *adapter);
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index 821cff68b3f..7fea7708810 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -706,28 +706,6 @@ int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
return rc;
}
-int netxen_is_flash_supported(struct netxen_adapter *adapter)
-{
- const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
- int addr, val01, val02, i, j;
-
- /* if the flash size less than 4Mb, make huge war cry and die */
- for (j = 1; j < 4; j++) {
- addr = j * NETXEN_NIC_WINDOW_MARGIN;
- for (i = 0; i < ARRAY_SIZE(locs); i++) {
- if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
- && netxen_rom_fast_read(adapter, (addr + locs[i]),
- &val02) == 0) {
- if (val01 == val02)
- return -1;
- } else
- return -1;
- }
- }
-
- return 0;
-}
-
static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
int size, __le32 * buf)
{
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c
index 13087782ac4..c172b6e24a9 100644
--- a/drivers/net/netxen/netxen_nic_main.c
+++ b/drivers/net/netxen/netxen_nic_main.c
@@ -405,9 +405,6 @@ netxen_read_mac_addr(struct netxen_adapter *adapter)
struct net_device *netdev = adapter->netdev;
struct pci_dev *pdev = adapter->pdev;
- if (netxen_is_flash_supported(adapter) != 0)
- return -EIO;
-
if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
if (netxen_p3_get_mac_addr(adapter, &mac_addr) != 0)
return -EIO;
diff --git a/drivers/net/qlge/qlge.h b/drivers/net/qlge/qlge.h
index e6fdce9206c..aff9c5fec73 100644
--- a/drivers/net/qlge/qlge.h
+++ b/drivers/net/qlge/qlge.h
@@ -927,6 +927,7 @@ struct ib_mac_iocb_rsp {
u8 flags1;
#define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */
#define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */
+#define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */
#define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */
#define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */
#define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */
diff --git a/drivers/net/qlge/qlge_main.c b/drivers/net/qlge/qlge_main.c
index 8ea72dc60f7..91191f761fb 100644
--- a/drivers/net/qlge/qlge_main.c
+++ b/drivers/net/qlge/qlge_main.c
@@ -1436,18 +1436,32 @@ static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
}
- if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
- QPRINTK(qdev, RX_STATUS, ERR,
- "Bad checksum for this %s packet.\n",
- ((ib_mac_rsp->
- flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
- skb->ip_summed = CHECKSUM_NONE;
- } else if (qdev->rx_csum &&
- ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
- ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
- !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
- QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
- skb->ip_summed = CHECKSUM_UNNECESSARY;
+
+ skb->protocol = eth_type_trans(skb, ndev);
+ skb->ip_summed = CHECKSUM_NONE;
+
+ /* If rx checksum is on, and there are no
+ * csum or frame errors.
+ */
+ if (qdev->rx_csum &&
+ !(ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) &&
+ !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
+ /* TCP frame. */
+ if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
+ QPRINTK(qdev, RX_STATUS, DEBUG,
+ "TCP checksum done!\n");
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
+ (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
+ /* Unfragmented ipv4 UDP frame. */
+ struct iphdr *iph = (struct iphdr *) skb->data;
+ if (!(iph->frag_off &
+ cpu_to_be16(IP_MF|IP_OFFSET))) {
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ QPRINTK(qdev, RX_STATUS, DEBUG,
+ "TCP checksum done!\n");
+ }
+ }
}
qdev->stats.rx_packets++;
qdev->stats.rx_bytes += skb->len;
@@ -1927,6 +1941,9 @@ static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
tx_ring = &qdev->tx_ring[tx_ring_idx];
+ if (skb_padto(skb, ETH_ZLEN))
+ return NETDEV_TX_OK;
+
if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
QPRINTK(qdev, TX_QUEUED, INFO,
"%s: shutting down tx queue %d du to lack of resources.\n",
@@ -2970,9 +2987,9 @@ static int ql_adapter_initialize(struct ql_adapter *qdev)
mask = value << 16;
ql_write32(qdev, SYS, mask | value);
- /* Set the default queue. */
- value = NIC_RCV_CFG_DFQ;
- mask = NIC_RCV_CFG_DFQ_MASK;
+ /* Set the default queue, and VLAN behavior. */
+ value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV;
+ mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16);
ql_write32(qdev, NIC_RCV_CFG, (mask | value));
/* Set the MPI interrupt to enabled. */
@@ -3149,6 +3166,11 @@ static int ql_adapter_down(struct ql_adapter *qdev)
ql_tx_ring_clean(qdev);
+ /* Call netif_napi_del() from common point.
+ */
+ for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
+ netif_napi_del(&qdev->rx_ring[i].napi);
+
spin_lock(&qdev->hw_lock);
status = ql_adapter_reset(qdev);
if (status)
@@ -3853,7 +3875,7 @@ static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
{
struct net_device *ndev = pci_get_drvdata(pdev);
struct ql_adapter *qdev = netdev_priv(ndev);
- int err, i;
+ int err;
netif_device_detach(ndev);
@@ -3863,9 +3885,6 @@ static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
return err;
}
- for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
- netif_napi_del(&qdev->rx_ring[i].napi);
-
err = pci_save_state(pdev);
if (err)
return err;
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index b3473401c83..43fedb9eced 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -81,9 +81,9 @@ static const int multicast_filter_limit = 32;
#define RTL8169_TX_TIMEOUT (6*HZ)
#define RTL8169_PHY_TIMEOUT (10*HZ)
-#define RTL_EEPROM_SIG 0x8129
+#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
+#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
#define RTL_EEPROM_SIG_ADDR 0x0000
-#define RTL_EEPROM_MAC_ADDR 0x0007
/* write/read MMIO register */
#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
@@ -293,11 +293,6 @@ enum rtl_register_content {
/* Cfg9346Bits */
Cfg9346_Lock = 0x00,
Cfg9346_Unlock = 0xc0,
- Cfg9346_Program = 0x80, /* Programming mode */
- Cfg9346_EECS = 0x08, /* Chip select */
- Cfg9346_EESK = 0x04, /* Serial data clock */
- Cfg9346_EEDI = 0x02, /* Data input */
- Cfg9346_EEDO = 0x01, /* Data output */
/* rx_mode_bits */
AcceptErr = 0x20,
@@ -310,7 +305,6 @@ enum rtl_register_content {
/* RxConfigBits */
RxCfgFIFOShift = 13,
RxCfgDMAShift = 8,
- RxCfg9356SEL = 6, /* EEPROM type: 0 = 9346, 1 = 9356 */
/* TxConfigBits */
TxInterFrameGapShift = 24,
@@ -1969,108 +1963,6 @@ static const struct net_device_ops rtl8169_netdev_ops = {
};
-/* Delay between EEPROM clock transitions. Force out buffered PCI writes. */
-#define RTL_EEPROM_DELAY() RTL_R8(Cfg9346)
-#define RTL_EEPROM_READ_CMD 6
-
-/* read 16bit word stored in EEPROM. EEPROM is addressed by words. */
-static u16 rtl_eeprom_read(void __iomem *ioaddr, int addr)
-{
- u16 result = 0;
- int cmd, cmd_len, i;
-
- /* check for EEPROM address size (in bits) */
- if (RTL_R32(RxConfig) & (1 << RxCfg9356SEL)) {
- /* EEPROM is 93C56 */
- cmd_len = 3 + 8; /* 3 bits for command id and 8 for address */
- cmd = (RTL_EEPROM_READ_CMD << 8) | (addr & 0xff);
- } else {
- /* EEPROM is 93C46 */
- cmd_len = 3 + 6; /* 3 bits for command id and 6 for address */
- cmd = (RTL_EEPROM_READ_CMD << 6) | (addr & 0x3f);
- }
-
- /* enter programming mode */
- RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS);
- RTL_EEPROM_DELAY();
-
- /* write command and requested address */
- while (cmd_len--) {
- u8 x = Cfg9346_Program | Cfg9346_EECS;
-
- x |= (cmd & (1 << cmd_len)) ? Cfg9346_EEDI : 0;
-
- /* write a bit */
- RTL_W8(Cfg9346, x);
- RTL_EEPROM_DELAY();
-
- /* raise clock */
- RTL_W8(Cfg9346, x | Cfg9346_EESK);
- RTL_EEPROM_DELAY();
- }
-
- /* lower clock */
- RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS);
- RTL_EEPROM_DELAY();
-
- /* read back 16bit value */
- for (i = 16; i > 0; i--) {
- /* raise clock */
- RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS | Cfg9346_EESK);
- RTL_EEPROM_DELAY();
-
- result <<= 1;
- result |= (RTL_R8(Cfg9346) & Cfg9346_EEDO) ? 1 : 0;
-
- /* lower clock */
- RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS);
- RTL_EEPROM_DELAY();
- }
-
- RTL_W8(Cfg9346, Cfg9346_Program);
- /* leave programming mode */
- RTL_W8(Cfg9346, Cfg9346_Lock);
-
- return result;
-}
-
-static void rtl_init_mac_address(struct rtl8169_private *tp,
- void __iomem *ioaddr)
-{
- struct pci_dev *pdev = tp->pci_dev;
- u16 x;
- u8 mac[8];
-
- /* read EEPROM signature */
- x = rtl_eeprom_read(ioaddr, RTL_EEPROM_SIG_ADDR);
-
- if (x != RTL_EEPROM_SIG) {
- dev_info(&pdev->dev, "Missing EEPROM signature: %04x\n", x);
- return;
- }
-
- /* read MAC address */
- x = rtl_eeprom_read(ioaddr, RTL_EEPROM_MAC_ADDR);
- mac[0] = x & 0xff;
- mac[1] = x >> 8;
- x = rtl_eeprom_read(ioaddr, RTL_EEPROM_MAC_ADDR + 1);
- mac[2] = x & 0xff;
- mac[3] = x >> 8;
- x = rtl_eeprom_read(ioaddr, RTL_EEPROM_MAC_ADDR + 2);
- mac[4] = x & 0xff;
- mac[5] = x >> 8;
-
- if (netif_msg_probe(tp)) {
- DECLARE_MAC_BUF(buf);
-
- dev_info(&pdev->dev, "MAC address found in EEPROM: %s\n",
- print_mac(buf, mac));
- }
-
- if (is_valid_ether_addr(mac))
- rtl_rar_set(tp, mac);
-}
-
static int __devinit
rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
@@ -2249,8 +2141,6 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
tp->mmio_addr = ioaddr;
- rtl_init_mac_address(tp, ioaddr);
-
/* Get MAC address */
for (i = 0; i < MAC_ADDR_LEN; i++)
dev->dev_addr[i] = RTL_R8(MAC0 + i);
@@ -3363,13 +3253,6 @@ static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
opts1 |= FirstFrag;
} else {
len = skb->len;
-
- if (unlikely(len < ETH_ZLEN)) {
- if (skb_padto(skb, ETH_ZLEN))
- goto err_update_stats;
- len = ETH_ZLEN;
- }
-
opts1 |= FirstFrag | LastFrag;
tp->tx_skb[entry].skb = skb;
}
@@ -3407,7 +3290,6 @@ out:
err_stop:
netif_stop_queue(dev);
ret = NETDEV_TX_BUSY;
-err_update_stats:
dev->stats.tx_dropped++;
goto out;
}
diff --git a/drivers/net/via-velocity.c b/drivers/net/via-velocity.c
index c5691fdb707..fb53ef872df 100644
--- a/drivers/net/via-velocity.c
+++ b/drivers/net/via-velocity.c
@@ -1838,17 +1838,19 @@ static void velocity_free_tx_buf(struct velocity_info *vptr, struct velocity_td_
{
struct sk_buff *skb = tdinfo->skb;
int i;
+ int pktlen;
/*
* Don't unmap the pre-allocated tx_bufs
*/
if (tdinfo->skb_dma) {
+ pktlen = (skb->len > ETH_ZLEN ? : ETH_ZLEN);
for (i = 0; i < tdinfo->nskb_dma; i++) {
#ifdef VELOCITY_ZERO_COPY_SUPPORT
pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], le16_to_cpu(td->tdesc1.len), PCI_DMA_TODEVICE);
#else
- pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], skb->len, PCI_DMA_TODEVICE);
+ pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], pktlen, PCI_DMA_TODEVICE);
#endif
tdinfo->skb_dma[i] = 0;
}
@@ -2080,17 +2082,14 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev)
struct tx_desc *td_ptr;
struct velocity_td_info *tdinfo;
unsigned long flags;
- int pktlen = skb->len;
+ int pktlen;
__le16 len;
int index;
-
- if (skb->len < ETH_ZLEN) {
- if (skb_padto(skb, ETH_ZLEN))
- goto out;
- pktlen = ETH_ZLEN;
- }
+ if (skb_padto(skb, ETH_ZLEN))
+ goto out;
+ pktlen = max_t(unsigned int, skb->len, ETH_ZLEN);
len = cpu_to_le16(pktlen);
diff --git a/drivers/parisc/dino.c b/drivers/parisc/dino.c
index d539d9df88e..bb5a1c9597c 100644
--- a/drivers/parisc/dino.c
+++ b/drivers/parisc/dino.c
@@ -479,7 +479,7 @@ dino_card_setup(struct pci_bus *bus, void __iomem *base_addr)
res = &dino_dev->hba.lmmio_space;
res->flags = IORESOURCE_MEM;
size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)",
- bus->bridge->bus_id);
+ dev_name(bus->bridge));
res->name = kmalloc(size+1, GFP_KERNEL);
if(res->name)
strcpy((char *)res->name, name);
@@ -493,7 +493,7 @@ dino_card_setup(struct pci_bus *bus, void __iomem *base_addr)
struct list_head *ln, *tmp_ln;
printk(KERN_ERR "Dino: cannot attach bus %s\n",
- bus->bridge->bus_id);
+ dev_name(bus->bridge));
/* kill the bus, we can't do anything with it */
list_for_each_safe(ln, tmp_ln, &bus->devices) {
struct pci_dev *dev = pci_dev_b(ln);
@@ -587,7 +587,7 @@ dino_fixup_bus(struct pci_bus *bus)
bus->resource[i+1] = &res[i];
}
- } else if(bus->self) {
+ } else if (bus->parent) {
int i;
pci_read_bridge_bases(bus);
@@ -611,12 +611,12 @@ dino_fixup_bus(struct pci_bus *bus)
}
DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n",
- bus->self->dev.bus_id, i,
+ dev_name(&bus->self->dev), i,
bus->self->resource[i].start,
bus->self->resource[i].end);
pci_assign_resource(bus->self, i);
DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n",
- bus->self->dev.bus_id, i,
+ dev_name(&bus->self->dev), i,
bus->self->resource[i].start,
bus->self->resource[i].end);
}
@@ -1026,7 +1026,8 @@ static int __init dino_probe(struct parisc_device *dev)
dino_current_bus = bus->subordinate + 1;
pci_bus_assign_resources(bus);
} else {
- printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (probably duplicate bus number %d)\n", dev->dev.bus_id, dino_current_bus);
+ printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (probably duplicate bus number %d)\n",
+ dev_name(&dev->dev), dino_current_bus);
/* increment the bus number in case of duplicates */
dino_current_bus++;
}
diff --git a/drivers/parisc/gsc.c b/drivers/parisc/gsc.c
index e76db9e4d50..d3363291769 100644
--- a/drivers/parisc/gsc.c
+++ b/drivers/parisc/gsc.c
@@ -186,29 +186,34 @@ void gsc_asic_assign_irq(struct gsc_asic *asic, int local_irq, int *irqp)
*irqp = irq;
}
-static struct device *next_device(struct klist_iter *i)
+struct gsc_fixup_struct {
+ void (*choose_irq)(struct parisc_device *, void *);
+ void *ctrl;
+};
+
+static int gsc_fixup_irqs_callback(struct device *dev, void *data)
{
- struct klist_node * n = klist_next(i);
- return n ? container_of(n, struct device, knode_parent) : NULL;
+ struct parisc_device *padev = to_parisc_device(dev);
+ struct gsc_fixup_struct *gf = data;
+
+ /* work-around for 715/64 and others which have parent
+ at path [5] and children at path [5/0/x] */
+ if (padev->id.hw_type == HPHW_FAULTY)
+ gsc_fixup_irqs(padev, gf->ctrl, gf->choose_irq);
+ gf->choose_irq(padev, gf->ctrl);
+
+ return 0;
}
void gsc_fixup_irqs(struct parisc_device *parent, void *ctrl,
void (*choose_irq)(struct parisc_device *, void *))
{
- struct device *dev;
- struct klist_iter i;
-
- klist_iter_init(&parent->dev.klist_children, &i);
- while ((dev = next_device(&i))) {
- struct parisc_device *padev = to_parisc_device(dev);
-
- /* work-around for 715/64 and others which have parent
- at path [5] and children at path [5/0/x] */
- if (padev->id.hw_type == HPHW_FAULTY)
- return gsc_fixup_irqs(padev, ctrl, choose_irq);
- choose_irq(padev, ctrl);
- }
- klist_iter_exit(&i);
+ struct gsc_fixup_struct data = {
+ .choose_irq = choose_irq,
+ .ctrl = ctrl,
+ };
+
+ device_for_each_child(&parent->dev, &data, gsc_fixup_irqs_callback);
}
int gsc_common_setup(struct parisc_device *parent, struct gsc_asic *gsc_asic)
diff --git a/drivers/parisc/iosapic.c b/drivers/parisc/iosapic.c
index 0797659ee01..501aaf1f253 100644
--- a/drivers/parisc/iosapic.c
+++ b/drivers/parisc/iosapic.c
@@ -487,7 +487,7 @@ iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev)
}
/* Check if pcidev behind a PPB */
- if (NULL != pcidev->bus->self) {
+ if (pcidev->bus->parent) {
/* Convert pcidev INTR_PIN into something we
** can lookup in the IRT.
*/
@@ -523,10 +523,9 @@ iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev)
#endif /* PCI_BRIDGE_FUNCS */
/*
- ** Locate the host slot the PPB nearest the Host bus
- ** adapter.
- */
- while (NULL != p->parent->self)
+ * Locate the host slot of the PPB.
+ */
+ while (p->parent->parent)
p = p->parent;
intr_slot = PCI_SLOT(p->self->devfn);
@@ -709,11 +708,14 @@ static void iosapic_set_affinity_irq(unsigned int irq,
struct vector_info *vi = iosapic_get_vector(irq);
u32 d0, d1, dummy_d0;
unsigned long flags;
+ int dest_cpu;
- if (cpu_check_affinity(irq, dest))
+ dest_cpu = cpu_check_affinity(irq, dest);
+ if (dest_cpu < 0)
return;
- vi->txn_addr = txn_affinity_addr(irq, cpumask_first(dest));
+ irq_desc[irq].affinity = cpumask_of_cpu(dest_cpu);
+ vi->txn_addr = txn_affinity_addr(irq, dest_cpu);
spin_lock_irqsave(&iosapic_lock, flags);
/* d1 contains the destination CPU, so only want to set that
diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c
index d8233de8c75..59fbbf12836 100644
--- a/drivers/parisc/lba_pci.c
+++ b/drivers/parisc/lba_pci.c
@@ -644,7 +644,7 @@ lba_fixup_bus(struct pci_bus *bus)
** Properly Setup MMIO resources for this bus.
** pci_alloc_primary_bus() mangles this.
*/
- if (bus->self) {
+ if (bus->parent) {
int i;
/* PCI-PCI Bridge */
pci_read_bridge_bases(bus);
@@ -802,7 +802,7 @@ lba_fixup_bus(struct pci_bus *bus)
** Can't fixup here anyway....garr...
*/
if (fbb_enable) {
- if (bus->self) {
+ if (bus->parent) {
u8 control;
/* enable on PPB */
(void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
diff --git a/drivers/parisc/sba_iommu.c b/drivers/parisc/sba_iommu.c
index a70cf16ee1a..e5999c4cedc 100644
--- a/drivers/parisc/sba_iommu.c
+++ b/drivers/parisc/sba_iommu.c
@@ -1206,30 +1206,48 @@ sba_alloc_pdir(unsigned int pdir_size)
return (void *) pdir_base;
}
-static struct device *next_device(struct klist_iter *i)
+struct ibase_data_struct {
+ struct ioc *ioc;
+ int ioc_num;
+};
+
+static int setup_ibase_imask_callback(struct device *dev, void *data)
{
- struct klist_node * n = klist_next(i);
- return n ? container_of(n, struct device, knode_parent) : NULL;
+ /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
+ extern void lba_set_iregs(struct parisc_device *, u32, u32);
+ struct parisc_device *lba = to_parisc_device(dev);
+ struct ibase_data_struct *ibd = data;
+ int rope_num = (lba->hpa.start >> 13) & 0xf;
+ if (rope_num >> 3 == ibd->ioc_num)
+ lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask);
+ return 0;
}
/* setup Mercury or Elroy IBASE/IMASK registers. */
static void
setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
{
- /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
- extern void lba_set_iregs(struct parisc_device *, u32, u32);
- struct device *dev;
- struct klist_iter i;
-
- klist_iter_init(&sba->dev.klist_children, &i);
- while ((dev = next_device(&i))) {
- struct parisc_device *lba = to_parisc_device(dev);
- int rope_num = (lba->hpa.start >> 13) & 0xf;
- if (rope_num >> 3 == ioc_num)
- lba_set_iregs(lba, ioc->ibase, ioc->imask);
- }
- klist_iter_exit(&i);
+ struct ibase_data_struct ibase_data = {
+ .ioc = ioc,
+ .ioc_num = ioc_num,
+ };
+
+ device_for_each_child(&sba->dev, &ibase_data,
+ setup_ibase_imask_callback);
+}
+
+#ifdef SBA_AGP_SUPPORT
+static int
+sba_ioc_find_quicksilver(struct device *dev, void *data)
+{
+ int *agp_found = data;
+ struct parisc_device *lba = to_parisc_device(dev);
+
+ if (IS_QUICKSILVER(lba))
+ *agp_found = 1;
+ return 0;
}
+#endif
static void
sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
@@ -1332,9 +1350,6 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
#ifdef SBA_AGP_SUPPORT
-{
- struct klist_iter i;
- struct device *dev = NULL;
/*
** If an AGP device is present, only use half of the IOV space
@@ -1344,13 +1359,7 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
** We program the next pdir index after we stop w/ a key for
** the GART code to handshake on.
*/
- klist_iter_init(&sba->dev.klist_children, &i);
- while ((dev = next_device(&i))) {
- struct parisc_device *lba = to_parisc_device(dev);
- if (IS_QUICKSILVER(lba))
- agp_found = 1;
- }
- klist_iter_exit(&i);
+ device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver);
if (agp_found && sba_reserve_agpgart) {
printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
@@ -1358,9 +1367,7 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
ioc->pdir_size /= 2;
ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
}
-}
#endif /*SBA_AGP_SUPPORT*/
-
}
static void
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index b3866ad5022..3608081bc3e 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -15,8 +15,7 @@ menuconfig X86_PLATFORM_DEVICES
if X86_PLATFORM_DEVICES
config ACER_WMI
- tristate "Acer WMI Laptop Extras (EXPERIMENTAL)"
- depends on EXPERIMENTAL
+ tristate "Acer WMI Laptop Extras"
depends on ACPI
depends on LEDS_CLASS
depends on NEW_LEDS
@@ -39,9 +38,9 @@ config ASUS_LAPTOP
tristate "Asus Laptop Extras (EXPERIMENTAL)"
depends on ACPI
depends on EXPERIMENTAL && !ACPI_ASUS
- depends on LEDS_CLASS
- depends on NEW_LEDS
- depends on BACKLIGHT_CLASS_DEVICE
+ select LEDS_CLASS
+ select NEW_LEDS
+ select BACKLIGHT_CLASS_DEVICE
depends on INPUT
---help---
This is the new Linux driver for Asus laptops. It may also support some
@@ -185,11 +184,11 @@ config SONYPI_COMPAT
config THINKPAD_ACPI
tristate "ThinkPad ACPI Laptop Extras"
depends on ACPI
+ depends on INPUT
select BACKLIGHT_LCD_SUPPORT
select BACKLIGHT_CLASS_DEVICE
select HWMON
select NVRAM
- select INPUT
select NEW_LEDS
select LEDS_CLASS
select NET
@@ -315,9 +314,8 @@ config EEEPC_LAPTOP
config ACPI_WMI
- tristate "WMI (EXPERIMENTAL)"
+ tristate "WMI"
depends on ACPI
- depends on EXPERIMENTAL
help
This driver adds support for the ACPI-WMI (Windows Management
Instrumentation) mapper device (PNP0C14) found on some systems.
diff --git a/drivers/platform/x86/acer-wmi.c b/drivers/platform/x86/acer-wmi.c
index 6bcca616a70..a6a42e8c060 100644
--- a/drivers/platform/x86/acer-wmi.c
+++ b/drivers/platform/x86/acer-wmi.c
@@ -1026,7 +1026,7 @@ static void acer_rfkill_exit(void)
kfree(wireless_rfkill->data);
rfkill_unregister(wireless_rfkill);
if (has_cap(ACER_CAP_BLUETOOTH)) {
- kfree(wireless_rfkill->data);
+ kfree(bluetooth_rfkill->data);
rfkill_unregister(bluetooth_rfkill);
}
return;
diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c
index 56af6cf385b..eeafc6c0160 100644
--- a/drivers/platform/x86/asus-laptop.c
+++ b/drivers/platform/x86/asus-laptop.c
@@ -815,6 +815,7 @@ static int asus_setkeycode(struct input_dev *dev, int scancode, int keycode)
static void asus_hotk_notify(acpi_handle handle, u32 event, void *data)
{
static struct key_entry *key;
+ u16 count;
/* TODO Find a better way to handle events count. */
if (!hotk)
@@ -832,9 +833,11 @@ static void asus_hotk_notify(acpi_handle handle, u32 event, void *data)
lcd_blank(FB_BLANK_POWERDOWN);
}
+ count = hotk->event_count[event % 128]++;
+ acpi_bus_generate_proc_event(hotk->device, event, count);
acpi_bus_generate_netlink_event(hotk->device->pnp.device_class,
dev_name(&hotk->device->dev), event,
- hotk->event_count[event % 128]++);
+ count);
if (hotk->inputdev) {
key = asus_get_entry_by_scancode(event);
diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c
index 786ed8661cb..6f54fd1757c 100644
--- a/drivers/platform/x86/eeepc-laptop.c
+++ b/drivers/platform/x86/eeepc-laptop.c
@@ -557,13 +557,17 @@ static void eeepc_rfkill_notify(acpi_handle handle, u32 event, void *data)
static void eeepc_hotk_notify(acpi_handle handle, u32 event, void *data)
{
static struct key_entry *key;
+ u16 count;
+
if (!ehotk)
return;
if (event >= NOTIFY_BRN_MIN && event <= NOTIFY_BRN_MAX)
notify_brn();
+ count = ehotk->event_count[event % 128]++;
+ acpi_bus_generate_proc_event(ehotk->device, event, count);
acpi_bus_generate_netlink_event(ehotk->device->pnp.device_class,
dev_name(&ehotk->device->dev), event,
- ehotk->event_count[event % 128]++);
+ count);
if (ehotk->inputdev) {
key = eepc_get_entry_by_scancode(event);
if (key) {
diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c
index bcbc05107ba..d2433204a40 100644
--- a/drivers/platform/x86/thinkpad_acpi.c
+++ b/drivers/platform/x86/thinkpad_acpi.c
@@ -7532,7 +7532,7 @@ MODULE_ALIAS(TPACPI_DRVR_SHORTNAME);
* if it is not there yet.
*/
#define IBM_BIOS_MODULE_ALIAS(__type) \
- MODULE_ALIAS("dmi:bvnIBM:bvr" __type "ET??WW")
+ MODULE_ALIAS("dmi:bvnIBM:bvr" __type "ET??WW*")
/* Non-ancient thinkpads */
MODULE_ALIAS("dmi:bvnIBM:*:svnIBM:*:pvrThinkPad*:rvnIBM:*");
@@ -7541,9 +7541,9 @@ MODULE_ALIAS("dmi:bvnLENOVO:*:svnLENOVO:*:pvrThinkPad*:rvnLENOVO:*");
/* Ancient thinkpad BIOSes have to be identified by
* BIOS type or model number, and there are far less
* BIOS types than model numbers... */
-IBM_BIOS_MODULE_ALIAS("I[B,D,H,I,M,N,O,T,W,V,Y,Z]");
-IBM_BIOS_MODULE_ALIAS("1[0,3,6,8,A-G,I,K,M-P,S,T]");
-IBM_BIOS_MODULE_ALIAS("K[U,X-Z]");
+IBM_BIOS_MODULE_ALIAS("I[BDHIMNOTWVYZ]");
+IBM_BIOS_MODULE_ALIAS("1[0368A-GIKM-PST]");
+IBM_BIOS_MODULE_ALIAS("K[UX-Z]");
MODULE_AUTHOR("Borislav Deianov, Henrique de Moraes Holschuh");
MODULE_DESCRIPTION(TPACPI_DESC);
diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c
index 8a8b377712c..2f269e117b8 100644
--- a/drivers/platform/x86/wmi.c
+++ b/drivers/platform/x86/wmi.c
@@ -708,7 +708,7 @@ static int __init acpi_wmi_add(struct acpi_device *device)
static int __init acpi_wmi_init(void)
{
- acpi_status result;
+ int result;
INIT_LIST_HEAD(&wmi_blocks.list);
diff --git a/drivers/scsi/fcoe/fc_transport_fcoe.c b/drivers/scsi/fcoe/fc_transport_fcoe.c
index bf7fe6fc082..8862758006c 100644
--- a/drivers/scsi/fcoe/fc_transport_fcoe.c
+++ b/drivers/scsi/fcoe/fc_transport_fcoe.c
@@ -33,19 +33,19 @@ static LIST_HEAD(fcoe_transports);
static DEFINE_MUTEX(fcoe_transports_lock);
/**
- * fcoe_transport_default - returns ptr to the default transport fcoe_sw
- **/
+ * fcoe_transport_default() - Returns ptr to the default transport fcoe_sw
+ */
struct fcoe_transport *fcoe_transport_default(void)
{
return &fcoe_sw_transport;
}
/**
- * fcoe_transport_to_pcidev - get the pci dev from a netdev
+ * fcoe_transport_to_pcidev() - get the pci dev from a netdev
* @netdev: the netdev that pci dev will be retrived from
*
* Returns: NULL or the corrsponding pci_dev
- **/
+ */
struct pci_dev *fcoe_transport_pcidev(const struct net_device *netdev)
{
if (!netdev->dev.parent)
@@ -54,18 +54,17 @@ struct pci_dev *fcoe_transport_pcidev(const struct net_device *netdev)
}
/**
- * fcoe_transport_device_lookup - find out netdev is managed by the
- * transport
- * assign a transport to a device
+ * fcoe_transport_device_lookup() - Lookup a transport
* @netdev: the netdev the transport to be attached to
*
* This will look for existing offload driver, if not found, it falls back to
* the default sw hba (fcoe_sw) as its fcoe transport.
*
* Returns: 0 for success
- **/
-static struct fcoe_transport_internal *fcoe_transport_device_lookup(
- struct fcoe_transport *t, struct net_device *netdev)
+ */
+static struct fcoe_transport_internal *
+fcoe_transport_device_lookup(struct fcoe_transport *t,
+ struct net_device *netdev)
{
struct fcoe_transport_internal *ti;
@@ -81,14 +80,14 @@ static struct fcoe_transport_internal *fcoe_transport_device_lookup(
return NULL;
}
/**
- * fcoe_transport_device_add - assign a transport to a device
+ * fcoe_transport_device_add() - Assign a transport to a device
* @netdev: the netdev the transport to be attached to
*
* This will look for existing offload driver, if not found, it falls back to
* the default sw hba (fcoe_sw) as its fcoe transport.
*
* Returns: 0 for success
- **/
+ */
static int fcoe_transport_device_add(struct fcoe_transport *t,
struct net_device *netdev)
{
@@ -123,14 +122,14 @@ static int fcoe_transport_device_add(struct fcoe_transport *t,
}
/**
- * fcoe_transport_device_remove - remove a device from its transport
+ * fcoe_transport_device_remove() - Remove a device from its transport
* @netdev: the netdev the transport to be attached to
*
- * this removes the device from the transport so the given transport will
+ * This removes the device from the transport so the given transport will
* not manage this device any more
*
* Returns: 0 for success
- **/
+ */
static int fcoe_transport_device_remove(struct fcoe_transport *t,
struct net_device *netdev)
{
@@ -155,13 +154,13 @@ static int fcoe_transport_device_remove(struct fcoe_transport *t,
}
/**
- * fcoe_transport_device_remove_all - remove all from transport devlist
+ * fcoe_transport_device_remove_all() - Remove all from transport devlist
*
- * this removes the device from the transport so the given transport will
+ * This removes the device from the transport so the given transport will
* not manage this device any more
*
* Returns: 0 for success
- **/
+ */
static void fcoe_transport_device_remove_all(struct fcoe_transport *t)
{
struct fcoe_transport_internal *ti, *tmp;
@@ -175,18 +174,18 @@ static void fcoe_transport_device_remove_all(struct fcoe_transport *t)
}
/**
- * fcoe_transport_match - use the bus device match function to match the hw
- * @t: the fcoe transport
- * @netdev:
+ * fcoe_transport_match() - Use the bus device match function to match the hw
+ * @t: The fcoe transport to check
+ * @netdev: The netdev to match against
*
- * This function is used to check if the givne transport wants to manage the
+ * This function is used to check if the given transport wants to manage the
* input netdev. if the transports implements the match function, it will be
* called, o.w. we just compare the pci vendor and device id.
*
* Returns: true for match up
- **/
+ */
static bool fcoe_transport_match(struct fcoe_transport *t,
- struct net_device *netdev)
+ struct net_device *netdev)
{
/* match transport by vendor and device id */
struct pci_dev *pci;
@@ -210,17 +209,17 @@ static bool fcoe_transport_match(struct fcoe_transport *t,
}
/**
- * fcoe_transport_lookup - check if the transport is already registered
+ * fcoe_transport_lookup() - Check if the transport is already registered
* @t: the transport to be looked up
*
* This compares the parent device (pci) vendor and device id
*
* Returns: NULL if not found
*
- * TODO - return default sw transport if no other transport is found
- **/
-static struct fcoe_transport *fcoe_transport_lookup(
- struct net_device *netdev)
+ * TODO: return default sw transport if no other transport is found
+ */
+static struct fcoe_transport *
+fcoe_transport_lookup(struct net_device *netdev)
{
struct fcoe_transport *t;
@@ -239,11 +238,11 @@ static struct fcoe_transport *fcoe_transport_lookup(
}
/**
- * fcoe_transport_register - adds a fcoe transport to the fcoe transports list
+ * fcoe_transport_register() - Adds a fcoe transport to the fcoe transports list
* @t: ptr to the fcoe transport to be added
*
* Returns: 0 for success
- **/
+ */
int fcoe_transport_register(struct fcoe_transport *t)
{
struct fcoe_transport *tt;
@@ -259,9 +258,6 @@ int fcoe_transport_register(struct fcoe_transport *t)
list_add_tail(&t->list, &fcoe_transports);
mutex_unlock(&fcoe_transports_lock);
- mutex_init(&t->devlock);
- INIT_LIST_HEAD(&t->devlist);
-
printk(KERN_DEBUG "fcoe_transport_register:%s\n", t->name);
return 0;
@@ -269,11 +265,11 @@ int fcoe_transport_register(struct fcoe_transport *t)
EXPORT_SYMBOL_GPL(fcoe_transport_register);
/**
- * fcoe_transport_unregister - remove the tranport fro the fcoe transports list
+ * fcoe_transport_unregister() - Remove the tranport fro the fcoe transports list
* @t: ptr to the fcoe transport to be removed
*
* Returns: 0 for success
- **/
+ */
int fcoe_transport_unregister(struct fcoe_transport *t)
{
struct fcoe_transport *tt, *tmp;
@@ -294,8 +290,8 @@ int fcoe_transport_unregister(struct fcoe_transport *t)
}
EXPORT_SYMBOL_GPL(fcoe_transport_unregister);
-/*
- * fcoe_load_transport_driver - load an offload driver by alias name
+/**
+ * fcoe_load_transport_driver() - Load an offload driver by alias name
* @netdev: the target net device
*
* Requests for an offload driver module as the fcoe transport, if fails, it
@@ -307,7 +303,7 @@ EXPORT_SYMBOL_GPL(fcoe_transport_unregister);
* 3. pure hw fcoe hba may not have netdev
*
* Returns: 0 for success
- **/
+ */
int fcoe_load_transport_driver(struct net_device *netdev)
{
struct pci_dev *pci;
@@ -335,14 +331,14 @@ int fcoe_load_transport_driver(struct net_device *netdev)
EXPORT_SYMBOL_GPL(fcoe_load_transport_driver);
/**
- * fcoe_transport_attach - load transport to fcoe
+ * fcoe_transport_attach() - Load transport to fcoe
* @netdev: the netdev the transport to be attached to
*
* This will look for existing offload driver, if not found, it falls back to
* the default sw hba (fcoe_sw) as its fcoe transport.
*
* Returns: 0 for success
- **/
+ */
int fcoe_transport_attach(struct net_device *netdev)
{
struct fcoe_transport *t;
@@ -373,11 +369,11 @@ int fcoe_transport_attach(struct net_device *netdev)
EXPORT_SYMBOL_GPL(fcoe_transport_attach);
/**
- * fcoe_transport_release - unload transport from fcoe
+ * fcoe_transport_release() - Unload transport from fcoe
* @netdev: the net device on which fcoe is to be released
*
* Returns: 0 for success
- **/
+ */
int fcoe_transport_release(struct net_device *netdev)
{
struct fcoe_transport *t;
@@ -410,12 +406,12 @@ int fcoe_transport_release(struct net_device *netdev)
EXPORT_SYMBOL_GPL(fcoe_transport_release);
/**
- * fcoe_transport_init - initializes fcoe transport layer
+ * fcoe_transport_init() - Initializes fcoe transport layer
*
* This prepares for the fcoe transport layer
*
* Returns: none
- **/
+ */
int __init fcoe_transport_init(void)
{
INIT_LIST_HEAD(&fcoe_transports);
@@ -424,12 +420,13 @@ int __init fcoe_transport_init(void)
}
/**
- * fcoe_transport_exit - cleans up the fcoe transport layer
+ * fcoe_transport_exit() - Cleans up the fcoe transport layer
+ *
* This cleans up the fcoe transport layer. removing any transport on the list,
* note that the transport destroy func is not called here.
*
* Returns: none
- **/
+ */
int __exit fcoe_transport_exit(void)
{
struct fcoe_transport *t, *tmp;
diff --git a/drivers/scsi/fcoe/fcoe_sw.c b/drivers/scsi/fcoe/fcoe_sw.c
index dc4cd5e2576..da210eba194 100644
--- a/drivers/scsi/fcoe/fcoe_sw.c
+++ b/drivers/scsi/fcoe/fcoe_sw.c
@@ -104,19 +104,19 @@ static struct scsi_host_template fcoe_sw_shost_template = {
.max_sectors = 0xffff,
};
-/*
- * fcoe_sw_lport_config - sets up the fc_lport
+/**
+ * fcoe_sw_lport_config() - sets up the fc_lport
* @lp: ptr to the fc_lport
* @shost: ptr to the parent scsi host
*
* Returns: 0 for success
- *
*/
static int fcoe_sw_lport_config(struct fc_lport *lp)
{
int i = 0;
- lp->link_status = 0;
+ lp->link_up = 0;
+ lp->qfull = 0;
lp->max_retry_count = 3;
lp->e_d_tov = 2 * 1000; /* FC-FS default */
lp->r_a_tov = 2 * 2 * 1000;
@@ -136,16 +136,14 @@ static int fcoe_sw_lport_config(struct fc_lport *lp)
return 0;
}
-/*
- * fcoe_sw_netdev_config - sets up fcoe_softc for lport and network
- * related properties
+/**
+ * fcoe_sw_netdev_config() - Set up netdev for SW FCoE
* @lp : ptr to the fc_lport
* @netdev : ptr to the associated netdevice struct
*
* Must be called after fcoe_sw_lport_config() as it will use lport mutex
*
* Returns : 0 for success
- *
*/
static int fcoe_sw_netdev_config(struct fc_lport *lp, struct net_device *netdev)
{
@@ -181,9 +179,8 @@ static int fcoe_sw_netdev_config(struct fc_lport *lp, struct net_device *netdev)
if (fc_set_mfs(lp, mfs))
return -EINVAL;
- lp->link_status = ~FC_PAUSE & ~FC_LINK_UP;
if (!fcoe_link_ok(lp))
- lp->link_status |= FC_LINK_UP;
+ lp->link_up = 1;
/* offload features support */
if (fc->real_dev->features & NETIF_F_SG)
@@ -191,6 +188,7 @@ static int fcoe_sw_netdev_config(struct fc_lport *lp, struct net_device *netdev)
skb_queue_head_init(&fc->fcoe_pending_queue);
+ fc->fcoe_pending_queue_active = 0;
/* setup Source Mac Address */
memcpy(fc->ctl_src_addr, fc->real_dev->dev_addr,
@@ -224,16 +222,15 @@ static int fcoe_sw_netdev_config(struct fc_lport *lp, struct net_device *netdev)
return 0;
}
-/*
- * fcoe_sw_shost_config - sets up fc_lport->host
+/**
+ * fcoe_sw_shost_config() - Sets up fc_lport->host
* @lp : ptr to the fc_lport
* @shost : ptr to the associated scsi host
* @dev : device associated to scsi host
*
- * Must be called after fcoe_sw_lport_config) and fcoe_sw_netdev_config()
+ * Must be called after fcoe_sw_lport_config() and fcoe_sw_netdev_config()
*
* Returns : 0 for success
- *
*/
static int fcoe_sw_shost_config(struct fc_lport *lp, struct Scsi_Host *shost,
struct device *dev)
@@ -261,8 +258,8 @@ static int fcoe_sw_shost_config(struct fc_lport *lp, struct Scsi_Host *shost,
return 0;
}
-/*
- * fcoe_sw_em_config - allocates em for this lport
+/**
+ * fcoe_sw_em_config() - allocates em for this lport
* @lp: the port that em is to allocated for
*
* Returns : 0 on success
@@ -279,8 +276,8 @@ static inline int fcoe_sw_em_config(struct fc_lport *lp)
return 0;
}
-/*
- * fcoe_sw_destroy - FCoE software HBA tear-down function
+/**
+ * fcoe_sw_destroy() - FCoE software HBA tear-down function
* @netdev: ptr to the associated net_device
*
* Returns: 0 if link is OK for use by FCoE.
@@ -301,7 +298,7 @@ static int fcoe_sw_destroy(struct net_device *netdev)
if (!lp)
return -ENODEV;
- fc = fcoe_softc(lp);
+ fc = lport_priv(lp);
/* Logout of the fabric */
fc_fabric_logoff(lp);
@@ -353,8 +350,8 @@ static struct libfc_function_template fcoe_sw_libfc_fcn_templ = {
.frame_send = fcoe_xmit,
};
-/*
- * fcoe_sw_create - this function creates the fcoe interface
+/**
+ * fcoe_sw_create() - this function creates the fcoe interface
* @netdev: pointer the associated netdevice
*
* Creates fc_lport struct and scsi_host for lport, configures lport
@@ -440,8 +437,8 @@ out_host_put:
return rc;
}
-/*
- * fcoe_sw_match - the fcoe sw transport match function
+/**
+ * fcoe_sw_match() - The FCoE SW transport match function
*
* Returns : false always
*/
@@ -461,8 +458,8 @@ struct fcoe_transport fcoe_sw_transport = {
.device = 0xffff,
};
-/*
- * fcoe_sw_init - registers fcoe_sw_transport
+/**
+ * fcoe_sw_init() - Registers fcoe_sw_transport
*
* Returns : 0 on success
*/
@@ -471,17 +468,22 @@ int __init fcoe_sw_init(void)
/* attach to scsi transport */
scsi_transport_fcoe_sw =
fc_attach_transport(&fcoe_sw_transport_function);
+
if (!scsi_transport_fcoe_sw) {
printk(KERN_ERR "fcoe_sw_init:fc_attach_transport() failed\n");
return -ENODEV;
}
+
+ mutex_init(&fcoe_sw_transport.devlock);
+ INIT_LIST_HEAD(&fcoe_sw_transport.devlist);
+
/* register sw transport */
fcoe_transport_register(&fcoe_sw_transport);
return 0;
}
-/*
- * fcoe_sw_exit - unregisters fcoe_sw_transport
+/**
+ * fcoe_sw_exit() - Unregisters fcoe_sw_transport
*
* Returns : 0 on success
*/
diff --git a/drivers/scsi/fcoe/libfcoe.c b/drivers/scsi/fcoe/libfcoe.c
index e419f486cdb..5548bf3bb58 100644
--- a/drivers/scsi/fcoe/libfcoe.c
+++ b/drivers/scsi/fcoe/libfcoe.c
@@ -49,6 +49,7 @@
static int debug_fcoe;
#define FCOE_MAX_QUEUE_DEPTH 256
+#define FCOE_LOW_QUEUE_DEPTH 32
/* destination address mode */
#define FCOE_GW_ADDR_MODE 0x00
@@ -69,8 +70,6 @@ struct fcoe_percpu_s *fcoe_percpu[NR_CPUS];
/* Function Prototyes */
static int fcoe_check_wait_queue(struct fc_lport *);
-static void fcoe_insert_wait_queue_head(struct fc_lport *, struct sk_buff *);
-static void fcoe_insert_wait_queue(struct fc_lport *, struct sk_buff *);
static void fcoe_recv_flogi(struct fcoe_softc *, struct fc_frame *, u8 *);
#ifdef CONFIG_HOTPLUG_CPU
static int fcoe_cpu_callback(struct notifier_block *, ulong, void *);
@@ -91,13 +90,13 @@ static struct notifier_block fcoe_cpu_notifier = {
};
/**
- * fcoe_create_percpu_data - creates the associated cpu data
+ * fcoe_create_percpu_data() - creates the associated cpu data
* @cpu: index for the cpu where fcoe cpu data will be created
*
* create percpu stats block, from cpu add notifier
*
* Returns: none
- **/
+ */
static void fcoe_create_percpu_data(int cpu)
{
struct fc_lport *lp;
@@ -115,13 +114,13 @@ static void fcoe_create_percpu_data(int cpu)
}
/**
- * fcoe_destroy_percpu_data - destroys the associated cpu data
+ * fcoe_destroy_percpu_data() - destroys the associated cpu data
* @cpu: index for the cpu where fcoe cpu data will destroyed
*
* destroy percpu stats block called by cpu add/remove notifier
*
* Retuns: none
- **/
+ */
static void fcoe_destroy_percpu_data(int cpu)
{
struct fc_lport *lp;
@@ -137,7 +136,7 @@ static void fcoe_destroy_percpu_data(int cpu)
}
/**
- * fcoe_cpu_callback - fcoe cpu hotplug event callback
+ * fcoe_cpu_callback() - fcoe cpu hotplug event callback
* @nfb: callback data block
* @action: event triggering the callback
* @hcpu: index for the cpu of this event
@@ -145,7 +144,7 @@ static void fcoe_destroy_percpu_data(int cpu)
* this creates or destroys per cpu data for fcoe
*
* Returns NOTIFY_OK always.
- **/
+ */
static int fcoe_cpu_callback(struct notifier_block *nfb, unsigned long action,
void *hcpu)
{
@@ -166,7 +165,7 @@ static int fcoe_cpu_callback(struct notifier_block *nfb, unsigned long action,
#endif /* CONFIG_HOTPLUG_CPU */
/**
- * fcoe_rcv - this is the fcoe receive function called by NET_RX_SOFTIRQ
+ * fcoe_rcv() - this is the fcoe receive function called by NET_RX_SOFTIRQ
* @skb: the receive skb
* @dev: associated net device
* @ptype: context
@@ -175,7 +174,7 @@ static int fcoe_cpu_callback(struct notifier_block *nfb, unsigned long action,
* this function will receive the packet and build fc frame and pass it up
*
* Returns: 0 for success
- **/
+ */
int fcoe_rcv(struct sk_buff *skb, struct net_device *dev,
struct packet_type *ptype, struct net_device *olddev)
{
@@ -265,11 +264,11 @@ err2:
EXPORT_SYMBOL_GPL(fcoe_rcv);
/**
- * fcoe_start_io - pass to netdev to start xmit for fcoe
+ * fcoe_start_io() - pass to netdev to start xmit for fcoe
* @skb: the skb to be xmitted
*
* Returns: 0 for success
- **/
+ */
static inline int fcoe_start_io(struct sk_buff *skb)
{
int rc;
@@ -283,12 +282,12 @@ static inline int fcoe_start_io(struct sk_buff *skb)
}
/**
- * fcoe_get_paged_crc_eof - in case we need alloc a page for crc_eof
+ * fcoe_get_paged_crc_eof() - in case we need alloc a page for crc_eof
* @skb: the skb to be xmitted
* @tlen: total len
*
* Returns: 0 for success
- **/
+ */
static int fcoe_get_paged_crc_eof(struct sk_buff *skb, int tlen)
{
struct fcoe_percpu_s *fps;
@@ -326,13 +325,12 @@ static int fcoe_get_paged_crc_eof(struct sk_buff *skb, int tlen)
}
/**
- * fcoe_fc_crc - calculates FC CRC in this fcoe skb
+ * fcoe_fc_crc() - calculates FC CRC in this fcoe skb
* @fp: the fc_frame containg data to be checksummed
*
* This uses crc32() to calculate the crc for fc frame
* Return : 32 bit crc
- *
- **/
+ */
u32 fcoe_fc_crc(struct fc_frame *fp)
{
struct sk_buff *skb = fp_skb(fp);
@@ -363,13 +361,12 @@ u32 fcoe_fc_crc(struct fc_frame *fp)
EXPORT_SYMBOL_GPL(fcoe_fc_crc);
/**
- * fcoe_xmit - FCoE frame transmit function
+ * fcoe_xmit() - FCoE frame transmit function
* @lp: the associated local port
* @fp: the fc_frame to be transmitted
*
* Return : 0 for success
- *
- **/
+ */
int fcoe_xmit(struct fc_lport *lp, struct fc_frame *fp)
{
int wlen, rc = 0;
@@ -389,7 +386,7 @@ int fcoe_xmit(struct fc_lport *lp, struct fc_frame *fp)
WARN_ON((fr_len(fp) % sizeof(u32)) != 0);
- fc = fcoe_softc(lp);
+ fc = lport_priv(lp);
/*
* if it is a flogi then we need to learn gw-addr
* and my own fcid
@@ -439,7 +436,7 @@ int fcoe_xmit(struct fc_lport *lp, struct fc_frame *fp)
if (skb_is_nonlinear(skb)) {
skb_frag_t *frag;
if (fcoe_get_paged_crc_eof(skb, tlen)) {
- kfree(skb);
+ kfree_skb(skb);
return -ENOMEM;
}
frag = &skb_shinfo(skb)->frags[skb_shinfo(skb)->nr_frags - 1];
@@ -502,21 +499,22 @@ int fcoe_xmit(struct fc_lport *lp, struct fc_frame *fp)
rc = fcoe_start_io(skb);
if (rc) {
- fcoe_insert_wait_queue(lp, skb);
+ spin_lock_bh(&fc->fcoe_pending_queue.lock);
+ __skb_queue_tail(&fc->fcoe_pending_queue, skb);
+ spin_unlock_bh(&fc->fcoe_pending_queue.lock);
if (fc->fcoe_pending_queue.qlen > FCOE_MAX_QUEUE_DEPTH)
- fc_pause(lp);
+ lp->qfull = 1;
}
return 0;
}
EXPORT_SYMBOL_GPL(fcoe_xmit);
-/*
- * fcoe_percpu_receive_thread - recv thread per cpu
+/**
+ * fcoe_percpu_receive_thread() - recv thread per cpu
* @arg: ptr to the fcoe per cpu struct
*
* Return: 0 for success
- *
*/
int fcoe_percpu_receive_thread(void *arg)
{
@@ -533,7 +531,7 @@ int fcoe_percpu_receive_thread(void *arg)
struct fcoe_softc *fc;
struct fcoe_hdr *hp;
- set_user_nice(current, 19);
+ set_user_nice(current, -20);
while (!kthread_should_stop()) {
@@ -658,7 +656,7 @@ int fcoe_percpu_receive_thread(void *arg)
}
/**
- * fcoe_recv_flogi - flogi receive function
+ * fcoe_recv_flogi() - flogi receive function
* @fc: associated fcoe_softc
* @fp: the recieved frame
* @sa: the source address of this flogi
@@ -667,7 +665,7 @@ int fcoe_percpu_receive_thread(void *arg)
* mac address for the initiator, eitehr OUI based or GW based.
*
* Returns: none
- **/
+ */
static void fcoe_recv_flogi(struct fcoe_softc *fc, struct fc_frame *fp, u8 *sa)
{
struct fc_frame_header *fh;
@@ -715,32 +713,23 @@ static void fcoe_recv_flogi(struct fcoe_softc *fc, struct fc_frame *fp, u8 *sa)
}
/**
- * fcoe_watchdog - fcoe timer callback
+ * fcoe_watchdog() - fcoe timer callback
* @vp:
*
- * This checks the pending queue length for fcoe and put fcoe to be paused state
+ * This checks the pending queue length for fcoe and set lport qfull
* if the FCOE_MAX_QUEUE_DEPTH is reached. This is done for all fc_lport on the
* fcoe_hostlist.
*
* Returns: 0 for success
- **/
+ */
void fcoe_watchdog(ulong vp)
{
- struct fc_lport *lp;
struct fcoe_softc *fc;
- int paused = 0;
read_lock(&fcoe_hostlist_lock);
list_for_each_entry(fc, &fcoe_hostlist, list) {
- lp = fc->lp;
- if (lp) {
- if (fc->fcoe_pending_queue.qlen > FCOE_MAX_QUEUE_DEPTH)
- paused = 1;
- if (fcoe_check_wait_queue(lp) < FCOE_MAX_QUEUE_DEPTH) {
- if (paused)
- fc_unpause(lp);
- }
- }
+ if (fc->lp)
+ fcoe_check_wait_queue(fc->lp);
}
read_unlock(&fcoe_hostlist_lock);
@@ -750,96 +739,64 @@ void fcoe_watchdog(ulong vp)
/**
- * fcoe_check_wait_queue - put the skb into fcoe pending xmit queue
+ * fcoe_check_wait_queue() - put the skb into fcoe pending xmit queue
* @lp: the fc_port for this skb
* @skb: the associated skb to be xmitted
*
* This empties the wait_queue, dequeue the head of the wait_queue queue
* and calls fcoe_start_io() for each packet, if all skb have been
- * transmitted, return 0 if a error occurs, then restore wait_queue and
- * try again later.
+ * transmitted, return qlen or -1 if a error occurs, then restore
+ * wait_queue and try again later.
*
* The wait_queue is used when the skb transmit fails. skb will go
* in the wait_queue which will be emptied by the time function OR
* by the next skb transmit.
*
* Returns: 0 for success
- **/
+ */
static int fcoe_check_wait_queue(struct fc_lport *lp)
{
- int rc, unpause = 0;
- int paused = 0;
+ struct fcoe_softc *fc = lport_priv(lp);
struct sk_buff *skb;
- struct fcoe_softc *fc;
+ int rc = -1;
- fc = fcoe_softc(lp);
spin_lock_bh(&fc->fcoe_pending_queue.lock);
+ if (fc->fcoe_pending_queue_active)
+ goto out;
+ fc->fcoe_pending_queue_active = 1;
- /*
- * is this interface paused?
- */
- if (fc->fcoe_pending_queue.qlen > FCOE_MAX_QUEUE_DEPTH)
- paused = 1;
- if (fc->fcoe_pending_queue.qlen) {
- while ((skb = __skb_dequeue(&fc->fcoe_pending_queue)) != NULL) {
- spin_unlock_bh(&fc->fcoe_pending_queue.lock);
- rc = fcoe_start_io(skb);
- if (rc) {
- fcoe_insert_wait_queue_head(lp, skb);
- return rc;
- }
- spin_lock_bh(&fc->fcoe_pending_queue.lock);
- }
- if (fc->fcoe_pending_queue.qlen < FCOE_MAX_QUEUE_DEPTH)
- unpause = 1;
- }
- spin_unlock_bh(&fc->fcoe_pending_queue.lock);
- if ((unpause) && (paused))
- fc_unpause(lp);
- return fc->fcoe_pending_queue.qlen;
-}
-
-/**
- * fcoe_insert_wait_queue_head - puts skb to fcoe pending queue head
- * @lp: the fc_port for this skb
- * @skb: the associated skb to be xmitted
- *
- * Returns: none
- **/
-static void fcoe_insert_wait_queue_head(struct fc_lport *lp,
- struct sk_buff *skb)
-{
- struct fcoe_softc *fc;
+ while (fc->fcoe_pending_queue.qlen) {
+ /* keep qlen > 0 until fcoe_start_io succeeds */
+ fc->fcoe_pending_queue.qlen++;
+ skb = __skb_dequeue(&fc->fcoe_pending_queue);
- fc = fcoe_softc(lp);
- spin_lock_bh(&fc->fcoe_pending_queue.lock);
- __skb_queue_head(&fc->fcoe_pending_queue, skb);
- spin_unlock_bh(&fc->fcoe_pending_queue.lock);
-}
+ spin_unlock_bh(&fc->fcoe_pending_queue.lock);
+ rc = fcoe_start_io(skb);
+ spin_lock_bh(&fc->fcoe_pending_queue.lock);
-/**
- * fcoe_insert_wait_queue - put the skb into fcoe pending queue tail
- * @lp: the fc_port for this skb
- * @skb: the associated skb to be xmitted
- *
- * Returns: none
- **/
-static void fcoe_insert_wait_queue(struct fc_lport *lp,
- struct sk_buff *skb)
-{
- struct fcoe_softc *fc;
+ if (rc) {
+ __skb_queue_head(&fc->fcoe_pending_queue, skb);
+ /* undo temporary increment above */
+ fc->fcoe_pending_queue.qlen--;
+ break;
+ }
+ /* undo temporary increment above */
+ fc->fcoe_pending_queue.qlen--;
+ }
- fc = fcoe_softc(lp);
- spin_lock_bh(&fc->fcoe_pending_queue.lock);
- __skb_queue_tail(&fc->fcoe_pending_queue, skb);
+ if (fc->fcoe_pending_queue.qlen < FCOE_LOW_QUEUE_DEPTH)
+ lp->qfull = 0;
+ fc->fcoe_pending_queue_active = 0;
+ rc = fc->fcoe_pending_queue.qlen;
+out:
spin_unlock_bh(&fc->fcoe_pending_queue.lock);
+ return rc;
}
/**
- * fcoe_dev_setup - setup link change notification interface
- *
- **/
-static void fcoe_dev_setup(void)
+ * fcoe_dev_setup() - setup link change notification interface
+ */
+static void fcoe_dev_setup()
{
/*
* here setup a interface specific wd time to
@@ -849,15 +806,15 @@ static void fcoe_dev_setup(void)
}
/**
- * fcoe_dev_setup - cleanup link change notification interface
- **/
+ * fcoe_dev_setup() - cleanup link change notification interface
+ */
static void fcoe_dev_cleanup(void)
{
unregister_netdevice_notifier(&fcoe_notifier);
}
/**
- * fcoe_device_notification - netdev event notification callback
+ * fcoe_device_notification() - netdev event notification callback
* @notifier: context of the notification
* @event: type of event
* @ptr: fixed array for output parsed ifname
@@ -865,7 +822,7 @@ static void fcoe_dev_cleanup(void)
* This function is called by the ethernet driver in case of link change event
*
* Returns: 0 for success
- **/
+ */
static int fcoe_device_notification(struct notifier_block *notifier,
ulong event, void *ptr)
{
@@ -873,7 +830,7 @@ static int fcoe_device_notification(struct notifier_block *notifier,
struct net_device *real_dev = ptr;
struct fcoe_softc *fc;
struct fcoe_dev_stats *stats;
- u16 new_status;
+ u32 new_link_up;
u32 mfs;
int rc = NOTIFY_OK;
@@ -890,17 +847,15 @@ static int fcoe_device_notification(struct notifier_block *notifier,
goto out;
}
- new_status = lp->link_status;
+ new_link_up = lp->link_up;
switch (event) {
case NETDEV_DOWN:
case NETDEV_GOING_DOWN:
- new_status &= ~FC_LINK_UP;
+ new_link_up = 0;
break;
case NETDEV_UP:
case NETDEV_CHANGE:
- new_status &= ~FC_LINK_UP;
- if (!fcoe_link_ok(lp))
- new_status |= FC_LINK_UP;
+ new_link_up = !fcoe_link_ok(lp);
break;
case NETDEV_CHANGEMTU:
mfs = fc->real_dev->mtu -
@@ -908,17 +863,15 @@ static int fcoe_device_notification(struct notifier_block *notifier,
sizeof(struct fcoe_crc_eof));
if (mfs >= FC_MIN_MAX_FRAME)
fc_set_mfs(lp, mfs);
- new_status &= ~FC_LINK_UP;
- if (!fcoe_link_ok(lp))
- new_status |= FC_LINK_UP;
+ new_link_up = !fcoe_link_ok(lp);
break;
case NETDEV_REGISTER:
break;
default:
FC_DBG("unknown event %ld call", event);
}
- if (lp->link_status != new_status) {
- if ((new_status & FC_LINK_UP) == FC_LINK_UP)
+ if (lp->link_up != new_link_up) {
+ if (new_link_up)
fc_linkup(lp);
else {
stats = lp->dev_stats[smp_processor_id()];
@@ -933,12 +886,12 @@ out:
}
/**
- * fcoe_if_to_netdev - parse a name buffer to get netdev
+ * fcoe_if_to_netdev() - parse a name buffer to get netdev
* @ifname: fixed array for output parsed ifname
* @buffer: incoming buffer to be copied
*
* Returns: NULL or ptr to netdeive
- **/
+ */
static struct net_device *fcoe_if_to_netdev(const char *buffer)
{
char *cp;
@@ -955,13 +908,13 @@ static struct net_device *fcoe_if_to_netdev(const char *buffer)
}
/**
- * fcoe_netdev_to_module_owner - finds out the nic drive moddule of the netdev
+ * fcoe_netdev_to_module_owner() - finds out the nic drive moddule of the netdev
* @netdev: the target netdev
*
* Returns: ptr to the struct module, NULL for failure
- **/
-static struct module *fcoe_netdev_to_module_owner(
- const struct net_device *netdev)
+ */
+static struct module *
+fcoe_netdev_to_module_owner(const struct net_device *netdev)
{
struct device *dev;
@@ -979,12 +932,14 @@ static struct module *fcoe_netdev_to_module_owner(
}
/**
- * fcoe_ethdrv_get - holds the nic driver module by try_module_get() for
- * the corresponding netdev.
+ * fcoe_ethdrv_get() - Hold the Ethernet driver
* @netdev: the target netdev
*
+ * Holds the Ethernet driver module by try_module_get() for
+ * the corresponding netdev.
+ *
* Returns: 0 for succsss
- **/
+ */
static int fcoe_ethdrv_get(const struct net_device *netdev)
{
struct module *owner;
@@ -999,12 +954,14 @@ static int fcoe_ethdrv_get(const struct net_device *netdev)
}
/**
- * fcoe_ethdrv_get - releases the nic driver module by module_put for
- * the corresponding netdev.
+ * fcoe_ethdrv_put() - Release the Ethernet driver
* @netdev: the target netdev
*
+ * Releases the Ethernet driver module by module_put for
+ * the corresponding netdev.
+ *
* Returns: 0 for succsss
- **/
+ */
static int fcoe_ethdrv_put(const struct net_device *netdev)
{
struct module *owner;
@@ -1020,12 +977,12 @@ static int fcoe_ethdrv_put(const struct net_device *netdev)
}
/**
- * fcoe_destroy- handles the destroy from sysfs
+ * fcoe_destroy() - handles the destroy from sysfs
* @buffer: expcted to be a eth if name
* @kp: associated kernel param
*
* Returns: 0 for success
- **/
+ */
static int fcoe_destroy(const char *buffer, struct kernel_param *kp)
{
int rc;
@@ -1058,12 +1015,12 @@ out_nodev:
}
/**
- * fcoe_create - handles the create call from sysfs
+ * fcoe_create() - Handles the create call from sysfs
* @buffer: expcted to be a eth if name
* @kp: associated kernel param
*
* Returns: 0 for success
- **/
+ */
static int fcoe_create(const char *buffer, struct kernel_param *kp)
{
int rc;
@@ -1104,8 +1061,8 @@ module_param_call(destroy, fcoe_destroy, NULL, NULL, S_IWUSR);
__MODULE_PARM_TYPE(destroy, "string");
MODULE_PARM_DESC(destroy, "Destroy fcoe port");
-/*
- * fcoe_link_ok - check if link is ok for the fc_lport
+/**
+ * fcoe_link_ok() - Check if link is ok for the fc_lport
* @lp: ptr to the fc_lport
*
* Any permanently-disqualifying conditions have been previously checked.
@@ -1120,7 +1077,7 @@ MODULE_PARM_DESC(destroy, "Destroy fcoe port");
*/
int fcoe_link_ok(struct fc_lport *lp)
{
- struct fcoe_softc *fc = fcoe_softc(lp);
+ struct fcoe_softc *fc = lport_priv(lp);
struct net_device *dev = fc->real_dev;
struct ethtool_cmd ecmd = { ETHTOOL_GSET };
int rc = 0;
@@ -1149,9 +1106,8 @@ int fcoe_link_ok(struct fc_lport *lp)
}
EXPORT_SYMBOL_GPL(fcoe_link_ok);
-/*
- * fcoe_percpu_clean - frees skb of the corresponding lport from the per
- * cpu queue.
+/**
+ * fcoe_percpu_clean() - Clear the pending skbs for an lport
* @lp: the fc_lport
*/
void fcoe_percpu_clean(struct fc_lport *lp)
@@ -1185,11 +1141,11 @@ void fcoe_percpu_clean(struct fc_lport *lp)
EXPORT_SYMBOL_GPL(fcoe_percpu_clean);
/**
- * fcoe_clean_pending_queue - dequeue skb and free it
+ * fcoe_clean_pending_queue() - Dequeue a skb and free it
* @lp: the corresponding fc_lport
*
* Returns: none
- **/
+ */
void fcoe_clean_pending_queue(struct fc_lport *lp)
{
struct fcoe_softc *fc = lport_priv(lp);
@@ -1206,21 +1162,21 @@ void fcoe_clean_pending_queue(struct fc_lport *lp)
EXPORT_SYMBOL_GPL(fcoe_clean_pending_queue);
/**
- * libfc_host_alloc - allocate a Scsi_Host with room for the fc_lport
+ * libfc_host_alloc() - Allocate a Scsi_Host with room for the fc_lport
* @sht: ptr to the scsi host templ
* @priv_size: size of private data after fc_lport
*
* Returns: ptr to Scsi_Host
- * TODO - to libfc?
+ * TODO: to libfc?
*/
-static inline struct Scsi_Host *libfc_host_alloc(
- struct scsi_host_template *sht, int priv_size)
+static inline struct Scsi_Host *
+libfc_host_alloc(struct scsi_host_template *sht, int priv_size)
{
return scsi_host_alloc(sht, sizeof(struct fc_lport) + priv_size);
}
/**
- * fcoe_host_alloc - allocate a Scsi_Host with room for the fcoe_softc
+ * fcoe_host_alloc() - Allocate a Scsi_Host with room for the fcoe_softc
* @sht: ptr to the scsi host templ
* @priv_size: size of private data after fc_lport
*
@@ -1232,8 +1188,8 @@ struct Scsi_Host *fcoe_host_alloc(struct scsi_host_template *sht, int priv_size)
}
EXPORT_SYMBOL_GPL(fcoe_host_alloc);
-/*
- * fcoe_reset - resets the fcoe
+/**
+ * fcoe_reset() - Resets the fcoe
* @shost: shost the reset is from
*
* Returns: always 0
@@ -1246,8 +1202,8 @@ int fcoe_reset(struct Scsi_Host *shost)
}
EXPORT_SYMBOL_GPL(fcoe_reset);
-/*
- * fcoe_wwn_from_mac - converts 48-bit IEEE MAC address to 64-bit FC WWN.
+/**
+ * fcoe_wwn_from_mac() - Converts 48-bit IEEE MAC address to 64-bit FC WWN.
* @mac: mac address
* @scheme: check port
* @port: port indicator for converting
@@ -1286,14 +1242,15 @@ u64 fcoe_wwn_from_mac(unsigned char mac[MAX_ADDR_LEN],
return wwn;
}
EXPORT_SYMBOL_GPL(fcoe_wwn_from_mac);
-/*
- * fcoe_hostlist_lookup_softc - find the corresponding lport by a given device
+
+/**
+ * fcoe_hostlist_lookup_softc() - find the corresponding lport by a given device
* @device: this is currently ptr to net_device
*
* Returns: NULL or the located fcoe_softc
*/
-static struct fcoe_softc *fcoe_hostlist_lookup_softc(
- const struct net_device *dev)
+static struct fcoe_softc *
+fcoe_hostlist_lookup_softc(const struct net_device *dev)
{
struct fcoe_softc *fc;
@@ -1308,8 +1265,8 @@ static struct fcoe_softc *fcoe_hostlist_lookup_softc(
return NULL;
}
-/*
- * fcoe_hostlist_lookup - find the corresponding lport by netdev
+/**
+ * fcoe_hostlist_lookup() - Find the corresponding lport by netdev
* @netdev: ptr to net_device
*
* Returns: 0 for success
@@ -1324,8 +1281,8 @@ struct fc_lport *fcoe_hostlist_lookup(const struct net_device *netdev)
}
EXPORT_SYMBOL_GPL(fcoe_hostlist_lookup);
-/*
- * fcoe_hostlist_add - add a lport to lports list
+/**
+ * fcoe_hostlist_add() - Add a lport to lports list
* @lp: ptr to the fc_lport to badded
*
* Returns: 0 for success
@@ -1336,7 +1293,7 @@ int fcoe_hostlist_add(const struct fc_lport *lp)
fc = fcoe_hostlist_lookup_softc(fcoe_netdev(lp));
if (!fc) {
- fc = fcoe_softc(lp);
+ fc = lport_priv(lp);
write_lock_bh(&fcoe_hostlist_lock);
list_add_tail(&fc->list, &fcoe_hostlist);
write_unlock_bh(&fcoe_hostlist_lock);
@@ -1345,8 +1302,8 @@ int fcoe_hostlist_add(const struct fc_lport *lp)
}
EXPORT_SYMBOL_GPL(fcoe_hostlist_add);
-/*
- * fcoe_hostlist_remove - remove a lport from lports list
+/**
+ * fcoe_hostlist_remove() - remove a lport from lports list
* @lp: ptr to the fc_lport to badded
*
* Returns: 0 for success
@@ -1366,12 +1323,12 @@ int fcoe_hostlist_remove(const struct fc_lport *lp)
EXPORT_SYMBOL_GPL(fcoe_hostlist_remove);
/**
- * fcoe_libfc_config - sets up libfc related properties for lport
+ * fcoe_libfc_config() - sets up libfc related properties for lport
* @lp: ptr to the fc_lport
* @tt: libfc function template
*
* Returns : 0 for success
- **/
+ */
int fcoe_libfc_config(struct fc_lport *lp, struct libfc_function_template *tt)
{
/* Set the function pointers set by the LLDD */
@@ -1389,14 +1346,14 @@ int fcoe_libfc_config(struct fc_lport *lp, struct libfc_function_template *tt)
EXPORT_SYMBOL_GPL(fcoe_libfc_config);
/**
- * fcoe_init - fcoe module loading initialization
+ * fcoe_init() - fcoe module loading initialization
*
* Initialization routine
* 1. Will create fc transport software structure
* 2. initialize the link list of port information structure
*
* Returns 0 on success, negative on failure
- **/
+ */
static int __init fcoe_init(void)
{
int cpu;
@@ -1433,7 +1390,6 @@ static int __init fcoe_init(void)
} else {
fcoe_percpu[cpu] = NULL;
kfree(p);
-
}
}
}
@@ -1443,11 +1399,9 @@ static int __init fcoe_init(void)
*/
fcoe_dev_setup();
- init_timer(&fcoe_timer);
- fcoe_timer.data = 0;
- fcoe_timer.function = fcoe_watchdog;
- fcoe_timer.expires = (jiffies + (10 * HZ));
- add_timer(&fcoe_timer);
+ setup_timer(&fcoe_timer, fcoe_watchdog, 0);
+
+ mod_timer(&fcoe_timer, jiffies + (10 * HZ));
/* initiatlize the fcoe transport */
fcoe_transport_init();
@@ -1459,10 +1413,10 @@ static int __init fcoe_init(void)
module_init(fcoe_init);
/**
- * fcoe_exit - fcoe module unloading cleanup
+ * fcoe_exit() - fcoe module unloading cleanup
*
* Returns 0 on success, negative on failure
- **/
+ */
static void __exit fcoe_exit(void)
{
u32 idx;
@@ -1483,7 +1437,7 @@ static void __exit fcoe_exit(void)
*/
del_timer_sync(&fcoe_timer);
- /* releases the assocaited fcoe transport for each lport */
+ /* releases the associated fcoe transport for each lport */
list_for_each_entry_safe(fc, tmp, &fcoe_hostlist, list)
fcoe_transport_release(fc->real_dev);
diff --git a/drivers/scsi/lasi700.c b/drivers/scsi/lasi700.c
index 4a4e6954ec7..f23c4ca9a2e 100644
--- a/drivers/scsi/lasi700.c
+++ b/drivers/scsi/lasi700.c
@@ -103,7 +103,7 @@ lasi700_probe(struct parisc_device *dev)
hostdata = kzalloc(sizeof(*hostdata), GFP_KERNEL);
if (!hostdata) {
- dev_printk(KERN_ERR, dev, "Failed to allocate host data\n");
+ dev_printk(KERN_ERR, &dev->dev, "Failed to allocate host data\n");
return -ENOMEM;
}
diff --git a/drivers/scsi/libfc/fc_disc.c b/drivers/scsi/libfc/fc_disc.c
index dd1564c9e04..e57556ea5b4 100644
--- a/drivers/scsi/libfc/fc_disc.c
+++ b/drivers/scsi/libfc/fc_disc.c
@@ -64,7 +64,7 @@ static void fc_disc_single(struct fc_disc *, struct fc_disc_port *);
static void fc_disc_restart(struct fc_disc *);
/**
- * fc_disc_lookup_rport - lookup a remote port by port_id
+ * fc_disc_lookup_rport() - lookup a remote port by port_id
* @lport: Fibre Channel host port instance
* @port_id: remote port port_id to match
*/
@@ -92,7 +92,7 @@ struct fc_rport *fc_disc_lookup_rport(const struct fc_lport *lport,
}
/**
- * fc_disc_stop_rports - delete all the remote ports associated with the lport
+ * fc_disc_stop_rports() - delete all the remote ports associated with the lport
* @disc: The discovery job to stop rports on
*
* Locking Note: This function expects that the lport mutex is locked before
@@ -117,7 +117,7 @@ void fc_disc_stop_rports(struct fc_disc *disc)
}
/**
- * fc_disc_rport_callback - Event handler for rport events
+ * fc_disc_rport_callback() - Event handler for rport events
* @lport: The lport which is receiving the event
* @rport: The rport which the event has occured on
* @event: The event that occured
@@ -151,7 +151,7 @@ static void fc_disc_rport_callback(struct fc_lport *lport,
}
/**
- * fc_disc_recv_rscn_req - Handle Registered State Change Notification (RSCN)
+ * fc_disc_recv_rscn_req() - Handle Registered State Change Notification (RSCN)
* @sp: Current sequence of the RSCN exchange
* @fp: RSCN Frame
* @lport: Fibre Channel host port instance
@@ -246,7 +246,7 @@ static void fc_disc_recv_rscn_req(struct fc_seq *sp, struct fc_frame *fp,
list_del(&dp->peers);
rport = lport->tt.rport_lookup(lport, dp->ids.port_id);
if (rport) {
- rdata = RPORT_TO_PRIV(rport);
+ rdata = rport->dd_data;
list_del(&rdata->peers);
lport->tt.rport_logoff(rport);
}
@@ -265,7 +265,7 @@ reject:
}
/**
- * fc_disc_recv_req - Handle incoming requests
+ * fc_disc_recv_req() - Handle incoming requests
* @sp: Current sequence of the request exchange
* @fp: The frame
* @lport: The FC local port
@@ -294,7 +294,7 @@ static void fc_disc_recv_req(struct fc_seq *sp, struct fc_frame *fp,
}
/**
- * fc_disc_restart - Restart discovery
+ * fc_disc_restart() - Restart discovery
* @lport: FC discovery context
*
* Locking Note: This function expects that the disc mutex
@@ -322,7 +322,7 @@ static void fc_disc_restart(struct fc_disc *disc)
}
/**
- * fc_disc_start - Fibre Channel Target discovery
+ * fc_disc_start() - Fibre Channel Target discovery
* @lport: FC local port
*
* Returns non-zero if discovery cannot be started.
@@ -383,7 +383,7 @@ static struct fc_rport_operations fc_disc_rport_ops = {
};
/**
- * fc_disc_new_target - Handle new target found by discovery
+ * fc_disc_new_target() - Handle new target found by discovery
* @lport: FC local port
* @rport: The previous FC remote port (NULL if new remote port)
* @ids: Identifiers for the new FC remote port
@@ -396,7 +396,7 @@ static int fc_disc_new_target(struct fc_disc *disc,
struct fc_rport_identifiers *ids)
{
struct fc_lport *lport = disc->lport;
- struct fc_rport_libfc_priv *rp;
+ struct fc_rport_libfc_priv *rdata;
int error = 0;
if (rport && ids->port_name) {
@@ -430,15 +430,15 @@ static int fc_disc_new_target(struct fc_disc *disc,
dp.ids.port_name = ids->port_name;
dp.ids.node_name = ids->node_name;
dp.ids.roles = ids->roles;
- rport = fc_rport_rogue_create(&dp);
+ rport = lport->tt.rport_create(&dp);
}
if (!rport)
error = -ENOMEM;
}
if (rport) {
- rp = rport->dd_data;
- rp->ops = &fc_disc_rport_ops;
- rp->rp_state = RPORT_ST_INIT;
+ rdata = rport->dd_data;
+ rdata->ops = &fc_disc_rport_ops;
+ rdata->rp_state = RPORT_ST_INIT;
lport->tt.rport_login(rport);
}
}
@@ -446,20 +446,20 @@ static int fc_disc_new_target(struct fc_disc *disc,
}
/**
- * fc_disc_del_target - Delete a target
+ * fc_disc_del_target() - Delete a target
* @disc: FC discovery context
* @rport: The remote port to be removed
*/
static void fc_disc_del_target(struct fc_disc *disc, struct fc_rport *rport)
{
struct fc_lport *lport = disc->lport;
- struct fc_rport_libfc_priv *rdata = RPORT_TO_PRIV(rport);
+ struct fc_rport_libfc_priv *rdata = rport->dd_data;
list_del(&rdata->peers);
lport->tt.rport_logoff(rport);
}
/**
- * fc_disc_done - Discovery has been completed
+ * fc_disc_done() - Discovery has been completed
* @disc: FC discovery context
*/
static void fc_disc_done(struct fc_disc *disc)
@@ -479,7 +479,7 @@ static void fc_disc_done(struct fc_disc *disc)
}
/**
- * fc_disc_error - Handle error on dNS request
+ * fc_disc_error() - Handle error on dNS request
* @disc: FC discovery context
* @fp: The frame pointer
*/
@@ -519,7 +519,7 @@ static void fc_disc_error(struct fc_disc *disc, struct fc_frame *fp)
}
/**
- * fc_disc_gpn_ft_req - Send Get Port Names by FC-4 type (GPN_FT) request
+ * fc_disc_gpn_ft_req() - Send Get Port Names by FC-4 type (GPN_FT) request
* @lport: FC discovery context
*
* Locking Note: This function expects that the disc_mutex is locked
@@ -553,7 +553,7 @@ err:
}
/**
- * fc_disc_gpn_ft_parse - Parse the list of IDs and names resulting from a request
+ * fc_disc_gpn_ft_parse() - Parse the list of IDs and names resulting from a request
* @lport: Fibre Channel host port instance
* @buf: GPN_FT response buffer
* @len: size of response buffer
@@ -617,7 +617,7 @@ static int fc_disc_gpn_ft_parse(struct fc_disc *disc, void *buf, size_t len)
if ((dp.ids.port_id != fc_host_port_id(lport->host)) &&
(dp.ids.port_name != lport->wwpn)) {
- rport = fc_rport_rogue_create(&dp);
+ rport = lport->tt.rport_create(&dp);
if (rport) {
rdata = rport->dd_data;
rdata->ops = &fc_disc_rport_ops;
@@ -658,7 +658,10 @@ static int fc_disc_gpn_ft_parse(struct fc_disc *disc, void *buf, size_t len)
return error;
}
-/*
+/**
+ * fc_disc_timeout() - Retry handler for the disc component
+ * @work: Structure holding disc obj that needs retry discovery
+ *
* Handle retry of memory allocation for remote ports.
*/
static void fc_disc_timeout(struct work_struct *work)
@@ -673,7 +676,7 @@ static void fc_disc_timeout(struct work_struct *work)
}
/**
- * fc_disc_gpn_ft_resp - Handle a response frame from Get Port Names (GPN_FT)
+ * fc_disc_gpn_ft_resp() - Handle a response frame from Get Port Names (GPN_FT)
* @sp: Current sequence of GPN_FT exchange
* @fp: response frame
* @lp_arg: Fibre Channel host port instance
@@ -712,9 +715,7 @@ static void fc_disc_gpn_ft_resp(struct fc_seq *sp, struct fc_frame *fp,
fr_len(fp));
} else if (ntohs(cp->ct_cmd) == FC_FS_ACC) {
- /*
- * Accepted. Parse response.
- */
+ /* Accepted, parse the response. */
buf = cp + 1;
len -= sizeof(*cp);
} else if (ntohs(cp->ct_cmd) == FC_FS_RJT) {
@@ -746,7 +747,7 @@ static void fc_disc_gpn_ft_resp(struct fc_seq *sp, struct fc_frame *fp,
}
/**
- * fc_disc_single - Discover the directory information for a single target
+ * fc_disc_single() - Discover the directory information for a single target
* @lport: FC local port
* @dp: The port to rediscover
*
@@ -769,7 +770,7 @@ static void fc_disc_single(struct fc_disc *disc, struct fc_disc_port *dp)
if (rport)
fc_disc_del_target(disc, rport);
- new_rport = fc_rport_rogue_create(dp);
+ new_rport = lport->tt.rport_create(dp);
if (new_rport) {
rdata = new_rport->dd_data;
rdata->ops = &fc_disc_rport_ops;
@@ -782,7 +783,7 @@ out:
}
/**
- * fc_disc_stop - Stop discovery for a given lport
+ * fc_disc_stop() - Stop discovery for a given lport
* @lport: The lport that discovery should stop for
*/
void fc_disc_stop(struct fc_lport *lport)
@@ -796,7 +797,7 @@ void fc_disc_stop(struct fc_lport *lport)
}
/**
- * fc_disc_stop_final - Stop discovery for a given lport
+ * fc_disc_stop_final() - Stop discovery for a given lport
* @lport: The lport that discovery should stop for
*
* This function will block until discovery has been
@@ -809,7 +810,7 @@ void fc_disc_stop_final(struct fc_lport *lport)
}
/**
- * fc_disc_init - Initialize the discovery block
+ * fc_disc_init() - Initialize the discovery block
* @lport: FC local port
*/
int fc_disc_init(struct fc_lport *lport)
diff --git a/drivers/scsi/libfc/fc_exch.c b/drivers/scsi/libfc/fc_exch.c
index 66db08a5f27..505825b6124 100644
--- a/drivers/scsi/libfc/fc_exch.c
+++ b/drivers/scsi/libfc/fc_exch.c
@@ -32,8 +32,6 @@
#include <scsi/libfc.h>
#include <scsi/fc_encode.h>
-#define FC_DEF_R_A_TOV (10 * 1000) /* resource allocation timeout */
-
/*
* fc_exch_debug can be set in debugger or at compile time to get more logs.
*/
@@ -627,7 +625,6 @@ static struct fc_exch *fc_exch_resp(struct fc_exch_mgr *mp, struct fc_frame *fp)
{
struct fc_exch *ep;
struct fc_frame_header *fh;
- u16 rxid;
ep = mp->lp->tt.exch_get(mp->lp, fp);
if (ep) {
@@ -654,18 +651,6 @@ static struct fc_exch *fc_exch_resp(struct fc_exch_mgr *mp, struct fc_frame *fp)
if ((ntoh24(fh->fh_f_ctl) & FC_FC_SEQ_INIT) == 0)
ep->esb_stat &= ~ESB_ST_SEQ_INIT;
- /*
- * Set the responder ID in the frame header.
- * The old one should've been 0xffff.
- * If it isn't, don't assign one.
- * Incoming basic link service frames may specify
- * a referenced RX_ID.
- */
- if (fh->fh_type != FC_TYPE_BLS) {
- rxid = ntohs(fh->fh_rx_id);
- WARN_ON(rxid != FC_XID_UNKNOWN);
- fh->fh_rx_id = htons(ep->rxid);
- }
fc_exch_hold(ep); /* hold for caller */
spin_unlock_bh(&ep->ex_lock); /* lock from exch_get */
}
@@ -677,8 +662,8 @@ static struct fc_exch *fc_exch_resp(struct fc_exch_mgr *mp, struct fc_frame *fp)
* If fc_pf_rjt_reason is FC_RJT_NONE then this function will have a hold
* on the ep that should be released by the caller.
*/
-static enum fc_pf_rjt_reason
-fc_seq_lookup_recip(struct fc_exch_mgr *mp, struct fc_frame *fp)
+static enum fc_pf_rjt_reason fc_seq_lookup_recip(struct fc_exch_mgr *mp,
+ struct fc_frame *fp)
{
struct fc_frame_header *fh = fc_frame_header_get(fp);
struct fc_exch *ep = NULL;
@@ -996,9 +981,9 @@ static void fc_seq_send_ack(struct fc_seq *sp, const struct fc_frame *rx_fp)
* Send BLS Reject.
* This is for rejecting BA_ABTS only.
*/
-static void
-fc_exch_send_ba_rjt(struct fc_frame *rx_fp, enum fc_ba_rjt_reason reason,
- enum fc_ba_rjt_explan explan)
+static void fc_exch_send_ba_rjt(struct fc_frame *rx_fp,
+ enum fc_ba_rjt_reason reason,
+ enum fc_ba_rjt_explan explan)
{
struct fc_frame *fp;
struct fc_frame_header *rx_fh;
@@ -1096,7 +1081,7 @@ static void fc_exch_recv_abts(struct fc_exch *ep, struct fc_frame *rx_fp)
ap->ba_high_seq_cnt = fh->fh_seq_cnt;
ap->ba_low_seq_cnt = htons(sp->cnt);
}
- sp = fc_seq_start_next(sp);
+ sp = fc_seq_start_next_locked(sp);
spin_unlock_bh(&ep->ex_lock);
fc_seq_send_last(sp, fp, FC_RCTL_BA_ACC, FC_TYPE_BLS);
fc_frame_free(rx_fp);
@@ -1480,10 +1465,11 @@ static void fc_exch_reset(struct fc_exch *ep)
* If sid is non-zero, reset only exchanges we source from that FID.
* If did is non-zero, reset only exchanges destined to that FID.
*/
-void fc_exch_mgr_reset(struct fc_exch_mgr *mp, u32 sid, u32 did)
+void fc_exch_mgr_reset(struct fc_lport *lp, u32 sid, u32 did)
{
struct fc_exch *ep;
struct fc_exch *next;
+ struct fc_exch_mgr *mp = lp->emp;
spin_lock_bh(&mp->em_lock);
restart:
@@ -1607,7 +1593,7 @@ static void fc_exch_rrq_resp(struct fc_seq *sp, struct fc_frame *fp, void *arg)
if (IS_ERR(fp)) {
int err = PTR_ERR(fp);
- if (err == -FC_EX_CLOSED)
+ if (err == -FC_EX_CLOSED || err == -FC_EX_TIMEOUT)
goto cleanup;
FC_DBG("Cannot process RRQ, because of frame error %d\n", err);
return;
diff --git a/drivers/scsi/libfc/fc_fcp.c b/drivers/scsi/libfc/fc_fcp.c
index 404e63ff46b..2a631d7dbce 100644
--- a/drivers/scsi/libfc/fc_fcp.c
+++ b/drivers/scsi/libfc/fc_fcp.c
@@ -161,7 +161,7 @@ static struct fc_fcp_pkt *fc_fcp_pkt_alloc(struct fc_lport *lp, gfp_t gfp)
}
/**
- * fc_fcp_pkt_release - release hold on scsi_pkt packet
+ * fc_fcp_pkt_release() - release hold on scsi_pkt packet
* @fsp: fcp packet struct
*
* This is used by upper layer scsi driver.
@@ -183,8 +183,7 @@ static void fc_fcp_pkt_hold(struct fc_fcp_pkt *fsp)
}
/**
- * fc_fcp_pkt_destory - release hold on scsi_pkt packet
- *
+ * fc_fcp_pkt_destory() - release hold on scsi_pkt packet
* @seq: exchange sequence
* @fsp: fcp packet struct
*
@@ -199,7 +198,7 @@ static void fc_fcp_pkt_destroy(struct fc_seq *seq, void *fsp)
}
/**
- * fc_fcp_lock_pkt - lock a packet and get a ref to it.
+ * fc_fcp_lock_pkt() - lock a packet and get a ref to it.
* @fsp: fcp packet
*
* We should only return error if we return a command to scsi-ml before
@@ -291,9 +290,7 @@ static void fc_fcp_recv_data(struct fc_fcp_pkt *fsp, struct fc_frame *fp)
buf = fc_frame_payload_get(fp, 0);
if (offset + len > fsp->data_len) {
- /*
- * this should never happen
- */
+ /* this should never happen */
if ((fr_flags(fp) & FCPHF_CRC_UNCHECKED) &&
fc_frame_crc_check(fp))
goto crc_err;
@@ -387,8 +384,8 @@ crc_err:
fc_fcp_complete_locked(fsp);
}
-/*
- * fc_fcp_send_data - Send SCSI data to target.
+/**
+ * fc_fcp_send_data() - Send SCSI data to target.
* @fsp: ptr to fc_fcp_pkt
* @sp: ptr to this sequence
* @offset: starting offset for this data request
@@ -610,8 +607,8 @@ static void fc_fcp_abts_resp(struct fc_fcp_pkt *fsp, struct fc_frame *fp)
}
}
-/*
- * fc_fcp_reduce_can_queue - drop can_queue
+/**
+ * fc_fcp_reduce_can_queue() - drop can_queue
* @lp: lport to drop queueing for
*
* If we are getting memory allocation failures, then we may
@@ -642,9 +639,11 @@ done:
spin_unlock_irqrestore(lp->host->host_lock, flags);
}
-/*
- * exch mgr calls this routine to process scsi
- * exchanges.
+/**
+ * fc_fcp_recv() - Reveive FCP frames
+ * @seq: The sequence the frame is on
+ * @fp: The FC frame
+ * @arg: The related FCP packet
*
* Return : None
* Context : called from Soft IRQ context
@@ -832,7 +831,7 @@ err:
}
/**
- * fc_fcp_complete_locked - complete processing of a fcp packet
+ * fc_fcp_complete_locked() - complete processing of a fcp packet
* @fsp: fcp packet
*
* This function may sleep if a timer is pending. The packet lock must be
@@ -900,7 +899,7 @@ static void fc_fcp_cleanup_cmd(struct fc_fcp_pkt *fsp, int error)
}
/**
- * fc_fcp_cleanup_each_cmd - run fn on each active command
+ * fc_fcp_cleanup_each_cmd() - Cleanup active commads
* @lp: logical port
* @id: target id
* @lun: lun
@@ -952,7 +951,7 @@ static void fc_fcp_abort_io(struct fc_lport *lp)
}
/**
- * fc_fcp_pkt_send - send a fcp packet to the lower level.
+ * fc_fcp_pkt_send() - send a fcp packet to the lower level.
* @lp: fc lport
* @fsp: fc packet.
*
@@ -1621,7 +1620,7 @@ out:
static inline int fc_fcp_lport_queue_ready(struct fc_lport *lp)
{
/* lock ? */
- return (lp->state == LPORT_ST_READY) && (lp->link_status & FC_LINK_UP);
+ return (lp->state == LPORT_ST_READY) && lp->link_up && !lp->qfull;
}
/**
@@ -1727,7 +1726,7 @@ out:
EXPORT_SYMBOL(fc_queuecommand);
/**
- * fc_io_compl - Handle responses for completed commands
+ * fc_io_compl() - Handle responses for completed commands
* @fsp: scsi packet
*
* Translates a error to a Linux SCSI error.
@@ -1810,12 +1809,12 @@ static void fc_io_compl(struct fc_fcp_pkt *fsp)
sc_cmd->result = DID_ERROR << 16;
break;
case FC_DATA_UNDRUN:
- if (fsp->cdb_status == 0) {
+ if ((fsp->cdb_status == 0) && !(fsp->req_flags & FC_SRB_READ)) {
/*
* scsi status is good but transport level
- * underrun. for read it should be an error??
+ * underrun.
*/
- sc_cmd->result = (DID_OK << 16) | fsp->cdb_status;
+ sc_cmd->result = DID_OK << 16;
} else {
/*
* scsi got underrun, this is an error
@@ -1857,7 +1856,7 @@ static void fc_io_compl(struct fc_fcp_pkt *fsp)
}
/**
- * fc_fcp_complete - complete processing of a fcp packet
+ * fc_fcp_complete() - complete processing of a fcp packet
* @fsp: fcp packet
*
* This function may sleep if a fsp timer is pending.
@@ -1874,9 +1873,10 @@ void fc_fcp_complete(struct fc_fcp_pkt *fsp)
EXPORT_SYMBOL(fc_fcp_complete);
/**
- * fc_eh_abort - Abort a command...from scsi host template
+ * fc_eh_abort() - Abort a command
* @sc_cmd: scsi command to abort
*
+ * From scsi host template.
* send ABTS to the target device and wait for the response
* sc_cmd is the pointer to the command to be aborted.
*/
@@ -1890,7 +1890,7 @@ int fc_eh_abort(struct scsi_cmnd *sc_cmd)
lp = shost_priv(sc_cmd->device->host);
if (lp->state != LPORT_ST_READY)
return rc;
- else if (!(lp->link_status & FC_LINK_UP))
+ else if (!lp->link_up)
return rc;
spin_lock_irqsave(lp->host->host_lock, flags);
@@ -1920,7 +1920,7 @@ release_pkt:
EXPORT_SYMBOL(fc_eh_abort);
/**
- * fc_eh_device_reset: Reset a single LUN
+ * fc_eh_device_reset() Reset a single LUN
* @sc_cmd: scsi command
*
* Set from scsi host template to send tm cmd to the target and wait for the
@@ -1973,7 +1973,7 @@ out:
EXPORT_SYMBOL(fc_eh_device_reset);
/**
- * fc_eh_host_reset - The reset function will reset the ports on the host.
+ * fc_eh_host_reset() - The reset function will reset the ports on the host.
* @sc_cmd: scsi command
*/
int fc_eh_host_reset(struct scsi_cmnd *sc_cmd)
@@ -1999,7 +1999,7 @@ int fc_eh_host_reset(struct scsi_cmnd *sc_cmd)
EXPORT_SYMBOL(fc_eh_host_reset);
/**
- * fc_slave_alloc - configure queue depth
+ * fc_slave_alloc() - configure queue depth
* @sdev: scsi device
*
* Configures queue depth based on host's cmd_per_len. If not set
diff --git a/drivers/scsi/libfc/fc_lport.c b/drivers/scsi/libfc/fc_lport.c
index 0b9bdb1fb80..2ae50a1188e 100644
--- a/drivers/scsi/libfc/fc_lport.c
+++ b/drivers/scsi/libfc/fc_lport.c
@@ -139,7 +139,7 @@ static int fc_frame_drop(struct fc_lport *lport, struct fc_frame *fp)
}
/**
- * fc_lport_rport_callback - Event handler for rport events
+ * fc_lport_rport_callback() - Event handler for rport events
* @lport: The lport which is receiving the event
* @rport: The rport which the event has occured on
* @event: The event that occured
@@ -195,7 +195,7 @@ static void fc_lport_rport_callback(struct fc_lport *lport,
}
/**
- * fc_lport_state - Return a string which represents the lport's state
+ * fc_lport_state() - Return a string which represents the lport's state
* @lport: The lport whose state is to converted to a string
*/
static const char *fc_lport_state(struct fc_lport *lport)
@@ -209,7 +209,7 @@ static const char *fc_lport_state(struct fc_lport *lport)
}
/**
- * fc_lport_ptp_setup - Create an rport for point-to-point mode
+ * fc_lport_ptp_setup() - Create an rport for point-to-point mode
* @lport: The lport to attach the ptp rport to
* @fid: The FID of the ptp rport
* @remote_wwpn: The WWPN of the ptp rport
@@ -232,7 +232,7 @@ static void fc_lport_ptp_setup(struct fc_lport *lport,
lport->ptp_rp = NULL;
}
- lport->ptp_rp = fc_rport_rogue_create(&dp);
+ lport->ptp_rp = lport->tt.rport_create(&dp);
lport->tt.rport_login(lport->ptp_rp);
@@ -250,7 +250,7 @@ void fc_get_host_port_state(struct Scsi_Host *shost)
{
struct fc_lport *lp = shost_priv(shost);
- if ((lp->link_status & FC_LINK_UP) == FC_LINK_UP)
+ if (lp->link_up)
fc_host_port_state(shost) = FC_PORTSTATE_ONLINE;
else
fc_host_port_state(shost) = FC_PORTSTATE_OFFLINE;
@@ -351,7 +351,7 @@ static void fc_lport_add_fc4_type(struct fc_lport *lport, enum fc_fh_type type)
}
/**
- * fc_lport_recv_rlir_req - Handle received Registered Link Incident Report.
+ * fc_lport_recv_rlir_req() - Handle received Registered Link Incident Report.
* @lport: Fibre Channel local port recieving the RLIR
* @sp: current sequence in the RLIR exchange
* @fp: RLIR request frame
@@ -370,7 +370,7 @@ static void fc_lport_recv_rlir_req(struct fc_seq *sp, struct fc_frame *fp,
}
/**
- * fc_lport_recv_echo_req - Handle received ECHO request
+ * fc_lport_recv_echo_req() - Handle received ECHO request
* @lport: Fibre Channel local port recieving the ECHO
* @sp: current sequence in the ECHO exchange
* @fp: ECHO request frame
@@ -412,7 +412,7 @@ static void fc_lport_recv_echo_req(struct fc_seq *sp, struct fc_frame *in_fp,
}
/**
- * fc_lport_recv_echo_req - Handle received Request Node ID data request
+ * fc_lport_recv_echo_req() - Handle received Request Node ID data request
* @lport: Fibre Channel local port recieving the RNID
* @sp: current sequence in the RNID exchange
* @fp: RNID request frame
@@ -479,7 +479,7 @@ static void fc_lport_recv_rnid_req(struct fc_seq *sp, struct fc_frame *in_fp,
}
/**
- * fc_lport_recv_adisc_req - Handle received Address Discovery Request
+ * fc_lport_recv_adisc_req() - Handle received Address Discovery Request
* @lport: Fibre Channel local port recieving the ADISC
* @sp: current sequence in the ADISC exchange
* @fp: ADISC request frame
@@ -529,7 +529,7 @@ static void fc_lport_recv_adisc_req(struct fc_seq *sp, struct fc_frame *in_fp,
}
/**
- * fc_lport_recv_logo_req - Handle received fabric LOGO request
+ * fc_lport_recv_logo_req() - Handle received fabric LOGO request
* @lport: Fibre Channel local port recieving the LOGO
* @sp: current sequence in the LOGO exchange
* @fp: LOGO request frame
@@ -546,7 +546,7 @@ static void fc_lport_recv_logo_req(struct fc_seq *sp, struct fc_frame *fp,
}
/**
- * fc_fabric_login - Start the lport state machine
+ * fc_fabric_login() - Start the lport state machine
* @lport: The lport that should log into the fabric
*
* Locking Note: This function should not be called
@@ -568,7 +568,7 @@ int fc_fabric_login(struct fc_lport *lport)
EXPORT_SYMBOL(fc_fabric_login);
/**
- * fc_linkup - Handler for transport linkup events
+ * fc_linkup() - Handler for transport linkup events
* @lport: The lport whose link is up
*/
void fc_linkup(struct fc_lport *lport)
@@ -577,8 +577,8 @@ void fc_linkup(struct fc_lport *lport)
fc_host_port_id(lport->host));
mutex_lock(&lport->lp_mutex);
- if ((lport->link_status & FC_LINK_UP) != FC_LINK_UP) {
- lport->link_status |= FC_LINK_UP;
+ if (!lport->link_up) {
+ lport->link_up = 1;
if (lport->state == LPORT_ST_RESET)
fc_lport_enter_flogi(lport);
@@ -588,7 +588,7 @@ void fc_linkup(struct fc_lport *lport)
EXPORT_SYMBOL(fc_linkup);
/**
- * fc_linkdown - Handler for transport linkdown events
+ * fc_linkdown() - Handler for transport linkdown events
* @lport: The lport whose link is down
*/
void fc_linkdown(struct fc_lport *lport)
@@ -597,8 +597,8 @@ void fc_linkdown(struct fc_lport *lport)
FC_DEBUG_LPORT("Link is down for port (%6x)\n",
fc_host_port_id(lport->host));
- if ((lport->link_status & FC_LINK_UP) == FC_LINK_UP) {
- lport->link_status &= ~(FC_LINK_UP);
+ if (lport->link_up) {
+ lport->link_up = 0;
fc_lport_enter_reset(lport);
lport->tt.fcp_cleanup(lport);
}
@@ -607,48 +607,25 @@ void fc_linkdown(struct fc_lport *lport)
EXPORT_SYMBOL(fc_linkdown);
/**
- * fc_pause - Pause the flow of frames
- * @lport: The lport to be paused
- */
-void fc_pause(struct fc_lport *lport)
-{
- mutex_lock(&lport->lp_mutex);
- lport->link_status |= FC_PAUSE;
- mutex_unlock(&lport->lp_mutex);
-}
-EXPORT_SYMBOL(fc_pause);
-
-/**
- * fc_unpause - Unpause the flow of frames
- * @lport: The lport to be unpaused
- */
-void fc_unpause(struct fc_lport *lport)
-{
- mutex_lock(&lport->lp_mutex);
- lport->link_status &= ~(FC_PAUSE);
- mutex_unlock(&lport->lp_mutex);
-}
-EXPORT_SYMBOL(fc_unpause);
-
-/**
- * fc_fabric_logoff - Logout of the fabric
+ * fc_fabric_logoff() - Logout of the fabric
* @lport: fc_lport pointer to logoff the fabric
*
* Return value:
* 0 for success, -1 for failure
- **/
+ */
int fc_fabric_logoff(struct fc_lport *lport)
{
lport->tt.disc_stop_final(lport);
mutex_lock(&lport->lp_mutex);
fc_lport_enter_logo(lport);
mutex_unlock(&lport->lp_mutex);
+ cancel_delayed_work_sync(&lport->retry_work);
return 0;
}
EXPORT_SYMBOL(fc_fabric_logoff);
/**
- * fc_lport_destroy - unregister a fc_lport
+ * fc_lport_destroy() - unregister a fc_lport
* @lport: fc_lport pointer to unregister
*
* Return value:
@@ -658,26 +635,25 @@ EXPORT_SYMBOL(fc_fabric_logoff);
* clean-up all the allocated memory
* and free up other system resources.
*
- **/
+ */
int fc_lport_destroy(struct fc_lport *lport)
{
lport->tt.frame_send = fc_frame_drop;
lport->tt.fcp_abort_io(lport);
- lport->tt.exch_mgr_reset(lport->emp, 0, 0);
+ lport->tt.exch_mgr_reset(lport, 0, 0);
return 0;
}
EXPORT_SYMBOL(fc_lport_destroy);
/**
- * fc_set_mfs - sets up the mfs for the corresponding fc_lport
+ * fc_set_mfs() - sets up the mfs for the corresponding fc_lport
* @lport: fc_lport pointer to unregister
* @mfs: the new mfs for fc_lport
*
* Set mfs for the given fc_lport to the new mfs.
*
* Return: 0 for success
- *
- **/
+ */
int fc_set_mfs(struct fc_lport *lport, u32 mfs)
{
unsigned int old_mfs;
@@ -706,7 +682,7 @@ int fc_set_mfs(struct fc_lport *lport, u32 mfs)
EXPORT_SYMBOL(fc_set_mfs);
/**
- * fc_lport_disc_callback - Callback for discovery events
+ * fc_lport_disc_callback() - Callback for discovery events
* @lport: FC local port
* @event: The discovery event
*/
@@ -731,7 +707,7 @@ void fc_lport_disc_callback(struct fc_lport *lport, enum fc_disc_event event)
}
/**
- * fc_rport_enter_ready - Enter the ready state and start discovery
+ * fc_rport_enter_ready() - Enter the ready state and start discovery
* @lport: Fibre Channel local port that is ready
*
* Locking Note: The lport lock is expected to be held before calling
@@ -748,7 +724,7 @@ static void fc_lport_enter_ready(struct fc_lport *lport)
}
/**
- * fc_lport_recv_flogi_req - Receive a FLOGI request
+ * fc_lport_recv_flogi_req() - Receive a FLOGI request
* @sp_in: The sequence the FLOGI is on
* @rx_fp: The frame the FLOGI is in
* @lport: The lport that recieved the request
@@ -838,7 +814,7 @@ out:
}
/**
- * fc_lport_recv_req - The generic lport request handler
+ * fc_lport_recv_req() - The generic lport request handler
* @lport: The lport that received the request
* @sp: The sequence the request is on
* @fp: The frame the request is in
@@ -934,7 +910,7 @@ static void fc_lport_recv_req(struct fc_lport *lport, struct fc_seq *sp,
}
/**
- * fc_lport_reset - Reset an lport
+ * fc_lport_reset() - Reset an lport
* @lport: The lport which should be reset
*
* Locking Note: This functions should not be called with the
@@ -942,6 +918,7 @@ static void fc_lport_recv_req(struct fc_lport *lport, struct fc_seq *sp,
*/
int fc_lport_reset(struct fc_lport *lport)
{
+ cancel_delayed_work_sync(&lport->retry_work);
mutex_lock(&lport->lp_mutex);
fc_lport_enter_reset(lport);
mutex_unlock(&lport->lp_mutex);
@@ -950,7 +927,7 @@ int fc_lport_reset(struct fc_lport *lport)
EXPORT_SYMBOL(fc_lport_reset);
/**
- * fc_rport_enter_reset - Reset the local port
+ * fc_rport_enter_reset() - Reset the local port
* @lport: Fibre Channel local port to be reset
*
* Locking Note: The lport lock is expected to be held before calling
@@ -973,16 +950,16 @@ static void fc_lport_enter_reset(struct fc_lport *lport)
lport->tt.disc_stop(lport);
- lport->tt.exch_mgr_reset(lport->emp, 0, 0);
+ lport->tt.exch_mgr_reset(lport, 0, 0);
fc_host_fabric_name(lport->host) = 0;
fc_host_port_id(lport->host) = 0;
- if ((lport->link_status & FC_LINK_UP) == FC_LINK_UP)
+ if (lport->link_up)
fc_lport_enter_flogi(lport);
}
/**
- * fc_lport_error - Handler for any errors
+ * fc_lport_error() - Handler for any errors
* @lport: The fc_lport object
* @fp: The frame pointer
*
@@ -1029,8 +1006,8 @@ static void fc_lport_error(struct fc_lport *lport, struct fc_frame *fp)
}
/**
- * fc_lport_rft_id_resp - Handle response to Register Fibre
- * Channel Types by ID (RPN_ID) request
+ * fc_lport_rft_id_resp() - Handle response to Register Fibre
+ * Channel Types by ID (RPN_ID) request
* @sp: current sequence in RPN_ID exchange
* @fp: response frame
* @lp_arg: Fibre Channel host port instance
@@ -1053,17 +1030,17 @@ static void fc_lport_rft_id_resp(struct fc_seq *sp, struct fc_frame *fp,
FC_DEBUG_LPORT("Received a RFT_ID response\n");
+ if (IS_ERR(fp)) {
+ fc_lport_error(lport, fp);
+ goto err;
+ }
+
if (lport->state != LPORT_ST_RFT_ID) {
FC_DBG("Received a RFT_ID response, but in state %s\n",
fc_lport_state(lport));
goto out;
}
- if (IS_ERR(fp)) {
- fc_lport_error(lport, fp);
- goto err;
- }
-
fh = fc_frame_header_get(fp);
ct = fc_frame_payload_get(fp, sizeof(*ct));
@@ -1081,8 +1058,8 @@ err:
}
/**
- * fc_lport_rpn_id_resp - Handle response to Register Port
- * Name by ID (RPN_ID) request
+ * fc_lport_rpn_id_resp() - Handle response to Register Port
+ * Name by ID (RPN_ID) request
* @sp: current sequence in RPN_ID exchange
* @fp: response frame
* @lp_arg: Fibre Channel host port instance
@@ -1105,17 +1082,17 @@ static void fc_lport_rpn_id_resp(struct fc_seq *sp, struct fc_frame *fp,
FC_DEBUG_LPORT("Received a RPN_ID response\n");
+ if (IS_ERR(fp)) {
+ fc_lport_error(lport, fp);
+ goto err;
+ }
+
if (lport->state != LPORT_ST_RPN_ID) {
FC_DBG("Received a RPN_ID response, but in state %s\n",
fc_lport_state(lport));
goto out;
}
- if (IS_ERR(fp)) {
- fc_lport_error(lport, fp);
- goto err;
- }
-
fh = fc_frame_header_get(fp);
ct = fc_frame_payload_get(fp, sizeof(*ct));
if (fh && ct && fh->fh_type == FC_TYPE_CT &&
@@ -1133,7 +1110,7 @@ err:
}
/**
- * fc_lport_scr_resp - Handle response to State Change Register (SCR) request
+ * fc_lport_scr_resp() - Handle response to State Change Register (SCR) request
* @sp: current sequence in SCR exchange
* @fp: response frame
* @lp_arg: Fibre Channel lport port instance that sent the registration request
@@ -1155,17 +1132,17 @@ static void fc_lport_scr_resp(struct fc_seq *sp, struct fc_frame *fp,
FC_DEBUG_LPORT("Received a SCR response\n");
+ if (IS_ERR(fp)) {
+ fc_lport_error(lport, fp);
+ goto err;
+ }
+
if (lport->state != LPORT_ST_SCR) {
FC_DBG("Received a SCR response, but in state %s\n",
fc_lport_state(lport));
goto out;
}
- if (IS_ERR(fp)) {
- fc_lport_error(lport, fp);
- goto err;
- }
-
op = fc_frame_payload_op(fp);
if (op == ELS_LS_ACC)
fc_lport_enter_ready(lport);
@@ -1179,7 +1156,7 @@ err:
}
/**
- * fc_lport_enter_scr - Send a State Change Register (SCR) request
+ * fc_lport_enter_scr() - Send a State Change Register (SCR) request
* @lport: Fibre Channel local port to register for state changes
*
* Locking Note: The lport lock is expected to be held before calling
@@ -1206,7 +1183,7 @@ static void fc_lport_enter_scr(struct fc_lport *lport)
}
/**
- * fc_lport_enter_rft_id - Register FC4-types with the name server
+ * fc_lport_enter_rft_id() - Register FC4-types with the name server
* @lport: Fibre Channel local port to register
*
* Locking Note: The lport lock is expected to be held before calling
@@ -1248,7 +1225,7 @@ static void fc_lport_enter_rft_id(struct fc_lport *lport)
}
/**
- * fc_rport_enter_rft_id - Register port name with the name server
+ * fc_rport_enter_rft_id() - Register port name with the name server
* @lport: Fibre Channel local port to register
*
* Locking Note: The lport lock is expected to be held before calling
@@ -1281,7 +1258,7 @@ static struct fc_rport_operations fc_lport_rport_ops = {
};
/**
- * fc_rport_enter_dns - Create a rport to the name server
+ * fc_rport_enter_dns() - Create a rport to the name server
* @lport: Fibre Channel local port requesting a rport for the name server
*
* Locking Note: The lport lock is expected to be held before calling
@@ -1304,7 +1281,7 @@ static void fc_lport_enter_dns(struct fc_lport *lport)
fc_lport_state_enter(lport, LPORT_ST_DNS);
- rport = fc_rport_rogue_create(&dp);
+ rport = lport->tt.rport_create(&dp);
if (!rport)
goto err;
@@ -1318,7 +1295,7 @@ err:
}
/**
- * fc_lport_timeout - Handler for the retry_work timer.
+ * fc_lport_timeout() - Handler for the retry_work timer.
* @work: The work struct of the fc_lport
*/
static void fc_lport_timeout(struct work_struct *work)
@@ -1359,7 +1336,7 @@ static void fc_lport_timeout(struct work_struct *work)
}
/**
- * fc_lport_logo_resp - Handle response to LOGO request
+ * fc_lport_logo_resp() - Handle response to LOGO request
* @sp: current sequence in LOGO exchange
* @fp: response frame
* @lp_arg: Fibre Channel lport port instance that sent the LOGO request
@@ -1381,17 +1358,17 @@ static void fc_lport_logo_resp(struct fc_seq *sp, struct fc_frame *fp,
FC_DEBUG_LPORT("Received a LOGO response\n");
+ if (IS_ERR(fp)) {
+ fc_lport_error(lport, fp);
+ goto err;
+ }
+
if (lport->state != LPORT_ST_LOGO) {
FC_DBG("Received a LOGO response, but in state %s\n",
fc_lport_state(lport));
goto out;
}
- if (IS_ERR(fp)) {
- fc_lport_error(lport, fp);
- goto err;
- }
-
op = fc_frame_payload_op(fp);
if (op == ELS_LS_ACC)
fc_lport_enter_reset(lport);
@@ -1405,7 +1382,7 @@ err:
}
/**
- * fc_rport_enter_logo - Logout of the fabric
+ * fc_rport_enter_logo() - Logout of the fabric
* @lport: Fibre Channel local port to be logged out
*
* Locking Note: The lport lock is expected to be held before calling
@@ -1437,7 +1414,7 @@ static void fc_lport_enter_logo(struct fc_lport *lport)
}
/**
- * fc_lport_flogi_resp - Handle response to FLOGI request
+ * fc_lport_flogi_resp() - Handle response to FLOGI request
* @sp: current sequence in FLOGI exchange
* @fp: response frame
* @lp_arg: Fibre Channel lport port instance that sent the FLOGI request
@@ -1465,17 +1442,17 @@ static void fc_lport_flogi_resp(struct fc_seq *sp, struct fc_frame *fp,
FC_DEBUG_LPORT("Received a FLOGI response\n");
+ if (IS_ERR(fp)) {
+ fc_lport_error(lport, fp);
+ goto err;
+ }
+
if (lport->state != LPORT_ST_FLOGI) {
FC_DBG("Received a FLOGI response, but in state %s\n",
fc_lport_state(lport));
goto out;
}
- if (IS_ERR(fp)) {
- fc_lport_error(lport, fp);
- goto err;
- }
-
fh = fc_frame_header_get(fp);
did = ntoh24(fh->fh_d_id);
if (fc_frame_payload_op(fp) == ELS_LS_ACC && did != 0) {
@@ -1532,7 +1509,7 @@ err:
}
/**
- * fc_rport_enter_flogi - Send a FLOGI request to the fabric manager
+ * fc_rport_enter_flogi() - Send a FLOGI request to the fabric manager
* @lport: Fibre Channel local port to be logged in to the fabric
*
* Locking Note: The lport lock is expected to be held before calling
diff --git a/drivers/scsi/libfc/fc_rport.c b/drivers/scsi/libfc/fc_rport.c
index e780d8caf70..dae65133a83 100644
--- a/drivers/scsi/libfc/fc_rport.c
+++ b/drivers/scsi/libfc/fc_rport.c
@@ -81,6 +81,7 @@ static void fc_rport_recv_logo_req(struct fc_rport *,
struct fc_seq *, struct fc_frame *);
static void fc_rport_timeout(struct work_struct *);
static void fc_rport_error(struct fc_rport *, struct fc_frame *);
+static void fc_rport_error_retry(struct fc_rport *, struct fc_frame *);
static void fc_rport_work(struct work_struct *);
static const char *fc_rport_state_names[] = {
@@ -145,7 +146,7 @@ struct fc_rport *fc_rport_rogue_create(struct fc_disc_port *dp)
}
/**
- * fc_rport_state - return a string for the state the rport is in
+ * fc_rport_state() - return a string for the state the rport is in
* @rport: The rport whose state we want to get a string for
*/
static const char *fc_rport_state(struct fc_rport *rport)
@@ -160,7 +161,7 @@ static const char *fc_rport_state(struct fc_rport *rport)
}
/**
- * fc_set_rport_loss_tmo - Set the remote port loss timeout in seconds.
+ * fc_set_rport_loss_tmo() - Set the remote port loss timeout in seconds.
* @rport: Pointer to Fibre Channel remote port structure
* @timeout: timeout in seconds
*/
@@ -174,12 +175,12 @@ void fc_set_rport_loss_tmo(struct fc_rport *rport, u32 timeout)
EXPORT_SYMBOL(fc_set_rport_loss_tmo);
/**
- * fc_plogi_get_maxframe - Get max payload from the common service parameters
+ * fc_plogi_get_maxframe() - Get max payload from the common service parameters
* @flp: FLOGI payload structure
* @maxval: upper limit, may be less than what is in the service parameters
*/
-static unsigned int
-fc_plogi_get_maxframe(struct fc_els_flogi *flp, unsigned int maxval)
+static unsigned int fc_plogi_get_maxframe(struct fc_els_flogi *flp,
+ unsigned int maxval)
{
unsigned int mfs;
@@ -197,7 +198,7 @@ fc_plogi_get_maxframe(struct fc_els_flogi *flp, unsigned int maxval)
}
/**
- * fc_rport_state_enter - Change the rport's state
+ * fc_rport_state_enter() - Change the rport's state
* @rport: The rport whose state should change
* @new: The new state of the rport
*
@@ -214,6 +215,7 @@ static void fc_rport_state_enter(struct fc_rport *rport,
static void fc_rport_work(struct work_struct *work)
{
+ u32 port_id;
struct fc_rport_libfc_priv *rdata =
container_of(work, struct fc_rport_libfc_priv, event_work);
enum fc_rport_event event;
@@ -279,14 +281,18 @@ static void fc_rport_work(struct work_struct *work)
rport_ops->event_callback(lport, rport, event);
if (trans_state == FC_PORTSTATE_ROGUE)
put_device(&rport->dev);
- else
+ else {
+ port_id = rport->port_id;
fc_remote_port_delete(rport);
+ lport->tt.exch_mgr_reset(lport, 0, port_id);
+ lport->tt.exch_mgr_reset(lport, port_id, 0);
+ }
} else
mutex_unlock(&rdata->rp_mutex);
}
/**
- * fc_rport_login - Start the remote port login state machine
+ * fc_rport_login() - Start the remote port login state machine
* @rport: Fibre Channel remote port
*
* Locking Note: Called without the rport lock held. This
@@ -309,7 +315,7 @@ int fc_rport_login(struct fc_rport *rport)
}
/**
- * fc_rport_logoff - Logoff and remove an rport
+ * fc_rport_logoff() - Logoff and remove an rport
* @rport: Fibre Channel remote port to be removed
*
* Locking Note: Called without the rport lock held. This
@@ -347,7 +353,7 @@ int fc_rport_logoff(struct fc_rport *rport)
}
/**
- * fc_rport_enter_ready - The rport is ready
+ * fc_rport_enter_ready() - The rport is ready
* @rport: Fibre Channel remote port that is ready
*
* Locking Note: The rport lock is expected to be held before calling
@@ -366,7 +372,7 @@ static void fc_rport_enter_ready(struct fc_rport *rport)
}
/**
- * fc_rport_timeout - Handler for the retry_work timer.
+ * fc_rport_timeout() - Handler for the retry_work timer.
* @work: The work struct of the fc_rport_libfc_priv
*
* Locking Note: Called without the rport lock held. This
@@ -405,59 +411,75 @@ static void fc_rport_timeout(struct work_struct *work)
}
/**
- * fc_rport_error - Handler for any errors
+ * fc_rport_error() - Error handler, called once retries have been exhausted
* @rport: The fc_rport object
* @fp: The frame pointer
*
- * If the error was caused by a resource allocation failure
- * then wait for half a second and retry, otherwise retry
- * immediately.
- *
* Locking Note: The rport lock is expected to be held before
* calling this routine
*/
static void fc_rport_error(struct fc_rport *rport, struct fc_frame *fp)
{
struct fc_rport_libfc_priv *rdata = rport->dd_data;
- unsigned long delay = 0;
FC_DEBUG_RPORT("Error %ld in state %s, retries %d\n",
PTR_ERR(fp), fc_rport_state(rport), rdata->retries);
- if (!fp || PTR_ERR(fp) == -FC_EX_TIMEOUT) {
- /*
- * Memory allocation failure, or the exchange timed out.
- * Retry after delay
- */
- if (rdata->retries < rdata->local_port->max_retry_count) {
- rdata->retries++;
- if (!fp)
- delay = msecs_to_jiffies(500);
- get_device(&rport->dev);
- schedule_delayed_work(&rdata->retry_work, delay);
- } else {
- switch (rdata->rp_state) {
- case RPORT_ST_PLOGI:
- case RPORT_ST_PRLI:
- case RPORT_ST_LOGO:
- rdata->event = RPORT_EV_FAILED;
- queue_work(rport_event_queue,
- &rdata->event_work);
- break;
- case RPORT_ST_RTV:
- fc_rport_enter_ready(rport);
- break;
- case RPORT_ST_NONE:
- case RPORT_ST_READY:
- case RPORT_ST_INIT:
- break;
- }
- }
+ switch (rdata->rp_state) {
+ case RPORT_ST_PLOGI:
+ case RPORT_ST_PRLI:
+ case RPORT_ST_LOGO:
+ rdata->event = RPORT_EV_FAILED;
+ queue_work(rport_event_queue,
+ &rdata->event_work);
+ break;
+ case RPORT_ST_RTV:
+ fc_rport_enter_ready(rport);
+ break;
+ case RPORT_ST_NONE:
+ case RPORT_ST_READY:
+ case RPORT_ST_INIT:
+ break;
}
}
/**
- * fc_rport_plogi_recv_resp - Handle incoming ELS PLOGI response
+ * fc_rport_error_retry() - Error handler when retries are desired
+ * @rport: The fc_rport object
+ * @fp: The frame pointer
+ *
+ * If the error was an exchange timeout retry immediately,
+ * otherwise wait for E_D_TOV.
+ *
+ * Locking Note: The rport lock is expected to be held before
+ * calling this routine
+ */
+static void fc_rport_error_retry(struct fc_rport *rport, struct fc_frame *fp)
+{
+ struct fc_rport_libfc_priv *rdata = rport->dd_data;
+ unsigned long delay = FC_DEF_E_D_TOV;
+
+ /* make sure this isn't an FC_EX_CLOSED error, never retry those */
+ if (PTR_ERR(fp) == -FC_EX_CLOSED)
+ return fc_rport_error(rport, fp);
+
+ if (rdata->retries < rdata->local_port->max_retry_count) {
+ FC_DEBUG_RPORT("Error %ld in state %s, retrying\n",
+ PTR_ERR(fp), fc_rport_state(rport));
+ rdata->retries++;
+ /* no additional delay on exchange timeouts */
+ if (PTR_ERR(fp) == -FC_EX_TIMEOUT)
+ delay = 0;
+ get_device(&rport->dev);
+ schedule_delayed_work(&rdata->retry_work, delay);
+ return;
+ }
+
+ return fc_rport_error(rport, fp);
+}
+
+/**
+ * fc_rport_plogi_recv_resp() - Handle incoming ELS PLOGI response
* @sp: current sequence in the PLOGI exchange
* @fp: response frame
* @rp_arg: Fibre Channel remote port
@@ -483,17 +505,17 @@ static void fc_rport_plogi_resp(struct fc_seq *sp, struct fc_frame *fp,
FC_DEBUG_RPORT("Received a PLOGI response from port (%6x)\n",
rport->port_id);
+ if (IS_ERR(fp)) {
+ fc_rport_error_retry(rport, fp);
+ goto err;
+ }
+
if (rdata->rp_state != RPORT_ST_PLOGI) {
FC_DBG("Received a PLOGI response, but in state %s\n",
fc_rport_state(rport));
goto out;
}
- if (IS_ERR(fp)) {
- fc_rport_error(rport, fp);
- goto err;
- }
-
op = fc_frame_payload_op(fp);
if (op == ELS_LS_ACC &&
(plp = fc_frame_payload_get(fp, sizeof(*plp))) != NULL) {
@@ -522,7 +544,7 @@ static void fc_rport_plogi_resp(struct fc_seq *sp, struct fc_frame *fp,
else
fc_rport_enter_prli(rport);
} else
- fc_rport_error(rport, fp);
+ fc_rport_error_retry(rport, fp);
out:
fc_frame_free(fp);
@@ -532,7 +554,7 @@ err:
}
/**
- * fc_rport_enter_plogi - Send Port Login (PLOGI) request to peer
+ * fc_rport_enter_plogi() - Send Port Login (PLOGI) request to peer
* @rport: Fibre Channel remote port to send PLOGI to
*
* Locking Note: The rport lock is expected to be held before calling
@@ -552,20 +574,20 @@ static void fc_rport_enter_plogi(struct fc_rport *rport)
rport->maxframe_size = FC_MIN_MAX_PAYLOAD;
fp = fc_frame_alloc(lport, sizeof(struct fc_els_flogi));
if (!fp) {
- fc_rport_error(rport, fp);
+ fc_rport_error_retry(rport, fp);
return;
}
rdata->e_d_tov = lport->e_d_tov;
if (!lport->tt.elsct_send(lport, rport, fp, ELS_PLOGI,
fc_rport_plogi_resp, rport, lport->e_d_tov))
- fc_rport_error(rport, fp);
+ fc_rport_error_retry(rport, fp);
else
get_device(&rport->dev);
}
/**
- * fc_rport_prli_resp - Process Login (PRLI) response handler
+ * fc_rport_prli_resp() - Process Login (PRLI) response handler
* @sp: current sequence in the PRLI exchange
* @fp: response frame
* @rp_arg: Fibre Channel remote port
@@ -592,17 +614,17 @@ static void fc_rport_prli_resp(struct fc_seq *sp, struct fc_frame *fp,
FC_DEBUG_RPORT("Received a PRLI response from port (%6x)\n",
rport->port_id);
+ if (IS_ERR(fp)) {
+ fc_rport_error_retry(rport, fp);
+ goto err;
+ }
+
if (rdata->rp_state != RPORT_ST_PRLI) {
FC_DBG("Received a PRLI response, but in state %s\n",
fc_rport_state(rport));
goto out;
}
- if (IS_ERR(fp)) {
- fc_rport_error(rport, fp);
- goto err;
- }
-
op = fc_frame_payload_op(fp);
if (op == ELS_LS_ACC) {
pp = fc_frame_payload_get(fp, sizeof(*pp));
@@ -635,7 +657,7 @@ err:
}
/**
- * fc_rport_logo_resp - Logout (LOGO) response handler
+ * fc_rport_logo_resp() - Logout (LOGO) response handler
* @sp: current sequence in the LOGO exchange
* @fp: response frame
* @rp_arg: Fibre Channel remote port
@@ -657,7 +679,7 @@ static void fc_rport_logo_resp(struct fc_seq *sp, struct fc_frame *fp,
rport->port_id);
if (IS_ERR(fp)) {
- fc_rport_error(rport, fp);
+ fc_rport_error_retry(rport, fp);
goto err;
}
@@ -684,7 +706,7 @@ err:
}
/**
- * fc_rport_enter_prli - Send Process Login (PRLI) request to peer
+ * fc_rport_enter_prli() - Send Process Login (PRLI) request to peer
* @rport: Fibre Channel remote port to send PRLI to
*
* Locking Note: The rport lock is expected to be held before calling
@@ -707,19 +729,19 @@ static void fc_rport_enter_prli(struct fc_rport *rport)
fp = fc_frame_alloc(lport, sizeof(*pp));
if (!fp) {
- fc_rport_error(rport, fp);
+ fc_rport_error_retry(rport, fp);
return;
}
if (!lport->tt.elsct_send(lport, rport, fp, ELS_PRLI,
fc_rport_prli_resp, rport, lport->e_d_tov))
- fc_rport_error(rport, fp);
+ fc_rport_error_retry(rport, fp);
else
get_device(&rport->dev);
}
/**
- * fc_rport_els_rtv_resp - Request Timeout Value response handler
+ * fc_rport_els_rtv_resp() - Request Timeout Value response handler
* @sp: current sequence in the RTV exchange
* @fp: response frame
* @rp_arg: Fibre Channel remote port
@@ -742,17 +764,17 @@ static void fc_rport_rtv_resp(struct fc_seq *sp, struct fc_frame *fp,
FC_DEBUG_RPORT("Received a RTV response from port (%6x)\n",
rport->port_id);
+ if (IS_ERR(fp)) {
+ fc_rport_error(rport, fp);
+ goto err;
+ }
+
if (rdata->rp_state != RPORT_ST_RTV) {
FC_DBG("Received a RTV response, but in state %s\n",
fc_rport_state(rport));
goto out;
}
- if (IS_ERR(fp)) {
- fc_rport_error(rport, fp);
- goto err;
- }
-
op = fc_frame_payload_op(fp);
if (op == ELS_LS_ACC) {
struct fc_els_rtv_acc *rtv;
@@ -785,7 +807,7 @@ err:
}
/**
- * fc_rport_enter_rtv - Send Request Timeout Value (RTV) request to peer
+ * fc_rport_enter_rtv() - Send Request Timeout Value (RTV) request to peer
* @rport: Fibre Channel remote port to send RTV to
*
* Locking Note: The rport lock is expected to be held before calling
@@ -804,19 +826,19 @@ static void fc_rport_enter_rtv(struct fc_rport *rport)
fp = fc_frame_alloc(lport, sizeof(struct fc_els_rtv));
if (!fp) {
- fc_rport_error(rport, fp);
+ fc_rport_error_retry(rport, fp);
return;
}
if (!lport->tt.elsct_send(lport, rport, fp, ELS_RTV,
fc_rport_rtv_resp, rport, lport->e_d_tov))
- fc_rport_error(rport, fp);
+ fc_rport_error_retry(rport, fp);
else
get_device(&rport->dev);
}
/**
- * fc_rport_enter_logo - Send Logout (LOGO) request to peer
+ * fc_rport_enter_logo() - Send Logout (LOGO) request to peer
* @rport: Fibre Channel remote port to send LOGO to
*
* Locking Note: The rport lock is expected to be held before calling
@@ -835,20 +857,20 @@ static void fc_rport_enter_logo(struct fc_rport *rport)
fp = fc_frame_alloc(lport, sizeof(struct fc_els_logo));
if (!fp) {
- fc_rport_error(rport, fp);
+ fc_rport_error_retry(rport, fp);
return;
}
if (!lport->tt.elsct_send(lport, rport, fp, ELS_LOGO,
fc_rport_logo_resp, rport, lport->e_d_tov))
- fc_rport_error(rport, fp);
+ fc_rport_error_retry(rport, fp);
else
get_device(&rport->dev);
}
/**
- * fc_rport_recv_req - Receive a request from a rport
+ * fc_rport_recv_req() - Receive a request from a rport
* @sp: current sequence in the PLOGI exchange
* @fp: response frame
* @rp_arg: Fibre Channel remote port
@@ -909,7 +931,7 @@ void fc_rport_recv_req(struct fc_seq *sp, struct fc_frame *fp,
}
/**
- * fc_rport_recv_plogi_req - Handle incoming Port Login (PLOGI) request
+ * fc_rport_recv_plogi_req() - Handle incoming Port Login (PLOGI) request
* @rport: Fibre Channel remote port that initiated PLOGI
* @sp: current sequence in the PLOGI exchange
* @fp: PLOGI request frame
@@ -1031,7 +1053,7 @@ static void fc_rport_recv_plogi_req(struct fc_rport *rport,
}
/**
- * fc_rport_recv_prli_req - Handle incoming Process Login (PRLI) request
+ * fc_rport_recv_prli_req() - Handle incoming Process Login (PRLI) request
* @rport: Fibre Channel remote port that initiated PRLI
* @sp: current sequence in the PRLI exchange
* @fp: PRLI request frame
@@ -1182,7 +1204,7 @@ static void fc_rport_recv_prli_req(struct fc_rport *rport,
}
/**
- * fc_rport_recv_prlo_req - Handle incoming Process Logout (PRLO) request
+ * fc_rport_recv_prlo_req() - Handle incoming Process Logout (PRLO) request
* @rport: Fibre Channel remote port that initiated PRLO
* @sp: current sequence in the PRLO exchange
* @fp: PRLO request frame
@@ -1213,7 +1235,7 @@ static void fc_rport_recv_prlo_req(struct fc_rport *rport, struct fc_seq *sp,
}
/**
- * fc_rport_recv_logo_req - Handle incoming Logout (LOGO) request
+ * fc_rport_recv_logo_req() - Handle incoming Logout (LOGO) request
* @rport: Fibre Channel remote port that initiated LOGO
* @sp: current sequence in the LOGO exchange
* @fp: LOGO request frame
@@ -1249,6 +1271,9 @@ static void fc_rport_flush_queue(void)
int fc_rport_init(struct fc_lport *lport)
{
+ if (!lport->tt.rport_create)
+ lport->tt.rport_create = fc_rport_rogue_create;
+
if (!lport->tt.rport_login)
lport->tt.rport_login = fc_rport_login;
@@ -1285,7 +1310,7 @@ void fc_rport_terminate_io(struct fc_rport *rport)
struct fc_rport_libfc_priv *rdata = rport->dd_data;
struct fc_lport *lport = rdata->local_port;
- lport->tt.exch_mgr_reset(lport->emp, 0, rport->port_id);
- lport->tt.exch_mgr_reset(lport->emp, rport->port_id, 0);
+ lport->tt.exch_mgr_reset(lport, 0, rport->port_id);
+ lport->tt.exch_mgr_reset(lport, rport->port_id, 0);
}
EXPORT_SYMBOL(fc_rport_terminate_io);
diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c
index f4c57227ec1..ee9d4015243 100644
--- a/drivers/scsi/qla2xxx/qla_attr.c
+++ b/drivers/scsi/qla2xxx/qla_attr.c
@@ -244,12 +244,6 @@ qla2x00_sysfs_write_optrom_ctl(struct kobject *kobj,
if (ha->optrom_state != QLA_SWAITING)
break;
- if (start & 0xfff) {
- qla_printk(KERN_WARNING, ha,
- "Invalid start region 0x%x/0x%x.\n", start, size);
- return -EINVAL;
- }
-
ha->optrom_region_start = start;
ha->optrom_region_size = start + size > ha->optrom_size ?
ha->optrom_size - start : size;
@@ -303,8 +297,7 @@ qla2x00_sysfs_write_optrom_ctl(struct kobject *kobj,
else if (start == (ha->flt_region_boot * 4) ||
start == (ha->flt_region_fw * 4))
valid = 1;
- else if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) &&
- start == (ha->flt_region_vpd_nvram * 4))
+ else if (IS_QLA25XX(ha) || IS_QLA81XX(ha))
valid = 1;
if (!valid) {
qla_printk(KERN_WARNING, ha,
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index 986501759ad..87f9abc7146 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -1308,8 +1308,12 @@ qla2x00_init_rings(scsi_qla_host_t *vha)
DEBUG(printk("scsi(%ld): Issue init firmware.\n", vha->host_no));
- if (ha->flags.npiv_supported)
+ if (ha->flags.npiv_supported) {
+ if (ha->operating_mode == LOOP)
+ ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
+ }
+
mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
@@ -2610,6 +2614,7 @@ qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
port_id_t wrap, nxt_d_id;
struct qla_hw_data *ha = vha->hw;
struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
+ struct scsi_qla_host *tvp;
rval = QLA_SUCCESS;
@@ -2709,7 +2714,7 @@ qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
/* Bypass virtual ports of the same host. */
found = 0;
if (ha->num_vhosts) {
- list_for_each_entry(vp, &ha->vp_list, list) {
+ list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
if (new_fcport->d_id.b24 == vp->d_id.b24) {
found = 1;
break;
@@ -2832,6 +2837,7 @@ qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
uint16_t first_loop_id;
struct qla_hw_data *ha = vha->hw;
struct scsi_qla_host *vp;
+ struct scsi_qla_host *tvp;
rval = QLA_SUCCESS;
@@ -2856,7 +2862,7 @@ qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
/* Check for loop ID being already in use. */
found = 0;
fcport = NULL;
- list_for_each_entry(vp, &ha->vp_list, list) {
+ list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
list_for_each_entry(fcport, &vp->vp_fcports, list) {
if (fcport->loop_id == dev->loop_id &&
fcport != dev) {
@@ -3291,6 +3297,7 @@ qla2x00_abort_isp(scsi_qla_host_t *vha)
uint8_t status = 0;
struct qla_hw_data *ha = vha->hw;
struct scsi_qla_host *vp;
+ struct scsi_qla_host *tvp;
struct req_que *req = ha->req_q_map[0];
if (vha->flags.online) {
@@ -3306,7 +3313,7 @@ qla2x00_abort_isp(scsi_qla_host_t *vha)
if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
atomic_set(&vha->loop_state, LOOP_DOWN);
qla2x00_mark_all_devices_lost(vha, 0);
- list_for_each_entry(vp, &ha->vp_list, list)
+ list_for_each_entry_safe(vp, tvp, &ha->vp_list, list)
qla2x00_mark_all_devices_lost(vp, 0);
} else {
if (!atomic_read(&vha->loop_down_timer))
@@ -3403,7 +3410,7 @@ qla2x00_abort_isp(scsi_qla_host_t *vha)
DEBUG(printk(KERN_INFO
"qla2x00_abort_isp(%ld): succeeded.\n",
vha->host_no));
- list_for_each_entry(vp, &ha->vp_list, list) {
+ list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
if (vp->vp_idx)
qla2x00_vp_abort_isp(vp);
}
@@ -3428,7 +3435,7 @@ qla2x00_abort_isp(scsi_qla_host_t *vha)
static int
qla2x00_restart_isp(scsi_qla_host_t *vha)
{
- uint8_t status = 0;
+ int status = 0;
uint32_t wait_time;
struct qla_hw_data *ha = vha->hw;
struct req_que *req = ha->req_q_map[0];
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c
index 4c7504cb399..4aab7acf752 100644
--- a/drivers/scsi/qla2xxx/qla_mbx.c
+++ b/drivers/scsi/qla2xxx/qla_mbx.c
@@ -2685,6 +2685,7 @@ qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
struct qla_hw_data *ha = vha->hw;
scsi_qla_host_t *vp;
+ scsi_qla_host_t *tvp;
if (rptid_entry->entry_status != 0)
return;
@@ -2710,7 +2711,7 @@ qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
if (MSB(stat) == 1)
return;
- list_for_each_entry(vp, &ha->vp_list, list)
+ list_for_each_entry_safe(vp, tvp, &ha->vp_list, list)
if (vp_idx == vp->vp_idx)
break;
if (!vp)
diff --git a/drivers/scsi/qla2xxx/qla_mid.c b/drivers/scsi/qla2xxx/qla_mid.c
index 3f23932210c..785c61279e6 100644
--- a/drivers/scsi/qla2xxx/qla_mid.c
+++ b/drivers/scsi/qla2xxx/qla_mid.c
@@ -69,9 +69,10 @@ static scsi_qla_host_t *
qla24xx_find_vhost_by_name(struct qla_hw_data *ha, uint8_t *port_name)
{
scsi_qla_host_t *vha;
+ struct scsi_qla_host *tvha;
/* Locate matching device in database. */
- list_for_each_entry(vha, &ha->vp_list, list) {
+ list_for_each_entry_safe(vha, tvha, &ha->vp_list, list) {
if (!memcmp(port_name, vha->port_name, WWN_SIZE))
return vha;
}
@@ -194,11 +195,11 @@ qla24xx_configure_vp(scsi_qla_host_t *vha)
void
qla2x00_alert_all_vps(struct rsp_que *rsp, uint16_t *mb)
{
- scsi_qla_host_t *vha;
+ scsi_qla_host_t *vha, *tvha;
struct qla_hw_data *ha = rsp->hw;
int i = 0;
- list_for_each_entry(vha, &ha->vp_list, list) {
+ list_for_each_entry_safe(vha, tvha, &ha->vp_list, list) {
if (vha->vp_idx) {
switch (mb[0]) {
case MBA_LIP_OCCURRED:
@@ -300,6 +301,7 @@ qla2x00_do_dpc_all_vps(scsi_qla_host_t *vha)
int ret;
struct qla_hw_data *ha = vha->hw;
scsi_qla_host_t *vp;
+ struct scsi_qla_host *tvp;
if (vha->vp_idx)
return;
@@ -308,7 +310,7 @@ qla2x00_do_dpc_all_vps(scsi_qla_host_t *vha)
clear_bit(VP_DPC_NEEDED, &vha->dpc_flags);
- list_for_each_entry(vp, &ha->vp_list, list) {
+ list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
if (vp->vp_idx)
ret = qla2x00_do_dpc_vp(vp);
}
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index 2f5f72531e2..3ddfa889e94 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -2222,10 +2222,6 @@ qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
{
char name[16];
- ha->init_cb_size = sizeof(init_cb_t);
- if (IS_QLA2XXX_MIDTYPE(ha))
- ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
-
ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
&ha->init_cb_dma, GFP_KERNEL);
if (!ha->init_cb)
@@ -2568,7 +2564,7 @@ qla2x00_do_work(struct scsi_qla_host *vha)
void qla2x00_relogin(struct scsi_qla_host *vha)
{
fc_port_t *fcport;
- uint8_t status;
+ int status;
uint16_t next_loopid = 0;
struct qla_hw_data *ha = vha->hw;
diff --git a/drivers/scsi/qla2xxx/qla_version.h b/drivers/scsi/qla2xxx/qla_version.h
index 79f7053da99..a772eab2f0e 100644
--- a/drivers/scsi/qla2xxx/qla_version.h
+++ b/drivers/scsi/qla2xxx/qla_version.h
@@ -7,7 +7,7 @@
/*
* Driver version
*/
-#define QLA2XXX_VERSION "8.03.00-k3"
+#define QLA2XXX_VERSION "8.03.00-k4"
#define QLA_DRIVER_MAJOR_VER 8
#define QLA_DRIVER_MINOR_VER 3
diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c
index 55310dbc10a..4970ae4a62d 100644
--- a/drivers/scsi/sd.c
+++ b/drivers/scsi/sd.c
@@ -1167,23 +1167,19 @@ sd_spinup_disk(struct scsi_disk *sdkp)
/*
* The device does not want the automatic start to be issued.
*/
- if (sdkp->device->no_start_on_add) {
+ if (sdkp->device->no_start_on_add)
break;
- }
-
- /*
- * If manual intervention is required, or this is an
- * absent USB storage device, a spinup is meaningless.
- */
- if (sense_valid &&
- sshdr.sense_key == NOT_READY &&
- sshdr.asc == 4 && sshdr.ascq == 3) {
- break; /* manual intervention required */
- /*
- * Issue command to spin up drive when not ready
- */
- } else if (sense_valid && sshdr.sense_key == NOT_READY) {
+ if (sense_valid && sshdr.sense_key == NOT_READY) {
+ if (sshdr.asc == 4 && sshdr.ascq == 3)
+ break; /* manual intervention required */
+ if (sshdr.asc == 4 && sshdr.ascq == 0xb)
+ break; /* standby */
+ if (sshdr.asc == 4 && sshdr.ascq == 0xc)
+ break; /* unavailable */
+ /*
+ * Issue command to spin up drive when not ready
+ */
if (!spintime) {
sd_printk(KERN_NOTICE, sdkp, "Spinning up disk...");
cmd[0] = START_STOP;
diff --git a/drivers/scsi/zalon.c b/drivers/scsi/zalon.c
index a8d61a62522..97f3158fa7b 100644
--- a/drivers/scsi/zalon.c
+++ b/drivers/scsi/zalon.c
@@ -137,7 +137,7 @@ zalon_probe(struct parisc_device *dev)
goto fail;
if (request_irq(dev->irq, ncr53c8xx_intr, IRQF_SHARED, "zalon", host)) {
- dev_printk(KERN_ERR, dev, "irq problem with %d, detaching\n ",
+ dev_printk(KERN_ERR, &dev->dev, "irq problem with %d, detaching\n ",
dev->irq);
goto fail;
}
diff --git a/drivers/video/logo/logo_linux_clut224.ppm b/drivers/video/logo/logo_linux_clut224.ppm
index 3c14e43b82f..de93ff3fc1a 100644
--- a/drivers/video/logo/logo_linux_clut224.ppm
+++ b/drivers/video/logo/logo_linux_clut224.ppm
@@ -1,1604 +1,2828 @@
P3
-# Standard 224-color Linux logo
-80 80
+145 113
255
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 6 6 6 6 6 6 10 10 10 10 10 10
- 10 10 10 6 6 6 6 6 6 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 6 6 6 10 10 10 14 14 14
- 22 22 22 26 26 26 30 30 30 34 34 34
- 30 30 30 30 30 30 26 26 26 18 18 18
- 14 14 14 10 10 10 6 6 6 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 1 0 0 1 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 6 6 6 14 14 14 26 26 26 42 42 42
- 54 54 54 66 66 66 78 78 78 78 78 78
- 78 78 78 74 74 74 66 66 66 54 54 54
- 42 42 42 26 26 26 18 18 18 10 10 10
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 1 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 22 22 22 42 42 42 66 66 66 86 86 86
- 66 66 66 38 38 38 38 38 38 22 22 22
- 26 26 26 34 34 34 54 54 54 66 66 66
- 86 86 86 70 70 70 46 46 46 26 26 26
- 14 14 14 6 6 6 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 1 0 0 1 0 0 1 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 10 10 10 26 26 26
- 50 50 50 82 82 82 58 58 58 6 6 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 6 6 6 54 54 54 86 86 86 66 66 66
- 38 38 38 18 18 18 6 6 6 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 6 6 6 22 22 22 50 50 50
- 78 78 78 34 34 34 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 6 6 6 70 70 70
- 78 78 78 46 46 46 22 22 22 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 1 0 0 1 0 0 1 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 6 6 6 18 18 18 42 42 42 82 82 82
- 26 26 26 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 14 14 14
- 46 46 46 34 34 34 6 6 6 2 2 6
- 42 42 42 78 78 78 42 42 42 18 18 18
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 1 0 0 0 0 0 1 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 10 10 10 30 30 30 66 66 66 58 58 58
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 26 26 26
- 86 86 86 101 101 101 46 46 46 10 10 10
- 2 2 6 58 58 58 70 70 70 34 34 34
- 10 10 10 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 1 0 0 1 0 0 1 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 14 14 14 42 42 42 86 86 86 10 10 10
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 30 30 30
- 94 94 94 94 94 94 58 58 58 26 26 26
- 2 2 6 6 6 6 78 78 78 54 54 54
- 22 22 22 6 6 6 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 6 6 6
- 22 22 22 62 62 62 62 62 62 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 26 26 26
- 54 54 54 38 38 38 18 18 18 10 10 10
- 2 2 6 2 2 6 34 34 34 82 82 82
- 38 38 38 14 14 14 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 1 0 0 1 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 6 6 6
- 30 30 30 78 78 78 30 30 30 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 10 10 10
- 10 10 10 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 78 78 78
- 50 50 50 18 18 18 6 6 6 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 1 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 38 38 38 86 86 86 14 14 14 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 54 54 54
- 66 66 66 26 26 26 6 6 6 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 1 0 0 1 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 14 14 14
- 42 42 42 82 82 82 2 2 6 2 2 6
- 2 2 6 6 6 6 10 10 10 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 6 6 6
- 14 14 14 10 10 10 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 18 18 18
- 82 82 82 34 34 34 10 10 10 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 1 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 14 14 14
- 46 46 46 86 86 86 2 2 6 2 2 6
- 6 6 6 6 6 6 22 22 22 34 34 34
- 6 6 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 18 18 18 34 34 34
- 10 10 10 50 50 50 22 22 22 2 2 6
- 2 2 6 2 2 6 2 2 6 10 10 10
- 86 86 86 42 42 42 14 14 14 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 1 0 0 1 0 0 1 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 14 14 14
- 46 46 46 86 86 86 2 2 6 2 2 6
- 38 38 38 116 116 116 94 94 94 22 22 22
- 22 22 22 2 2 6 2 2 6 2 2 6
- 14 14 14 86 86 86 138 138 138 162 162 162
-154 154 154 38 38 38 26 26 26 6 6 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 86 86 86 46 46 46 14 14 14 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 14 14 14
- 46 46 46 86 86 86 2 2 6 14 14 14
-134 134 134 198 198 198 195 195 195 116 116 116
- 10 10 10 2 2 6 2 2 6 6 6 6
-101 98 89 187 187 187 210 210 210 218 218 218
-214 214 214 134 134 134 14 14 14 6 6 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 86 86 86 50 50 50 18 18 18 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 1 0 0 0
- 0 0 1 0 0 1 0 0 1 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 14 14 14
- 46 46 46 86 86 86 2 2 6 54 54 54
-218 218 218 195 195 195 226 226 226 246 246 246
- 58 58 58 2 2 6 2 2 6 30 30 30
-210 210 210 253 253 253 174 174 174 123 123 123
-221 221 221 234 234 234 74 74 74 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 70 70 70 58 58 58 22 22 22 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 14 14 14
- 46 46 46 82 82 82 2 2 6 106 106 106
-170 170 170 26 26 26 86 86 86 226 226 226
-123 123 123 10 10 10 14 14 14 46 46 46
-231 231 231 190 190 190 6 6 6 70 70 70
- 90 90 90 238 238 238 158 158 158 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 70 70 70 58 58 58 22 22 22 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 1 0 0 0
- 0 0 1 0 0 1 0 0 1 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 14 14 14
- 42 42 42 86 86 86 6 6 6 116 116 116
-106 106 106 6 6 6 70 70 70 149 149 149
-128 128 128 18 18 18 38 38 38 54 54 54
-221 221 221 106 106 106 2 2 6 14 14 14
- 46 46 46 190 190 190 198 198 198 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 74 74 74 62 62 62 22 22 22 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 1 0 0 0
- 0 0 1 0 0 0 0 0 1 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 14 14 14
- 42 42 42 94 94 94 14 14 14 101 101 101
-128 128 128 2 2 6 18 18 18 116 116 116
-118 98 46 121 92 8 121 92 8 98 78 10
-162 162 162 106 106 106 2 2 6 2 2 6
- 2 2 6 195 195 195 195 195 195 6 6 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 74 74 74 62 62 62 22 22 22 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 1 0 0 1
- 0 0 1 0 0 0 0 0 1 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 38 38 38 90 90 90 14 14 14 58 58 58
-210 210 210 26 26 26 54 38 6 154 114 10
-226 170 11 236 186 11 225 175 15 184 144 12
-215 174 15 175 146 61 37 26 9 2 2 6
- 70 70 70 246 246 246 138 138 138 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 70 70 70 66 66 66 26 26 26 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 38 38 38 86 86 86 14 14 14 10 10 10
-195 195 195 188 164 115 192 133 9 225 175 15
-239 182 13 234 190 10 232 195 16 232 200 30
-245 207 45 241 208 19 232 195 16 184 144 12
-218 194 134 211 206 186 42 42 42 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 50 50 50 74 74 74 30 30 30 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 34 34 34 86 86 86 14 14 14 2 2 6
-121 87 25 192 133 9 219 162 10 239 182 13
-236 186 11 232 195 16 241 208 19 244 214 54
-246 218 60 246 218 38 246 215 20 241 208 19
-241 208 19 226 184 13 121 87 25 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 50 50 50 82 82 82 34 34 34 10 10 10
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 34 34 34 82 82 82 30 30 30 61 42 6
-180 123 7 206 145 10 230 174 11 239 182 13
-234 190 10 238 202 15 241 208 19 246 218 74
-246 218 38 246 215 20 246 215 20 246 215 20
-226 184 13 215 174 15 184 144 12 6 6 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 26 26 26 94 94 94 42 42 42 14 14 14
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 30 30 30 78 78 78 50 50 50 104 69 6
-192 133 9 216 158 10 236 178 12 236 186 11
-232 195 16 241 208 19 244 214 54 245 215 43
-246 215 20 246 215 20 241 208 19 198 155 10
-200 144 11 216 158 10 156 118 10 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 6 6 6 90 90 90 54 54 54 18 18 18
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 30 30 30 78 78 78 46 46 46 22 22 22
-137 92 6 210 162 10 239 182 13 238 190 10
-238 202 15 241 208 19 246 215 20 246 215 20
-241 208 19 203 166 17 185 133 11 210 150 10
-216 158 10 210 150 10 102 78 10 2 2 6
- 6 6 6 54 54 54 14 14 14 2 2 6
- 2 2 6 62 62 62 74 74 74 30 30 30
- 10 10 10 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 34 34 34 78 78 78 50 50 50 6 6 6
- 94 70 30 139 102 15 190 146 13 226 184 13
-232 200 30 232 195 16 215 174 15 190 146 13
-168 122 10 192 133 9 210 150 10 213 154 11
-202 150 34 182 157 106 101 98 89 2 2 6
- 2 2 6 78 78 78 116 116 116 58 58 58
- 2 2 6 22 22 22 90 90 90 46 46 46
- 18 18 18 6 6 6 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 38 38 38 86 86 86 50 50 50 6 6 6
-128 128 128 174 154 114 156 107 11 168 122 10
-198 155 10 184 144 12 197 138 11 200 144 11
-206 145 10 206 145 10 197 138 11 188 164 115
-195 195 195 198 198 198 174 174 174 14 14 14
- 2 2 6 22 22 22 116 116 116 116 116 116
- 22 22 22 2 2 6 74 74 74 70 70 70
- 30 30 30 10 10 10 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 6 6 6 18 18 18
- 50 50 50 101 101 101 26 26 26 10 10 10
-138 138 138 190 190 190 174 154 114 156 107 11
-197 138 11 200 144 11 197 138 11 192 133 9
-180 123 7 190 142 34 190 178 144 187 187 187
-202 202 202 221 221 221 214 214 214 66 66 66
- 2 2 6 2 2 6 50 50 50 62 62 62
- 6 6 6 2 2 6 10 10 10 90 90 90
- 50 50 50 18 18 18 6 6 6 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 10 10 10 34 34 34
- 74 74 74 74 74 74 2 2 6 6 6 6
-144 144 144 198 198 198 190 190 190 178 166 146
-154 121 60 156 107 11 156 107 11 168 124 44
-174 154 114 187 187 187 190 190 190 210 210 210
-246 246 246 253 253 253 253 253 253 182 182 182
- 6 6 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 62 62 62
- 74 74 74 34 34 34 14 14 14 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 10 10 10 22 22 22 54 54 54
- 94 94 94 18 18 18 2 2 6 46 46 46
-234 234 234 221 221 221 190 190 190 190 190 190
-190 190 190 187 187 187 187 187 187 190 190 190
-190 190 190 195 195 195 214 214 214 242 242 242
-253 253 253 253 253 253 253 253 253 253 253 253
- 82 82 82 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 14 14 14
- 86 86 86 54 54 54 22 22 22 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 6 6 6 18 18 18 46 46 46 90 90 90
- 46 46 46 18 18 18 6 6 6 182 182 182
-253 253 253 246 246 246 206 206 206 190 190 190
-190 190 190 190 190 190 190 190 190 190 190 190
-206 206 206 231 231 231 250 250 250 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-202 202 202 14 14 14 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 42 42 42 86 86 86 42 42 42 18 18 18
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 6 6 6
- 14 14 14 38 38 38 74 74 74 66 66 66
- 2 2 6 6 6 6 90 90 90 250 250 250
-253 253 253 253 253 253 238 238 238 198 198 198
-190 190 190 190 190 190 195 195 195 221 221 221
-246 246 246 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 82 82 82 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 78 78 78 70 70 70 34 34 34
- 14 14 14 6 6 6 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 14 14 14
- 34 34 34 66 66 66 78 78 78 6 6 6
- 2 2 6 18 18 18 218 218 218 253 253 253
-253 253 253 253 253 253 253 253 253 246 246 246
-226 226 226 231 231 231 246 246 246 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 178 178 178 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 18 18 18 90 90 90 62 62 62
- 30 30 30 10 10 10 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 10 10 10 26 26 26
- 58 58 58 90 90 90 18 18 18 2 2 6
- 2 2 6 110 110 110 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-250 250 250 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 231 231 231 18 18 18 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 18 18 18 94 94 94
- 54 54 54 26 26 26 10 10 10 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 6 6 6 22 22 22 50 50 50
- 90 90 90 26 26 26 2 2 6 2 2 6
- 14 14 14 195 195 195 250 250 250 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-250 250 250 242 242 242 54 54 54 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 38 38 38
- 86 86 86 50 50 50 22 22 22 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 6 6 6 14 14 14 38 38 38 82 82 82
- 34 34 34 2 2 6 2 2 6 2 2 6
- 42 42 42 195 195 195 246 246 246 253 253 253
-253 253 253 253 253 253 253 253 253 250 250 250
-242 242 242 242 242 242 250 250 250 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 250 250 250 246 246 246 238 238 238
-226 226 226 231 231 231 101 101 101 6 6 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 38 38 38 82 82 82 42 42 42 14 14 14
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 10 10 10 26 26 26 62 62 62 66 66 66
- 2 2 6 2 2 6 2 2 6 6 6 6
- 70 70 70 170 170 170 206 206 206 234 234 234
-246 246 246 250 250 250 250 250 250 238 238 238
-226 226 226 231 231 231 238 238 238 250 250 250
-250 250 250 250 250 250 246 246 246 231 231 231
-214 214 214 206 206 206 202 202 202 202 202 202
-198 198 198 202 202 202 182 182 182 18 18 18
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 62 62 62 66 66 66 30 30 30
- 10 10 10 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 14 14 14 42 42 42 82 82 82 18 18 18
- 2 2 6 2 2 6 2 2 6 10 10 10
- 94 94 94 182 182 182 218 218 218 242 242 242
-250 250 250 253 253 253 253 253 253 250 250 250
-234 234 234 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 246 246 246
-238 238 238 226 226 226 210 210 210 202 202 202
-195 195 195 195 195 195 210 210 210 158 158 158
- 6 6 6 14 14 14 50 50 50 14 14 14
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 6 6 6 86 86 86 46 46 46
- 18 18 18 6 6 6 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 6 6 6
- 22 22 22 54 54 54 70 70 70 2 2 6
- 2 2 6 10 10 10 2 2 6 22 22 22
-166 166 166 231 231 231 250 250 250 253 253 253
-253 253 253 253 253 253 253 253 253 250 250 250
-242 242 242 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 246 246 246
-231 231 231 206 206 206 198 198 198 226 226 226
- 94 94 94 2 2 6 6 6 6 38 38 38
- 30 30 30 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 62 62 62 66 66 66
- 26 26 26 10 10 10 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 30 30 30 74 74 74 50 50 50 2 2 6
- 26 26 26 26 26 26 2 2 6 106 106 106
-238 238 238 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 246 246 246 218 218 218 202 202 202
-210 210 210 14 14 14 2 2 6 2 2 6
- 30 30 30 22 22 22 2 2 6 2 2 6
- 2 2 6 2 2 6 18 18 18 86 86 86
- 42 42 42 14 14 14 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 14 14 14
- 42 42 42 90 90 90 22 22 22 2 2 6
- 42 42 42 2 2 6 18 18 18 218 218 218
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 250 250 250 221 221 221
-218 218 218 101 101 101 2 2 6 14 14 14
- 18 18 18 38 38 38 10 10 10 2 2 6
- 2 2 6 2 2 6 2 2 6 78 78 78
- 58 58 58 22 22 22 6 6 6 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 6 6 6 18 18 18
- 54 54 54 82 82 82 2 2 6 26 26 26
- 22 22 22 2 2 6 123 123 123 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 250 250 250
-238 238 238 198 198 198 6 6 6 38 38 38
- 58 58 58 26 26 26 38 38 38 2 2 6
- 2 2 6 2 2 6 2 2 6 46 46 46
- 78 78 78 30 30 30 10 10 10 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 10 10 10 30 30 30
- 74 74 74 58 58 58 2 2 6 42 42 42
- 2 2 6 22 22 22 231 231 231 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 250 250 250
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 246 246 246 46 46 46 38 38 38
- 42 42 42 14 14 14 38 38 38 14 14 14
- 2 2 6 2 2 6 2 2 6 6 6 6
- 86 86 86 46 46 46 14 14 14 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 6 6 6 14 14 14 42 42 42
- 90 90 90 18 18 18 18 18 18 26 26 26
- 2 2 6 116 116 116 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 250 250 250 238 238 238
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 94 94 94 6 6 6
- 2 2 6 2 2 6 10 10 10 34 34 34
- 2 2 6 2 2 6 2 2 6 2 2 6
- 74 74 74 58 58 58 22 22 22 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 10 10 10 26 26 26 66 66 66
- 82 82 82 2 2 6 38 38 38 6 6 6
- 14 14 14 210 210 210 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 246 246 246 242 242 242
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 144 144 144 2 2 6
- 2 2 6 2 2 6 2 2 6 46 46 46
- 2 2 6 2 2 6 2 2 6 2 2 6
- 42 42 42 74 74 74 30 30 30 10 10 10
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 6 6 6 14 14 14 42 42 42 90 90 90
- 26 26 26 6 6 6 42 42 42 2 2 6
- 74 74 74 250 250 250 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 242 242 242 242 242 242
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 182 182 182 2 2 6
- 2 2 6 2 2 6 2 2 6 46 46 46
- 2 2 6 2 2 6 2 2 6 2 2 6
- 10 10 10 86 86 86 38 38 38 10 10 10
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 10 10 10 26 26 26 66 66 66 82 82 82
- 2 2 6 22 22 22 18 18 18 2 2 6
-149 149 149 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 234 234 234 242 242 242
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 206 206 206 2 2 6
- 2 2 6 2 2 6 2 2 6 38 38 38
- 2 2 6 2 2 6 2 2 6 2 2 6
- 6 6 6 86 86 86 46 46 46 14 14 14
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 6 6 6
- 18 18 18 46 46 46 86 86 86 18 18 18
- 2 2 6 34 34 34 10 10 10 6 6 6
-210 210 210 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 234 234 234 242 242 242
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 221 221 221 6 6 6
- 2 2 6 2 2 6 6 6 6 30 30 30
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 82 82 82 54 54 54 18 18 18
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 26 26 26 66 66 66 62 62 62 2 2 6
- 2 2 6 38 38 38 10 10 10 26 26 26
-238 238 238 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 231 231 231 238 238 238
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 231 231 231 6 6 6
- 2 2 6 2 2 6 10 10 10 30 30 30
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 66 66 66 58 58 58 22 22 22
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 38 38 38 78 78 78 6 6 6 2 2 6
- 2 2 6 46 46 46 14 14 14 42 42 42
-246 246 246 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 231 231 231 242 242 242
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 234 234 234 10 10 10
- 2 2 6 2 2 6 22 22 22 14 14 14
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 66 66 66 62 62 62 22 22 22
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 6 6 6 18 18 18
- 50 50 50 74 74 74 2 2 6 2 2 6
- 14 14 14 70 70 70 34 34 34 62 62 62
-250 250 250 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 231 231 231 246 246 246
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 234 234 234 14 14 14
- 2 2 6 2 2 6 30 30 30 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 66 66 66 62 62 62 22 22 22
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 6 6 6 18 18 18
- 54 54 54 62 62 62 2 2 6 2 2 6
- 2 2 6 30 30 30 46 46 46 70 70 70
-250 250 250 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 231 231 231 246 246 246
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 226 226 226 10 10 10
- 2 2 6 6 6 6 30 30 30 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 66 66 66 58 58 58 22 22 22
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 6 6 6 22 22 22
- 58 58 58 62 62 62 2 2 6 2 2 6
- 2 2 6 2 2 6 30 30 30 78 78 78
-250 250 250 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 231 231 231 246 246 246
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 206 206 206 2 2 6
- 22 22 22 34 34 34 18 14 6 22 22 22
- 26 26 26 18 18 18 6 6 6 2 2 6
- 2 2 6 82 82 82 54 54 54 18 18 18
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 6 6 6 26 26 26
- 62 62 62 106 106 106 74 54 14 185 133 11
-210 162 10 121 92 8 6 6 6 62 62 62
-238 238 238 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 231 231 231 246 246 246
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 158 158 158 18 18 18
- 14 14 14 2 2 6 2 2 6 2 2 6
- 6 6 6 18 18 18 66 66 66 38 38 38
- 6 6 6 94 94 94 50 50 50 18 18 18
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 6 6 6
- 10 10 10 10 10 10 18 18 18 38 38 38
- 78 78 78 142 134 106 216 158 10 242 186 14
-246 190 14 246 190 14 156 118 10 10 10 10
- 90 90 90 238 238 238 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 231 231 231 250 250 250
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 246 230 190
-238 204 91 238 204 91 181 142 44 37 26 9
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 38 38 38 46 46 46
- 26 26 26 106 106 106 54 54 54 18 18 18
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 6 6 6 14 14 14 22 22 22
- 30 30 30 38 38 38 50 50 50 70 70 70
-106 106 106 190 142 34 226 170 11 242 186 14
-246 190 14 246 190 14 246 190 14 154 114 10
- 6 6 6 74 74 74 226 226 226 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 231 231 231 250 250 250
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 228 184 62
-241 196 14 241 208 19 232 195 16 38 30 10
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 6 6 6 30 30 30 26 26 26
-203 166 17 154 142 90 66 66 66 26 26 26
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 6 6 6 18 18 18 38 38 38 58 58 58
- 78 78 78 86 86 86 101 101 101 123 123 123
-175 146 61 210 150 10 234 174 13 246 186 14
-246 190 14 246 190 14 246 190 14 238 190 10
-102 78 10 2 2 6 46 46 46 198 198 198
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 234 234 234 242 242 242
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 224 178 62
-242 186 14 241 196 14 210 166 10 22 18 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 6 6 6 121 92 8
-238 202 15 232 195 16 82 82 82 34 34 34
- 10 10 10 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 14 14 14 38 38 38 70 70 70 154 122 46
-190 142 34 200 144 11 197 138 11 197 138 11
-213 154 11 226 170 11 242 186 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-225 175 15 46 32 6 2 2 6 22 22 22
-158 158 158 250 250 250 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 250 250 250 242 242 242 224 178 62
-239 182 13 236 186 11 213 154 11 46 32 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 61 42 6 225 175 15
-238 190 10 236 186 11 112 100 78 42 42 42
- 14 14 14 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 6 6 6
- 22 22 22 54 54 54 154 122 46 213 154 11
-226 170 11 230 174 11 226 170 11 226 170 11
-236 178 12 242 186 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-241 196 14 184 144 12 10 10 10 2 2 6
- 6 6 6 116 116 116 242 242 242 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 231 231 231 198 198 198 214 170 54
-236 178 12 236 178 12 210 150 10 137 92 6
- 18 14 6 2 2 6 2 2 6 2 2 6
- 6 6 6 70 47 6 200 144 11 236 178 12
-239 182 13 239 182 13 124 112 88 58 58 58
- 22 22 22 6 6 6 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 30 30 30 70 70 70 180 133 36 226 170 11
-239 182 13 242 186 14 242 186 14 246 186 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 232 195 16 98 70 6 2 2 6
- 2 2 6 2 2 6 66 66 66 221 221 221
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 206 206 206 198 198 198 214 166 58
-230 174 11 230 174 11 216 158 10 192 133 9
-163 110 8 116 81 8 102 78 10 116 81 8
-167 114 7 197 138 11 226 170 11 239 182 13
-242 186 14 242 186 14 162 146 94 78 78 78
- 34 34 34 14 14 14 6 6 6 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 6 6 6
- 30 30 30 78 78 78 190 142 34 226 170 11
-239 182 13 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 241 196 14 203 166 17 22 18 6
- 2 2 6 2 2 6 2 2 6 38 38 38
-218 218 218 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-250 250 250 206 206 206 198 198 198 202 162 69
-226 170 11 236 178 12 224 166 10 210 150 10
-200 144 11 197 138 11 192 133 9 197 138 11
-210 150 10 226 170 11 242 186 14 246 190 14
-246 190 14 246 186 14 225 175 15 124 112 88
- 62 62 62 30 30 30 14 14 14 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 30 30 30 78 78 78 174 135 50 224 166 10
-239 182 13 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 241 196 14 139 102 15
- 2 2 6 2 2 6 2 2 6 2 2 6
- 78 78 78 250 250 250 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-250 250 250 214 214 214 198 198 198 190 150 46
-219 162 10 236 178 12 234 174 13 224 166 10
-216 158 10 213 154 11 213 154 11 216 158 10
-226 170 11 239 182 13 246 190 14 246 190 14
-246 190 14 246 190 14 242 186 14 206 162 42
-101 101 101 58 58 58 30 30 30 14 14 14
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 30 30 30 74 74 74 174 135 50 216 158 10
-236 178 12 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 241 196 14 226 184 13
- 61 42 6 2 2 6 2 2 6 2 2 6
- 22 22 22 238 238 238 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 226 226 226 187 187 187 180 133 36
-216 158 10 236 178 12 239 182 13 236 178 12
-230 174 11 226 170 11 226 170 11 230 174 11
-236 178 12 242 186 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 186 14 239 182 13
-206 162 42 106 106 106 66 66 66 34 34 34
- 14 14 14 6 6 6 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 6 6 6
- 26 26 26 70 70 70 163 133 67 213 154 11
-236 178 12 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 241 196 14
-190 146 13 18 14 6 2 2 6 2 2 6
- 46 46 46 246 246 246 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 221 221 221 86 86 86 156 107 11
-216 158 10 236 178 12 242 186 14 246 186 14
-242 186 14 239 182 13 239 182 13 242 186 14
-242 186 14 246 186 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-242 186 14 225 175 15 142 122 72 66 66 66
- 30 30 30 10 10 10 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 6 6 6
- 26 26 26 70 70 70 163 133 67 210 150 10
-236 178 12 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-232 195 16 121 92 8 34 34 34 106 106 106
-221 221 221 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-242 242 242 82 82 82 18 14 6 163 110 8
-216 158 10 236 178 12 242 186 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 242 186 14 163 133 67
- 46 46 46 18 18 18 6 6 6 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 10 10 10
- 30 30 30 78 78 78 163 133 67 210 150 10
-236 178 12 246 186 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-241 196 14 215 174 15 190 178 144 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 218 218 218
- 58 58 58 2 2 6 22 18 6 167 114 7
-216 158 10 236 178 12 246 186 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 186 14 242 186 14 190 150 46
- 54 54 54 22 22 22 6 6 6 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 14 14 14
- 38 38 38 86 86 86 180 133 36 213 154 11
-236 178 12 246 186 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 232 195 16 190 146 13 214 214 214
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 250 250 250 170 170 170 26 26 26
- 2 2 6 2 2 6 37 26 9 163 110 8
-219 162 10 239 182 13 246 186 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 186 14 236 178 12 224 166 10 142 122 72
- 46 46 46 18 18 18 6 6 6 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 6 6 6 18 18 18
- 50 50 50 109 106 95 192 133 9 224 166 10
-242 186 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-242 186 14 226 184 13 210 162 10 142 110 46
-226 226 226 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-253 253 253 253 253 253 253 253 253 253 253 253
-198 198 198 66 66 66 2 2 6 2 2 6
- 2 2 6 2 2 6 50 34 6 156 107 11
-219 162 10 239 182 13 246 186 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 242 186 14
-234 174 13 213 154 11 154 122 46 66 66 66
- 30 30 30 10 10 10 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 6 6 6 22 22 22
- 58 58 58 154 121 60 206 145 10 234 174 13
-242 186 14 246 186 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 186 14 236 178 12 210 162 10 163 110 8
- 61 42 6 138 138 138 218 218 218 250 250 250
-253 253 253 253 253 253 253 253 253 250 250 250
-242 242 242 210 210 210 144 144 144 66 66 66
- 6 6 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 61 42 6 163 110 8
-216 158 10 236 178 12 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 239 182 13 230 174 11 216 158 10
-190 142 34 124 112 88 70 70 70 38 38 38
- 18 18 18 6 6 6 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 6 6 6 22 22 22
- 62 62 62 168 124 44 206 145 10 224 166 10
-236 178 12 239 182 13 242 186 14 242 186 14
-246 186 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 236 178 12 216 158 10 175 118 6
- 80 54 7 2 2 6 6 6 6 30 30 30
- 54 54 54 62 62 62 50 50 50 38 38 38
- 14 14 14 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 6 6 6 80 54 7 167 114 7
-213 154 11 236 178 12 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 190 14 242 186 14 239 182 13 239 182 13
-230 174 11 210 150 10 174 135 50 124 112 88
- 82 82 82 54 54 54 34 34 34 18 18 18
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 6 6 6 18 18 18
- 50 50 50 158 118 36 192 133 9 200 144 11
-216 158 10 219 162 10 224 166 10 226 170 11
-230 174 11 236 178 12 239 182 13 239 182 13
-242 186 14 246 186 14 246 190 14 246 190 14
-246 190 14 246 190 14 246 190 14 246 190 14
-246 186 14 230 174 11 210 150 10 163 110 8
-104 69 6 10 10 10 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 6 6 6 91 60 6 167 114 7
-206 145 10 230 174 11 242 186 14 246 190 14
-246 190 14 246 190 14 246 186 14 242 186 14
-239 182 13 230 174 11 224 166 10 213 154 11
-180 133 36 124 112 88 86 86 86 58 58 58
- 38 38 38 22 22 22 10 10 10 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 14 14 14
- 34 34 34 70 70 70 138 110 50 158 118 36
-167 114 7 180 123 7 192 133 9 197 138 11
-200 144 11 206 145 10 213 154 11 219 162 10
-224 166 10 230 174 11 239 182 13 242 186 14
-246 186 14 246 186 14 246 186 14 246 186 14
-239 182 13 216 158 10 185 133 11 152 99 6
-104 69 6 18 14 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 2 2 6 2 2 6 2 2 6
- 2 2 6 6 6 6 80 54 7 152 99 6
-192 133 9 219 162 10 236 178 12 239 182 13
-246 186 14 242 186 14 239 182 13 236 178 12
-224 166 10 206 145 10 192 133 9 154 121 60
- 94 94 94 62 62 62 42 42 42 22 22 22
- 14 14 14 6 6 6 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 6 6 6
- 18 18 18 34 34 34 58 58 58 78 78 78
-101 98 89 124 112 88 142 110 46 156 107 11
-163 110 8 167 114 7 175 118 6 180 123 7
-185 133 11 197 138 11 210 150 10 219 162 10
-226 170 11 236 178 12 236 178 12 234 174 13
-219 162 10 197 138 11 163 110 8 130 83 6
- 91 60 6 10 10 10 2 2 6 2 2 6
- 18 18 18 38 38 38 38 38 38 38 38 38
- 38 38 38 38 38 38 38 38 38 38 38 38
- 38 38 38 38 38 38 26 26 26 2 2 6
- 2 2 6 6 6 6 70 47 6 137 92 6
-175 118 6 200 144 11 219 162 10 230 174 11
-234 174 13 230 174 11 219 162 10 210 150 10
-192 133 9 163 110 8 124 112 88 82 82 82
- 50 50 50 30 30 30 14 14 14 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 6 6 6 14 14 14 22 22 22 34 34 34
- 42 42 42 58 58 58 74 74 74 86 86 86
-101 98 89 122 102 70 130 98 46 121 87 25
-137 92 6 152 99 6 163 110 8 180 123 7
-185 133 11 197 138 11 206 145 10 200 144 11
-180 123 7 156 107 11 130 83 6 104 69 6
- 50 34 6 54 54 54 110 110 110 101 98 89
- 86 86 86 82 82 82 78 78 78 78 78 78
- 78 78 78 78 78 78 78 78 78 78 78 78
- 78 78 78 82 82 82 86 86 86 94 94 94
-106 106 106 101 101 101 86 66 34 124 80 6
-156 107 11 180 123 7 192 133 9 200 144 11
-206 145 10 200 144 11 192 133 9 175 118 6
-139 102 15 109 106 95 70 70 70 42 42 42
- 22 22 22 10 10 10 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 6 6 6 10 10 10
- 14 14 14 22 22 22 30 30 30 38 38 38
- 50 50 50 62 62 62 74 74 74 90 90 90
-101 98 89 112 100 78 121 87 25 124 80 6
-137 92 6 152 99 6 152 99 6 152 99 6
-138 86 6 124 80 6 98 70 6 86 66 30
-101 98 89 82 82 82 58 58 58 46 46 46
- 38 38 38 34 34 34 34 34 34 34 34 34
- 34 34 34 34 34 34 34 34 34 34 34 34
- 34 34 34 34 34 34 38 38 38 42 42 42
- 54 54 54 82 82 82 94 86 76 91 60 6
-134 86 6 156 107 11 167 114 7 175 118 6
-175 118 6 167 114 7 152 99 6 121 87 25
-101 98 89 62 62 62 34 34 34 18 18 18
- 6 6 6 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 6 6 6 6 6 6 10 10 10
- 18 18 18 22 22 22 30 30 30 42 42 42
- 50 50 50 66 66 66 86 86 86 101 98 89
-106 86 58 98 70 6 104 69 6 104 69 6
-104 69 6 91 60 6 82 62 34 90 90 90
- 62 62 62 38 38 38 22 22 22 14 14 14
- 10 10 10 10 10 10 10 10 10 10 10 10
- 10 10 10 10 10 10 6 6 6 10 10 10
- 10 10 10 10 10 10 10 10 10 14 14 14
- 22 22 22 42 42 42 70 70 70 89 81 66
- 80 54 7 104 69 6 124 80 6 137 92 6
-134 86 6 116 81 8 100 82 52 86 86 86
- 58 58 58 30 30 30 14 14 14 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 6 6 6 10 10 10 14 14 14
- 18 18 18 26 26 26 38 38 38 54 54 54
- 70 70 70 86 86 86 94 86 76 89 81 66
- 89 81 66 86 86 86 74 74 74 50 50 50
- 30 30 30 14 14 14 6 6 6 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 6 6 6 18 18 18 34 34 34 58 58 58
- 82 82 82 89 81 66 89 81 66 89 81 66
- 94 86 66 94 86 76 74 74 74 50 50 50
- 26 26 26 14 14 14 6 6 6 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 6 6 6 6 6 6 14 14 14 18 18 18
- 30 30 30 38 38 38 46 46 46 54 54 54
- 50 50 50 42 42 42 30 30 30 18 18 18
- 10 10 10 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 6 6 6 14 14 14 26 26 26
- 38 38 38 50 50 50 58 58 58 58 58 58
- 54 54 54 42 42 42 30 30 30 18 18 18
- 10 10 10 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 6 6 6
- 6 6 6 10 10 10 14 14 14 18 18 18
- 18 18 18 14 14 14 10 10 10 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 6 6 6
- 14 14 14 18 18 18 22 22 22 22 22 22
- 18 18 18 14 14 14 10 10 10 6 6 6
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 3 4 4 6 7 7
+8 10 10 8 10 10 6 8 8 6 7 7 3 4 4 2 2 2
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 4 5 5 17 18 17
+27 29 28 35 37 36 40 43 41 43 45 43 40 43 41 37 39 37
+32 34 33 27 30 29 23 25 24 17 21 21 15 18 18 12 15 15
+11 13 13 8 10 10 6 7 7 3 4 4 1 1 1 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 13 13 13 32 34 33 49 51 48 60 60 56 58 59 55
+55 57 54 55 56 53 49 51 48 43 45 43 39 40 39 33 37 35
+28 31 30 23 27 26 20 23 23 17 20 20 14 17 17 13 16 16
+11 14 14 10 13 13 10 12 12 9 11 11 8 10 10 6 7 7
+2 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 6 7 7 12 15 15
+12 15 15 8 9 9 2 3 3 0 0 0 1 1 1 25 27 26
+55 56 53 68 70 65 65 66 61 65 66 61 63 64 60 63 64 60
+58 59 55 51 52 50 47 48 46 41 42 42 35 37 36 30 32 31
+26 28 27 20 24 24 18 22 22 16 19 19 14 17 17 13 16 16
+12 15 15 11 14 14 10 13 13 10 12 12 9 11 11 8 10 10
+8 9 9 6 8 8 3 3 3 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 6 7 7 20 24 24 23 27 26
+23 27 26 18 22 22 11 13 13 23 24 24 61 63 57 72 73 67
+72 73 67 68 70 65 68 70 65 68 70 65 63 64 60 58 59 55
+55 56 53 47 48 46 41 42 42 35 37 36 30 32 31 26 28 27
+20 24 24 18 22 22 16 20 20 15 19 19 14 17 17 13 16 16
+12 15 15 12 15 15 11 14 14 10 13 13 10 12 12 9 11 11
+8 10 10 8 9 9 7 9 9 6 7 7 1 2 2 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 1 1 1 4 5 5 5 6 5 4 5 5
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 15 19 19 40 41 39 53 55 47
+33 36 34 27 30 29 51 52 50 72 73 67 72 73 67 72 73 67
+72 73 67 68 70 65 68 70 65 63 64 60 58 59 55 51 52 50
+47 48 46 40 43 41 33 37 35 30 32 31 26 28 27 20 24 24
+18 22 22 17 21 21 16 19 19 14 18 18 14 17 17 13 17 17
+13 16 16 12 15 15 12 15 15 11 14 14 10 13 13 10 12 12
+9 11 11 8 10 10 8 9 9 7 9 9 6 8 8 3 4 4
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+2 2 2 6 8 8 10 12 12 10 12 12 10 12 12 10 12 12
+6 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 20 23 23 71 71 57 131 127 93
+115 113 82 63 64 60 72 73 67 72 73 67 72 73 67 72 73 67
+68 70 65 65 66 61 61 63 57 55 57 54 49 51 48 43 45 43
+39 40 39 33 36 34 28 31 30 23 27 26 20 24 24 20 23 23
+17 21 21 16 20 20 15 19 19 15 18 18 14 18 18 14 17 17
+13 17 17 13 16 16 12 15 15 12 15 15 11 14 14 10 13 13
+10 12 12 9 11 11 8 10 10 7 9 9 7 9 9 6 8 8
+4 5 5 0 0 0 0 0 0 0 0 0 1 1 1 6 7 7
+10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12
+10 12 12 3 4 4 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 18 22 22 71 71 57 144 139 99
+84 83 72 68 70 65 72 73 67 72 73 67 68 70 65 65 66 61
+63 64 60 55 57 54 51 52 50 47 48 46 40 43 41 35 37 36
+30 32 31 27 29 28 23 27 26 20 24 24 18 22 22 17 21 21
+16 20 20 15 19 19 15 19 19 15 19 19 15 18 18 14 18 18
+14 17 17 13 17 17 13 16 16 12 15 15 12 15 15 11 14 14
+10 13 13 9 12 12 9 11 11 8 10 10 7 9 9 6 8 8
+6 8 8 3 4 4 0 0 0 2 2 2 8 10 10 10 12 12
+10 12 12 10 12 12 11 13 13 36 38 35 61 61 53 48 49 45
+10 12 12 7 9 9 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 15 19 19 61 61 53 84 83 72
+68 70 65 72 73 67 68 70 65 68 70 65 63 64 60 58 59 55
+51 52 50 47 48 46 41 42 42 37 39 37 32 35 33 28 31 30
+23 27 26 20 24 24 20 23 23 18 22 22 17 21 21 17 21 21
+17 21 21 17 21 21 17 20 20 16 20 20 16 20 20 16 19 19
+15 18 18 14 18 18 13 17 17 13 16 16 12 15 15 12 15 15
+11 14 14 10 13 13 9 12 12 9 11 11 8 10 10 7 9 9
+6 8 8 6 8 8 5 6 5 9 11 11 10 12 12 10 12 12
+19 20 18 82 81 62 149 145 103 160 154 106 142 137 94 96 95 69
+10 12 12 10 12 12 1 1 1 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 10 12 12 44 46 43 68 70 65
+72 73 67 68 70 65 68 70 65 63 64 60 55 57 54 49 51 48
+43 45 43 39 40 39 33 37 35 30 32 31 26 28 27 23 27 26
+20 24 24 18 22 22 18 22 22 18 22 22 18 22 22 20 23 23
+20 24 24 23 25 24 23 25 24 22 24 23 20 23 23 18 22 22
+17 20 20 15 19 19 15 18 18 14 17 17 13 16 16 12 15 15
+11 14 14 11 13 13 10 12 12 9 11 11 8 10 10 8 9 9
+7 9 9 7 9 9 10 12 12 10 12 12 10 12 12 71 71 57
+164 159 111 186 182 128 186 182 128 171 165 117 151 147 98 96 95 69
+10 12 12 10 12 12 3 3 3 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 8 10 10 63 64 60 68 70 65
+72 73 67 68 70 65 63 64 60 55 57 54 47 48 46 40 43 41
+33 37 35 30 32 31 27 29 28 23 27 26 20 24 24 20 23 23
+18 22 22 18 22 22 20 23 22 21 25 23 23 27 26 27 29 28
+28 31 30 31 33 31 31 33 31 31 33 31 28 31 30 26 28 27
+23 25 24 20 23 22 16 20 20 15 18 18 14 17 17 13 16 16
+12 15 15 11 14 14 10 13 13 10 12 12 9 11 11 8 10 10
+10 12 12 10 13 13 10 12 12 12 14 14 96 95 69 165 161 109
+186 182 128 192 187 134 192 187 134 176 171 126 160 154 106 103 101 77
+10 12 12 10 12 12 5 6 5 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 35 37 36 68 70 65 72 73 67
+68 70 65 65 66 61 58 59 55 49 51 48 40 43 41 33 37 35
+28 31 30 23 27 26 20 24 24 20 23 23 18 22 22 18 22 22
+18 22 22 20 23 23 23 27 26 27 30 29 32 35 33 37 39 37
+40 43 41 44 46 43 46 47 43 44 46 43 40 43 41 36 38 35
+31 33 31 27 29 28 22 24 23 17 21 21 15 18 18 14 17 17
+13 16 16 12 15 15 11 14 14 11 14 14 11 13 13 13 16 16
+13 16 16 11 14 14 10 12 12 79 78 62 142 137 94 164 159 111
+178 174 128 192 187 134 192 187 134 176 171 126 160 154 106 96 95 69
+10 12 12 10 12 12 6 7 7 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 55 57 54 68 70 65 72 73 67
+68 70 65 63 64 60 55 56 53 43 45 43 35 37 36 28 31 30
+23 27 26 20 24 24 18 22 22 17 21 21 17 21 21 17 21 21
+20 24 24 25 27 26 31 33 31 38 39 37 46 47 43 53 55 47
+61 61 53 66 65 55 66 65 55 66 65 55 61 61 53 53 55 47
+46 47 43 37 39 37 30 33 30 24 26 24 17 21 21 15 18 18
+13 17 17 12 15 15 12 15 15 13 16 16 14 18 18 14 18 18
+14 17 17 12 15 15 30 31 28 118 116 76 134 131 96 160 154 106
+174 170 121 178 174 128 178 174 128 171 165 117 151 147 98 96 95 69
+10 12 12 10 12 12 6 8 8 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 63 64 60 68 70 65 68 70 65
+65 66 61 58 59 55 49 51 48 39 40 39 30 32 31 23 27 26
+20 24 24 18 22 22 17 21 21 16 20 20 17 21 21 20 23 23
+25 27 26 32 35 33 43 44 41 53 55 47 66 65 55 75 75 61
+82 81 62 84 83 72 87 86 72 87 86 72 82 81 62 75 75 61
+66 65 55 53 55 47 40 41 39 31 33 31 23 25 24 17 20 20
+14 18 18 13 16 16 12 15 15 12 15 15 13 17 17 14 18 18
+14 18 18 13 16 16 46 47 43 96 95 69 125 122 87 142 137 94
+160 154 106 165 161 109 164 159 111 155 149 109 142 137 94 75 75 61
+10 12 12 10 12 12 6 8 8 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 60 60 56 68 70 65 68 70 65
+63 64 60 55 57 54 46 47 45 35 37 36 27 30 29 23 25 24
+18 22 22 17 21 21 16 20 20 17 21 21 18 22 22 23 27 26
+31 33 31 43 44 41 55 56 53 71 71 57 84 83 72 92 91 72
+103 101 77 92 91 72 82 81 62 82 81 62 87 86 72 92 91 72
+84 83 72 71 71 57 55 56 53 43 44 41 30 33 30 22 24 23
+16 19 19 14 17 17 12 15 15 12 15 15 13 16 16 14 18 18
+14 18 18 14 17 17 43 44 41 82 81 62 118 116 76 125 122 87
+142 137 94 144 139 99 144 139 99 134 131 96 118 116 76 53 55 47
+10 12 12 10 12 12 6 8 8 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 47 48 46 63 64 60 63 64 60
+55 57 54 49 51 48 40 43 41 32 34 33 26 28 27 20 24 24
+18 22 22 16 20 20 16 20 20 17 21 21 20 24 24 28 31 30
+40 41 39 53 55 47 75 75 61 90 89 73 87 86 72 48 49 45
+14 14 13 2 2 2 1 2 2 1 1 1 1 1 1 2 2 2
+19 20 18 43 44 41 66 65 55 53 55 47 38 39 37 26 28 27
+18 22 22 14 18 18 13 16 16 12 15 15 12 15 15 13 17 17
+14 18 18 14 18 18 30 31 28 66 65 55 96 95 69 103 101 77
+118 116 76 118 116 76 118 116 76 118 116 76 103 101 77 36 38 35
+10 12 12 10 12 12 6 7 7 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 28 31 30 55 57 54 51 52 50
+49 51 48 41 42 42 35 37 36 28 31 30 23 27 26 20 23 23
+17 21 21 16 20 20 16 20 20 18 22 22 23 27 26 33 36 34
+48 49 45 71 71 57 82 81 62 43 44 41 8 9 9 6 7 7
+6 7 7 6 7 7 6 7 7 5 6 5 4 5 5 3 4 4
+2 3 3 1 2 2 4 5 4 36 38 35 48 49 45 32 35 33
+21 25 23 16 19 19 13 17 17 12 15 15 12 15 15 13 16 16
+14 18 18 14 18 18 16 18 16 36 38 35 61 61 53 82 81 62
+96 95 69 96 95 69 96 95 69 96 95 69 79 78 62 19 20 18
+10 12 12 10 12 12 4 5 5 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 13 13 13 46 47 45 43 45 43
+40 43 41 35 37 36 30 32 31 23 27 26 20 24 24 18 22 22
+17 21 21 16 20 20 17 21 21 20 23 23 27 30 29 40 41 39
+61 61 53 53 55 47 16 17 16 9 11 11 10 12 12 10 12 12
+10 12 12 10 12 12 10 12 12 9 11 11 8 10 10 8 9 9
+6 8 8 5 6 5 4 5 5 2 3 3 19 20 18 38 39 37
+26 28 27 17 21 21 14 17 17 13 16 16 12 15 15 12 15 15
+13 17 17 14 18 18 12 15 15 13 12 7 30 31 28 46 47 43
+53 55 47 66 65 55 66 65 55 53 55 47 36 38 35 10 12 12
+10 12 12 10 12 12 2 3 3 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 1 1 1 33 37 35 35 37 36
+32 35 33 28 31 30 23 27 26 20 24 24 18 22 22 17 21 21
+16 20 20 16 20 20 17 21 21 21 25 23 31 33 31 44 46 43
+31 33 31 11 13 13 12 14 14 12 15 15 13 16 16 14 17 17
+14 17 17 14 17 17 14 17 17 13 16 16 12 15 15 12 14 14
+11 13 13 9 11 11 8 10 10 6 8 8 4 5 5 17 18 17
+30 33 30 20 23 22 15 18 18 13 16 16 12 15 15 12 14 14
+13 16 16 14 17 17 14 18 18 11 12 11 7 7 5 16 17 12
+21 22 20 30 31 28 25 27 25 21 22 20 14 14 13 10 12 12
+10 12 12 9 11 11 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 18 22 22 27 30 29
+27 29 28 40 41 39 53 55 47 53 55 47 53 55 47 46 47 43
+25 27 25 16 20 20 17 21 21 23 25 24 31 33 31 20 20 20
+12 15 15 14 17 17 15 19 19 16 20 20 17 21 21 18 22 22
+18 22 22 18 22 22 18 22 22 17 21 21 17 21 21 16 19 19
+15 18 18 13 16 16 12 15 15 10 12 12 8 10 10 6 8 8
+21 22 21 22 24 23 15 19 19 13 17 17 13 16 16 12 15 15
+12 15 15 13 17 17 14 18 18 14 18 18 13 15 14 10 9 6
+7 7 5 7 7 5 7 7 5 9 11 11 10 12 12 10 12 12
+10 12 12 6 7 7 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 16 17 12 82 81 62
+118 116 76 118 116 76 161 156 96 161 156 96 161 156 96 118 116 76
+118 116 76 96 95 69 53 55 47 22 24 23 14 17 17 13 16 16
+15 19 19 17 21 21 18 22 22 20 24 24 20 24 24 23 27 26
+23 27 26 23 27 26 23 27 26 23 27 26 23 27 26 20 24 24
+20 23 23 17 21 21 16 19 19 14 17 17 12 15 15 10 12 12
+9 11 11 20 23 22 16 19 19 14 17 17 13 16 16 12 15 15
+11 14 14 13 16 16 14 17 17 14 18 18 14 17 17 12 15 15
+10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12
+9 11 11 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 53 55 47 161 156 96
+161 156 96 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 161 156 96 118 116 76 96 95 69 21 22 20 16 19 19
+18 22 22 20 24 24 23 27 26 23 27 26 26 28 27 27 30 29
+27 30 29 18 22 22 12 14 14 8 10 10 9 11 11 17 21 21
+23 27 26 23 27 26 20 24 24 18 22 22 16 20 20 14 17 17
+12 14 14 14 17 17 16 20 20 14 17 17 13 17 17 13 16 16
+12 15 15 12 15 15 13 17 17 14 18 18 14 17 17 13 16 16
+11 13 13 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12
+4 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 13 12 7 118 116 76 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 161 156 96 118 116 76 30 31 28
+20 24 24 23 27 26 27 30 29 28 31 30 30 32 31 23 27 26
+16 19 19 17 21 21 12 15 15 9 11 11 10 12 12 9 11 11
+20 24 24 28 31 30 26 28 27 23 27 26 20 24 24 17 21 21
+15 19 19 13 16 16 16 19 19 14 18 18 14 17 17 13 16 16
+12 15 15 11 14 14 13 16 16 14 17 17 14 18 18 14 17 17
+12 15 15 10 12 12 10 12 12 10 12 12 10 12 12 8 9 9
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 82 81 62 161 156 96 230 229 82
+230 229 82 233 233 100 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 118 116 76
+27 29 28 27 30 29 30 32 31 30 32 31 23 27 26 20 24 24
+26 28 27 17 21 21 6 7 7 72 73 67 145 141 105 15 15 15
+14 17 17 33 37 35 30 32 31 28 31 30 26 28 27 23 27 26
+20 23 23 16 20 20 15 19 19 14 18 18 14 17 17 13 16 16
+12 15 15 11 14 14 12 15 15 13 17 17 14 18 18 14 17 17
+13 16 16 11 13 13 10 12 12 10 12 12 9 11 11 1 1 1
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 16 17 12 161 156 96 230 229 82 230 229 82
+243 242 120 235 234 117 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96
+82 81 62 28 31 30 28 31 30 27 30 29 28 31 30 30 32 31
+33 37 35 13 16 16 3 3 3 105 104 92 210 208 158 12 14 14
+17 21 21 33 37 35 33 37 35 32 35 33 30 32 31 27 30 29
+23 27 26 20 23 23 17 20 20 15 18 18 14 18 18 13 17 17
+13 16 16 12 15 15 11 14 14 13 16 16 14 17 17 14 18 18
+13 17 17 12 15 15 10 12 12 10 12 12 3 4 4 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 96 95 69 230 229 82 230 229 82 244 244 132
+241 241 143 243 242 120 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+161 156 96 46 47 43 32 35 33 33 37 35 33 37 35 33 37 35
+40 43 41 23 27 26 1 1 1 2 2 2 24 26 24 14 17 17
+23 27 26 33 37 35 33 37 35 33 37 35 33 37 35 30 32 31
+27 30 29 23 27 26 20 23 23 15 18 18 14 18 18 14 17 17
+13 16 16 12 15 15 11 14 14 12 15 15 13 17 17 14 17 17
+14 17 17 13 16 16 11 13 13 6 8 8 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 16 17 12 161 156 96 230 229 82 235 234 117 239 239 170
+239 239 170 236 236 101 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 118 116 76 33 37 35 33 37 35 37 39 37 37 39 37
+43 45 43 49 51 48 20 24 24 8 10 10 17 20 20 35 37 36
+33 37 35 40 43 41 37 39 37 35 37 36 33 37 35 33 37 35
+30 32 31 27 30 29 23 27 26 15 19 19 14 18 18 14 17 17
+13 17 17 13 16 16 12 15 15 11 14 14 13 16 16 14 17 17
+14 17 17 13 17 17 11 14 14 4 5 5 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 96 95 69 230 229 82 230 229 82 239 239 170 251 251 187
+241 241 143 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 161 156 96 36 38 35 33 37 35 33 37 35 33 37 35
+37 39 37 47 48 46 55 57 54 55 57 54 49 51 48 43 45 43
+43 45 43 43 45 43 40 43 41 40 43 41 37 39 37 33 37 35
+33 37 35 28 31 30 26 28 27 16 20 20 15 18 18 14 18 18
+14 17 17 13 16 16 12 15 15 11 14 14 12 15 15 13 17 17
+14 17 17 14 17 17 8 10 10 5 7 7 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+16 17 12 230 229 82 230 229 82 243 242 120 251 251 187 251 251 187
+246 246 123 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 66 65 55 30 32 31 32 35 33 33 37 35
+33 37 35 37 39 37 40 43 41 47 48 46 49 51 48 51 52 50
+55 57 54 55 57 54 51 52 50 47 48 46 43 45 43 39 40 39
+33 37 35 30 32 31 26 28 27 17 21 21 15 19 19 14 18 18
+14 17 17 13 16 16 12 15 15 12 14 14 11 14 14 13 16 16
+14 17 17 12 15 15 7 9 9 6 8 8 1 1 1 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+96 95 69 230 229 82 230 229 82 239 239 170 251 251 187 239 239 170
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 96 95 69 27 30 29 28 31 30 30 32 31
+33 37 35 40 43 41 46 47 45 55 57 54 63 64 60 72 73 67
+72 73 67 72 73 67 72 73 67 65 66 61 55 57 54 47 48 46
+39 40 39 32 35 33 27 30 29 17 21 21 15 19 19 15 18 18
+14 18 18 13 17 17 13 16 16 12 15 15 11 14 14 12 14 14
+13 16 16 9 11 11 7 9 9 9 11 11 66 65 55 115 113 82
+21 22 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 7
+230 229 82 230 229 82 236 236 101 251 251 187 251 251 187 246 246 123
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 118 116 76 23 27 26 26 28 27 32 35 33
+51 52 50 90 89 73 110 109 94 145 141 105 168 163 120 177 172 135
+177 172 135 188 184 146 188 184 146 181 176 137 194 191 148 188 184 146
+184 179 149 188 184 146 188 184 146 156 151 111 177 172 135 181 176 137
+177 172 135 168 163 120 168 163 120 158 153 112 156 151 111 158 153 112
+156 151 111 158 153 112 177 172 135 188 184 146 188 184 146 194 189 146
+36 38 35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 81 62
+230 229 82 230 229 82 244 244 132 251 251 187 244 244 132 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 82 81 62
+96 95 69 230 229 82 181 178 103 110 109 94 156 151 111 188 184 146
+188 184 146 197 193 154 188 184 146 184 181 136 188 184 146 168 163 120
+168 163 120 178 174 128 156 151 111 158 153 112 174 170 121 156 151 111
+156 151 111 158 153 112 156 151 111 168 163 120 178 174 128 181 176 137
+176 171 126 178 174 128 184 181 136 176 171 126 178 174 128 184 181 136
+176 171 126 178 174 128 184 181 136 164 159 111 155 149 109 96 95 69
+1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 161 156 96
+230 229 82 230 229 82 244 244 132 244 244 132 236 236 101 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 46 47 43 82 81 62
+158 153 112 197 193 154 194 189 146 184 181 136 188 184 146 168 163 120
+156 151 111 137 133 100 131 127 93 137 133 100 137 133 100 158 153 112
+121 119 87 137 133 100 156 151 111 145 141 105 99 98 80 84 83 72
+63 64 60 52 53 49 40 43 41 33 36 34 36 38 35 36 38 35
+38 39 37 43 44 41 43 44 41 46 47 43 48 49 45 48 49 45
+46 47 43 36 38 35 30 31 28 19 20 18 6 7 7 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 36 38 35 230 229 82
+230 229 82 230 229 82 246 246 123 236 236 101 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 53 55 47 121 119 87
+176 171 126 171 165 117 161 156 96 82 81 62 53 55 47 33 37 35
+39 40 39 63 64 60 99 98 80 121 119 87 137 133 100 177 172 135
+176 171 126 184 181 136 131 127 93 131 127 93 110 109 94 84 83 72
+51 52 50 39 40 39 27 29 28 18 22 22 16 19 19 15 19 19
+15 19 19 14 18 18 14 17 17 13 16 16 12 15 15 11 14 14
+10 13 13 9 12 12 9 11 11 8 9 9 7 9 9 1 1 1
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 118 116 76 230 229 82
+230 229 82 230 229 82 236 236 101 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 96 95 69 71 71 57
+36 38 35 118 116 76 118 116 76 12 15 15 15 18 18 20 24 24
+33 37 35 55 56 53 84 83 72 110 109 94 145 141 105 110 109 94
+168 163 120 121 119 87 156 151 111 131 127 93 87 86 72 61 63 57
+47 48 46 28 31 30 18 22 22 15 19 19 15 18 18 15 19 19
+15 19 19 14 18 18 14 17 17 13 17 17 13 16 16 12 15 15
+11 13 13 10 12 12 9 11 11 8 10 10 7 9 9 3 3 3
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 1 1 0 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96
+161 156 96 230 229 82 118 116 76 11 14 14 14 17 17 18 22 22
+27 30 29 40 43 41 60 60 56 84 83 72 105 104 92 110 109 94
+110 109 94 110 109 94 99 98 80 90 89 73 68 70 65 47 48 46
+32 34 33 23 25 24 20 23 23 17 21 21 15 19 19 14 17 17
+15 19 19 15 18 18 14 18 18 13 17 17 13 16 16 12 15 15
+11 14 14 10 12 12 9 11 11 8 10 10 7 9 9 4 5 5
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 16 17 12 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 161 156 96 118 116 76 11 13 13 13 16 16 15 19 19
+20 24 24 30 32 31 40 43 41 51 52 50 63 64 60 72 73 67
+65 66 61 65 66 61 65 66 61 55 57 54 46 47 45 33 37 35
+27 29 28 20 24 24 17 21 21 16 20 20 16 20 20 15 19 19
+15 19 19 15 19 19 14 18 18 14 17 17 13 16 16 12 15 15
+11 14 14 10 13 13 9 12 12 8 10 10 7 9 9 6 7 7
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 53 55 47 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+161 156 96 118 116 76 53 55 47 10 13 13 12 15 15 14 17 17
+17 20 20 20 24 24 27 29 28 32 34 33 37 39 37 40 43 41
+43 45 43 41 42 42 35 37 36 30 32 31 28 31 30 23 27 26
+20 23 23 17 21 21 16 20 20 16 20 20 16 20 20 16 19 19
+15 19 19 15 19 19 14 18 18 14 17 17 13 16 16 12 15 15
+11 14 14 10 13 13 9 12 12 9 11 11 8 10 10 10 12 12
+1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 82 81 62 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 161 156 96
+118 116 76 82 81 62 13 14 12 10 13 13 12 15 15 13 17 17
+15 19 19 16 20 20 20 23 23 20 24 24 23 27 26 26 28 27
+26 28 27 26 28 27 23 27 26 18 22 22 20 23 23 17 21 21
+17 21 21 16 20 20 16 20 20 16 20 20 16 20 20 16 19 19
+15 19 19 15 19 19 15 18 18 14 17 17 13 17 17 13 16 16
+12 15 15 12 14 14 12 14 14 12 14 14 12 14 14 23 24 24
+6 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 118 116 76 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 161 156 96 161 156 96 118 116 76
+71 71 57 13 14 12 9 12 12 10 13 13 12 15 15 13 17 17
+15 18 18 15 19 19 16 20 20 17 21 21 17 21 21 18 22 22
+18 22 22 18 22 22 17 21 21 16 19 19 15 18 18 14 18 18
+16 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+15 19 19 15 19 19 15 18 18 14 18 18 16 20 20 23 25 24
+17 21 21 25 27 26 47 48 46 47 48 46 51 52 50 72 73 67
+33 36 34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 118 116 76 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 161 156 96 118 116 76 118 116 76 46 47 43
+9 11 11 9 11 11 10 12 12 11 13 13 12 15 15 14 17 17
+15 18 18 15 19 19 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+15 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+15 19 19 16 20 20 20 24 24 55 56 53 32 34 33 84 83 72
+90 89 73 110 109 94 110 109 94 105 104 92 110 109 94 110 109 94
+72 73 67 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 96 95 69 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 161 156 96 118 116 76 82 81 62 16 17 12 9 11 11
+9 11 11 9 12 12 10 13 13 12 14 14 13 16 16 14 18 18
+15 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+16 19 19 33 36 34 99 98 80 156 151 111 145 141 105 184 179 149
+168 163 120 184 179 149 177 172 135 156 151 111 145 141 105 110 109 94
+90 89 73 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 71 71 57 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82
+230 229 82 161 156 96 230 229 82 230 229 82 230 229 82 161 156 96
+118 116 76 82 81 62 30 31 28 9 11 11 9 11 11 9 11 11
+10 12 12 10 13 13 11 14 14 13 16 16 14 17 17 15 18 18
+15 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+18 22 22 58 59 55 137 133 100 197 193 154 214 212 158 210 208 158
+197 193 154 184 179 149 184 179 149 137 133 100 110 109 94 99 98 80
+84 83 72 10 10 9 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 16 17 12 230 229 82 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96
+161 156 96 161 156 96 161 156 96 161 156 96 118 116 76 71 71 57
+21 22 20 12 14 14 11 13 13 10 12 12 10 12 12 10 13 13
+11 13 13 12 15 15 13 16 16 14 17 17 14 18 18 15 19 19
+16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 17 21 21
+23 27 26 84 83 72 184 179 149 251 251 187 210 208 158 184 179 149
+184 179 149 156 151 111 110 109 94 84 83 72 63 64 60 51 52 50
+18 22 22 6 8 8 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 118 116 76 230 229 82
+230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 161 156 96
+161 156 96 161 156 96 118 116 76 53 55 47 20 23 22 16 19 19
+13 16 16 12 15 15 12 14 14 11 14 14 11 14 14 11 14 14
+12 15 15 13 16 16 14 17 17 15 19 19 16 20 20 17 21 21
+23 27 26 18 22 22 20 24 24 23 27 26 30 32 31 17 21 21
+16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+23 27 26 33 37 35 137 133 100 156 151 111 158 153 112 105 104 92
+105 104 92 68 70 65 39 40 39 18 22 22 12 14 14 12 15 15
+9 11 11 4 5 5 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 16 17 12 230 229 82
+230 229 82 230 229 82 230 229 82 161 156 96 118 116 76 118 116 76
+118 116 76 66 65 55 43 45 43 32 34 33 25 27 26 20 23 22
+17 20 20 15 18 18 14 17 17 15 18 18 13 16 16 14 17 17
+14 18 18 16 20 20 32 34 33 55 57 54 58 59 55 72 73 67
+105 104 92 55 57 54 65 66 61 63 64 60 40 43 41 33 37 35
+41 42 42 20 24 24 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+17 21 21 26 28 27 30 32 31 35 37 36 68 70 65 39 40 39
+23 27 26 15 18 18 13 16 16 11 14 14 9 12 12 8 10 10
+7 9 9 6 7 7 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 38 35
+230 229 82 230 229 82 230 229 82 96 95 69 30 31 28 49 51 48
+90 89 73 68 70 65 55 57 54 47 48 46 47 48 46 43 45 43
+32 34 33 43 45 43 43 45 43 23 27 26 25 27 26 40 43 41
+40 43 41 90 89 73 110 109 94 145 141 105 156 151 111 156 151 111
+184 179 149 184 179 149 177 172 135 184 179 149 137 133 100 84 83 72
+105 104 92 63 64 60 49 51 48 47 48 46 28 31 30 18 22 22
+16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 15 19 19 15 19 19 15 19 19 18 22 22 15 19 19
+13 16 16 12 15 15 11 14 14 10 13 13 9 12 12 9 11 11
+8 10 10 6 8 8 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+30 31 28 230 229 82 71 71 57 2 2 1 0 0 0 58 59 55
+105 104 92 84 83 72 65 66 61 84 83 72 110 109 94 110 109 94
+145 141 105 105 104 92 110 109 94 110 109 94 84 83 72 110 109 94
+158 153 112 197 193 154 197 193 154 239 239 170 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 251 251 187 210 208 158 197 193 154
+197 193 154 184 179 149 145 141 105 137 133 100 105 104 92 47 48 46
+20 23 23 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 16 19 19 15 19 19 15 19 19 14 18 18 14 17 17
+13 17 17 13 16 16 12 14 14 12 14 14 13 13 13 13 13 13
+13 13 13 12 12 12 10 10 9 6 7 7 2 2 2 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 65 66 61
+105 104 92 84 83 72 84 83 72 110 109 94 184 179 149 210 208 158
+210 208 158 210 208 158 214 212 158 197 193 154 214 212 158 210 208 158
+251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187
+251 251 187 251 251 187 239 239 170 251 251 187 184 179 149 84 83 72
+26 28 27 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 16 20 20 15 19 19 15 19 19 15 18 18 14 18 18
+13 17 17 13 16 16 15 15 15 14 14 13 14 14 13 14 14 13
+13 13 13 13 13 13 12 12 12 12 12 12 12 12 12 3 4 4
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 72 73 67
+105 104 92 99 98 80 84 83 72 99 98 80 177 172 135 197 193 154
+251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 214 212 158 197 193 154 99 98 80
+23 27 26 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 16 20 20 15 19 19 15 19 19 15 18 18 14 18 18
+14 17 17 16 16 16 16 16 16 16 16 16 15 15 15 14 14 13
+14 14 13 13 13 13 13 13 13 12 12 12 12 12 12 12 12 12
+3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 84 83 72
+110 109 94 99 98 80 72 73 67 63 64 60 99 98 80 177 172 135
+184 179 149 210 208 158 251 251 187 251 251 187 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187
+251 251 187 210 208 158 184 179 149 177 172 135 110 109 94 33 37 35
+17 21 21 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+16 20 20 16 20 20 15 19 19 15 19 19 15 19 19 14 18 18
+15 18 18 18 19 18 18 19 18 17 17 17 16 16 16 15 15 15
+14 14 13 13 13 13 13 13 13 12 12 12 12 12 12 12 12 12
+10 10 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 105 104 92
+108 107 93 99 98 80 72 73 67 63 64 60 51 52 50 87 86 72
+105 104 92 110 109 94 108 107 93 156 151 111 184 179 149 184 179 149
+197 193 154 197 193 154 197 193 154 184 179 149 184 179 149 177 172 135
+197 193 154 156 151 111 177 172 135 184 179 149 168 163 120 137 133 100
+145 141 105 110 109 94 99 98 80 47 48 46 55 57 54 15 19 19
+16 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20
+17 20 20 17 21 21 16 20 20 16 19 19 15 19 19 16 19 19
+20 20 20 21 22 21 20 20 20 19 20 19 18 19 18 16 16 16
+15 15 15 14 14 13 13 13 13 13 13 13 12 12 12 12 12 12
+12 12 12 4 5 5 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 58 59 55 110 109 94
+105 104 92 90 89 73 72 73 67 55 57 54 43 45 43 39 40 39
+43 45 43 46 47 45 43 45 43 68 70 65 65 66 61 63 64 60
+108 107 93 72 73 67 105 104 92 90 89 73 72 73 67 40 43 41
+72 73 67 68 70 65 68 70 65 58 59 55 63 64 60 49 51 48
+43 45 43 33 36 34 27 30 29 20 24 24 16 20 20 15 19 19
+15 19 19 15 19 19 15 19 19 16 19 19 16 20 20 16 20 20
+17 21 21 20 24 24 20 23 22 17 21 21 17 20 20 20 20 20
+21 22 21 21 22 21 21 22 21 21 22 21 20 20 20 18 19 18
+16 16 16 15 15 15 13 13 13 13 13 13 12 12 12 12 12 12
+12 12 12 10 10 9 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 21 22 21 110 109 94 110 109 94
+105 104 92 84 83 72 68 70 65 51 52 50 41 42 42 33 37 35
+28 31 30 23 27 26 20 23 23 18 22 22 17 20 20 25 27 26
+26 28 27 27 30 29 25 27 26 20 23 23 23 27 26 30 32 31
+20 24 24 17 21 21 18 22 22 15 19 19 26 28 27 20 23 23
+14 18 18 15 19 19 15 18 18 15 19 19 15 19 19 15 19 19
+15 19 19 15 19 19 15 19 19 15 19 19 15 19 19 16 19 19
+16 20 20 22 24 23 24 26 24 22 24 23 20 23 22 22 24 23
+24 26 24 24 26 24 23 24 24 22 24 23 21 22 21 19 20 19
+17 17 17 15 15 15 14 14 13 13 13 13 12 12 12 12 12 12
+12 12 12 12 12 12 2 2 2 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 2 2 2 99 98 80 110 109 94 108 107 93
+105 104 92 84 83 72 63 64 60 49 51 48 39 40 39 32 34 33
+27 30 29 23 25 24 20 23 23 17 20 20 15 19 19 14 18 18
+14 17 17 13 17 17 13 17 17 13 17 17 13 17 17 13 17 17
+14 17 17 14 17 17 14 17 17 14 17 17 14 17 17 14 17 17
+14 18 18 14 18 18 14 18 18 14 18 18 15 18 18 15 19 19
+15 19 19 15 19 19 15 19 19 15 19 19 15 19 19 15 19 19
+15 19 19 17 21 21 27 29 28 26 28 27 25 27 26 25 27 26
+27 29 28 27 29 28 26 28 27 24 26 24 21 22 21 20 20 20
+18 19 18 16 16 16 14 14 13 13 13 13 12 12 12 12 12 12
+12 12 12 12 12 12 4 5 5 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 51 52 50 110 109 94 110 109 94 105 104 92
+90 89 73 72 73 67 55 57 54 43 45 43 35 37 36 30 32 31
+26 28 27 20 24 24 17 21 21 16 19 19 15 18 18 14 17 17
+13 16 16 13 16 16 13 16 16 13 16 16 13 16 16 13 16 16
+13 16 16 13 16 16 13 16 16 13 17 17 13 17 17 14 17 17
+14 17 17 14 17 17 14 17 17 14 18 18 14 18 18 14 18 18
+15 18 18 15 18 18 15 19 19 15 19 19 15 19 19 15 19 19
+15 19 19 15 19 19 27 29 28 32 34 33 28 31 30 27 29 28
+30 32 31 30 32 31 30 31 28 26 28 27 23 24 24 21 22 21
+19 20 19 16 16 16 14 14 13 13 13 13 12 12 12 12 12 12
+12 12 12 12 12 12 6 7 7 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 3 3 3 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 10 10 9 108 107 93 110 109 94 108 107 93 99 98 80
+84 83 72 63 64 60 49 51 48 40 43 41 33 36 34 27 30 29
+23 27 26 18 22 22 17 20 20 15 18 18 14 17 17 13 16 16
+13 16 16 13 16 16 12 15 15 12 15 15 12 15 15 12 15 15
+13 16 16 13 16 16 13 16 16 13 16 16 13 16 16 13 16 16
+13 17 17 13 17 17 14 17 17 14 17 17 14 17 17 14 18 18
+14 18 18 14 18 18 15 18 18 15 18 18 15 19 19 15 19 19
+15 19 19 15 19 19 17 21 21 33 36 34 32 34 33 31 33 31
+33 36 34 33 36 34 31 33 31 27 29 28 25 27 26 21 22 21
+19 20 19 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12
+12 12 12 12 12 12 8 8 7 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 63 64 60 137 133 100 43 45 43 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 68 70 65 110 109 94 110 109 94 105 104 92 84 83 72
+68 70 65 55 57 54 43 45 43 35 37 36 30 32 31 26 28 27
+20 24 24 17 21 21 16 19 19 14 17 17 13 16 16 12 15 15
+12 15 15 12 15 15 12 15 15 12 15 15 12 15 15 12 15 15
+12 15 15 12 15 15 12 15 15 12 15 15 12 15 15 13 16 16
+13 16 16 13 16 16 13 16 16 13 17 17 13 17 17 14 17 17
+14 17 17 14 17 17 14 18 18 14 18 18 14 18 18 15 18 18
+15 19 19 15 19 19 15 19 19 20 24 24 32 34 33 35 37 36
+37 39 37 35 37 36 33 36 34 30 32 31 26 28 27 22 24 23
+20 20 20 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12
+12 12 12 12 12 12 8 8 7 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+1 1 1 99 98 80 184 179 149 184 179 149 68 70 65 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+15 15 15 110 109 94 110 109 94 108 107 93 99 98 80 72 73 67
+61 63 57 49 51 48 39 40 39 33 36 34 27 30 29 23 25 24
+18 22 22 16 19 19 14 17 17 13 16 16 12 15 15 12 15 15
+11 14 14 11 14 14 11 14 14 11 14 14 11 14 14 11 14 14
+11 14 14 11 14 14 12 14 14 12 15 15 12 15 15 12 15 15
+12 15 15 13 16 16 13 16 16 13 16 16 13 16 16 13 16 16
+13 17 17 14 17 17 14 17 17 14 17 17 14 18 18 14 18 18
+14 18 18 15 18 18 15 19 19 15 19 19 30 32 31 38 39 37
+39 40 39 39 40 39 35 37 36 31 33 31 27 29 28 22 24 23
+20 20 20 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12
+12 12 12 12 12 12 8 8 7 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 3 3
+110 109 94 197 193 154 210 208 158 184 179 149 68 70 65 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+68 70 65 110 109 94 110 109 94 105 104 92 84 83 72 65 66 61
+51 52 50 43 45 43 35 37 36 30 32 31 25 27 26 20 23 23
+17 20 20 15 18 18 13 16 16 12 15 15 12 15 15 11 14 14
+11 14 14 11 14 14 11 13 13 11 13 13 11 13 13 11 13 13
+11 14 14 11 14 14 11 14 14 11 14 14 11 14 14 11 14 14
+12 15 15 12 15 15 12 15 15 12 15 15 13 16 16 13 16 16
+13 16 16 13 16 16 13 17 17 13 17 17 14 17 17 14 17 17
+14 18 18 14 18 18 14 18 18 16 19 19 37 39 37 41 42 42
+41 42 42 41 42 42 38 39 37 32 34 33 27 29 28 23 24 24
+21 22 21 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12
+12 12 12 12 12 12 8 8 7 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 11 11 11 137 133 100
+197 193 154 251 251 187 239 239 170 184 179 149 31 33 31 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 12 12
+110 109 94 110 109 94 105 104 92 90 89 73 72 73 67 58 59 55
+46 47 45 37 39 37 31 33 31 26 28 27 20 24 24 17 21 21
+15 18 18 13 16 16 12 15 15 12 14 14 11 13 13 11 13 13
+10 13 13 10 13 13 10 13 13 10 13 13 10 13 13 10 13 13
+10 13 13 10 13 13 11 13 13 11 13 13 11 14 14 11 14 14
+11 14 14 11 14 14 12 14 14 12 15 15 12 15 15 12 15 15
+13 16 16 13 16 16 13 16 16 13 16 16 13 17 17 13 17 17
+14 17 17 14 17 17 14 18 18 23 27 26 41 42 42 41 42 42
+43 45 43 41 42 42 39 40 39 33 36 34 27 29 28 23 24 24
+21 22 21 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12
+12 12 12 12 12 12 6 7 7 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 27 29 28 168 163 120 210 208 158
+251 251 187 251 251 187 210 208 158 137 133 100 1 1 1 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 60 56
+110 109 94 105 104 92 105 104 92 84 83 72 65 66 61 51 52 50
+40 43 41 33 36 34 27 30 29 23 25 24 18 22 22 16 19 19
+14 17 17 12 15 15 11 14 14 11 14 14 10 13 13 10 13 13
+10 13 13 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12
+10 12 12 10 12 12 10 13 13 10 13 13 10 13 13 11 13 13
+11 13 13 11 14 14 11 14 14 11 14 14 11 14 14 12 15 15
+12 15 15 12 15 15 12 15 15 13 16 16 13 16 16 13 16 16
+13 17 17 13 17 17 14 17 17 32 34 33 43 45 43 43 45 43
+43 45 43 43 45 43 39 40 39 33 36 34 27 29 28 23 24 24
+21 22 21 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12
+12 12 12 12 12 12 6 7 7 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 1 1 1 68 70 65 184 179 149 210 208 158 251 251 187
+251 251 187 214 212 158 184 179 149 37 39 37 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 6 7 7 105 104 92
+105 104 92 105 104 92 99 98 80 72 73 67 58 59 55 46 47 45
+35 37 36 30 32 31 25 27 26 20 23 23 16 19 19 14 17 17
+12 15 15 12 14 14 11 13 13 10 13 13 10 12 12 10 12 12
+10 12 12 10 12 12 9 12 12 9 12 12 9 12 12 9 12 12
+10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 10 13 13
+10 13 13 10 13 13 11 13 13 11 13 13 11 14 14 11 14 14
+11 14 14 12 15 15 12 15 15 12 15 15 12 15 15 13 16 16
+13 16 16 13 16 16 17 20 20 41 42 42 46 47 45 46 47 45
+46 47 45 43 45 43 40 41 39 33 36 34 27 29 28 23 24 24
+20 20 20 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12
+12 12 12 12 12 12 4 5 5 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+15 15 15 110 109 94 197 193 154 214 212 158 251 251 187 251 251 187
+239 239 170 184 179 149 84 83 72 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 47 48 46 105 104 92
+105 104 92 99 98 80 84 83 72 68 70 65 51 52 50 40 43 41
+32 34 33 27 29 28 22 24 23 17 21 21 15 18 18 13 16 16
+12 15 15 11 13 13 10 13 13 10 12 12 9 12 12 9 12 12
+9 12 12 9 12 12 9 11 11 9 11 11 9 11 11 9 11 11
+9 12 12 9 12 12 9 12 12 9 12 12 10 12 12 10 12 12
+10 12 12 10 12 12 10 13 13 10 13 13 10 13 13 11 13 13
+11 14 14 11 14 14 11 14 14 12 14 14 12 15 15 12 15 15
+12 15 15 13 16 16 28 31 30 43 45 43 47 48 46 47 48 46
+47 48 46 43 45 43 40 41 39 33 36 34 27 29 28 22 24 23
+20 20 20 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12
+12 12 12 12 12 12 3 4 4 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 60 60 56
+177 172 135 197 193 154 251 251 187 251 251 187 251 251 187 251 251 187
+184 179 149 110 109 94 3 4 4 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 1 1 1 99 98 80 105 104 92
+99 98 80 87 86 72 84 83 72 63 64 60 46 47 45 35 37 36
+30 32 31 25 27 26 18 22 22 16 19 19 14 17 17 12 15 15
+11 14 14 10 13 13 9 12 12 9 12 12 9 11 11 9 11 11
+9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11
+9 11 11 9 11 11 9 11 11 9 11 11 9 12 12 9 12 12
+9 12 12 10 12 12 10 12 12 10 12 12 10 13 13 10 13 13
+10 13 13 11 13 13 11 14 14 11 14 14 11 14 14 12 15 15
+12 15 15 14 17 17 41 42 42 47 48 46 49 51 48 51 52 50
+47 48 46 43 45 43 40 41 39 33 36 34 27 29 28 22 24 23
+19 20 19 16 16 16 14 14 13 13 13 13 12 12 12 12 12 12
+12 12 12 12 12 12 2 2 2 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 23 24 24 137 133 100 184 179 149
+210 208 158 251 251 187 251 251 187 251 251 187 251 251 187 184 179 149
+110 109 94 13 13 13 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 30 32 31 105 104 92 99 98 80
+84 83 72 84 83 72 72 73 67 55 57 54 41 42 42 32 34 33
+27 29 28 20 24 24 17 20 20 14 17 17 13 16 16 12 14 14
+10 13 13 10 12 12 9 11 11 9 11 11 9 11 11 9 11 11
+9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11
+9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11
+9 11 11 9 12 12 9 12 12 10 12 12 10 12 12 10 12 12
+10 13 13 10 13 13 10 13 13 11 13 13 11 14 14 11 14 14
+11 14 14 27 29 28 55 56 53 72 73 67 51 52 50 51 52 50
+49 51 48 43 45 43 39 40 39 32 34 33 26 28 27 21 22 21
+19 20 19 16 16 16 18 19 17 13 13 13 12 12 12 12 12 12
+12 12 12 12 12 12 1 1 1 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 8 8 7 84 83 72 184 179 149 197 193 154 251 251 187
+251 251 187 251 251 187 251 251 187 251 251 187 184 179 149 145 141 105
+19 20 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 14 14 13 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 72 73 67 105 104 92 84 83 72
+72 73 67 84 83 72 68 70 65 49 51 48 39 40 39 30 32 31
+25 27 26 18 22 22 15 18 18 13 16 16 12 15 15 11 13 13
+10 12 12 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11
+9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11
+9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11
+9 11 11 9 11 11 9 11 11 9 12 12 9 12 12 9 12 12
+10 12 12 10 12 12 10 12 12 10 13 13 10 13 13 11 13 13
+13 16 16 41 42 42 99 98 80 158 153 112 65 66 61 51 52 50
+49 51 48 43 45 43 39 40 39 31 33 31 25 27 26 21 22 21
+21 22 21 68 70 65 55 56 53 13 13 13 12 12 12 12 12 12
+12 12 12 11 11 11 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 3 3
+63 64 60 158 153 112 184 179 149 210 208 158 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 184 179 149 137 133 100 27 29 28
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+21 22 21 110 109 94 5 6 5 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 13 13 13 105 104 92 90 89 73 72 73 67
+68 70 65 84 83 72 63 64 60 46 47 45 35 37 36 27 29 28
+22 24 23 17 20 20 14 17 17 12 15 15 11 14 14 10 12 12
+10 12 12 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11
+9 11 11 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11
+9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11
+9 12 12 9 12 12 10 12 12 10 12 12 10 13 13 10 13 13
+30 32 31 47 48 46 177 172 135 210 208 158 137 133 100 55 56 53
+49 51 48 43 45 43 38 39 37 31 33 31 25 27 26 22 24 23
+110 109 94 184 179 149 63 64 60 13 13 13 12 12 12 12 12 12
+12 12 12 8 9 9 0 0 0 1 1 1 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 21 22 21 105 104 92
+184 179 149 210 208 158 251 251 187 251 251 187 251 251 187 251 251 187
+251 251 187 251 251 187 184 179 149 145 141 105 23 24 24 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+68 70 65 184 179 149 105 104 92 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 51 52 50 99 98 80 84 83 72 63 64 60
+68 70 65 72 73 67 55 57 54 41 42 42 32 34 33 25 27 26
+20 23 23 16 19 19 13 16 16 12 14 14 10 13 13 10 12 12
+9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 9 11 11 9 11 11
+9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11
+9 11 11 9 11 11 9 12 12 9 12 12 10 12 12 17 20 20
+46 47 45 72 73 67 210 208 158 251 251 187 210 208 158 63 64 60
+49 51 48 43 45 43 37 39 37 30 32 31 24 26 24 105 104 92
+210 208 158 197 193 154 47 48 46 13 13 13 12 12 12 12 12 12
+12 12 12 6 7 7 33 36 34 48 49 45 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 8 8 7 23 24 24 55 56 53 110 109 94
+210 208 158 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187
+251 251 187 184 179 149 110 109 94 20 20 20 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+110 109 94 251 251 187 210 208 158 47 48 46 0 0 0 0 0 0
+0 0 0 1 1 1 90 89 73 90 89 73 72 73 67 55 56 53
+72 73 67 68 70 65 51 52 50 37 39 37 28 31 30 23 25 24
+17 21 21 15 18 18 12 15 15 11 14 14 10 13 13 9 12 12
+9 11 11 9 11 11 9 11 11 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11
+9 11 11 9 11 11 9 11 11 9 12 12 13 16 16 41 42 42
+49 51 48 110 109 94 251 251 187 251 251 187 251 251 187 105 104 92
+49 51 48 43 45 43 35 37 36 30 31 28 47 48 46 197 193 154
+251 251 187 197 193 154 31 33 31 12 12 12 12 12 12 12 12 12
+12 12 12 51 52 50 184 179 149 72 73 67 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2
+11 11 11 21 22 21 30 32 31 40 41 39 60 60 56 145 141 105
+251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 214 212 158
+184 179 149 110 109 94 13 13 13 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 4 5 4 61 61 53 48 49 45 3 4 3
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+156 151 111 251 251 187 251 251 187 184 179 149 11 11 11 0 0 0
+0 0 0 26 28 27 99 98 80 84 83 72 60 60 56 43 45 43
+72 73 67 65 66 61 49 51 48 35 37 36 27 29 28 20 24 24
+17 20 20 14 17 17 12 15 15 11 13 13 10 12 12 9 11 11
+9 11 11 9 11 11 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 9 11 11 9 11 11
+9 11 11 9 11 11 9 11 11 11 13 13 37 39 37 47 48 46
+51 52 50 184 179 149 251 251 187 251 251 187 251 251 187 145 141 105
+47 48 46 41 42 42 35 37 36 27 29 28 137 133 100 251 251 187
+251 251 187 197 193 154 19 20 19 12 12 12 12 12 12 12 12 12
+27 29 28 184 179 149 214 212 158 63 64 60 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 1 1 1 6 7 7 16 16 16 24 26 24
+30 32 31 38 39 37 47 48 46 55 57 54 68 70 65 110 109 94
+197 193 154 251 251 187 251 251 187 251 251 187 210 208 158 184 179 149
+105 104 92 8 8 7 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 65 66 61 184 179 149 156 151 111
+30 32 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+168 163 120 251 251 187 251 251 187 251 251 187 110 109 94 0 0 0
+0 0 0 60 60 56 84 83 72 68 70 65 51 52 50 38 39 37
+84 83 72 63 64 60 43 45 43 33 36 34 25 27 26 20 23 22
+15 18 18 13 16 16 12 14 14 10 13 13 9 12 12 9 11 11
+9 11 11 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+9 11 11 9 11 11 10 12 12 33 36 34 46 47 45 51 52 50
+72 73 67 210 208 158 251 251 187 251 251 187 251 251 187 177 172 135
+47 48 46 41 42 42 35 37 36 37 39 37 184 179 149 251 251 187
+251 251 187 197 193 154 13 13 13 12 12 12 12 12 12 12 12 12
+110 109 94 251 251 187 251 251 187 37 39 37 0 0 0 0 0 0
+0 0 0 21 22 20 2 2 1 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+4 5 5 12 12 12 21 22 21 25 27 26 30 32 31 38 39 37
+46 47 45 55 56 53 60 60 56 65 66 61 68 70 65 105 104 92
+110 109 94 197 193 154 210 208 158 197 193 154 184 179 149 84 83 72
+2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 13 13 13 184 179 149 251 251 187
+197 193 154 43 44 41 0 0 0 0 0 0 0 0 0 0 0 0
+145 141 105 251 251 187 251 251 187 251 251 187 214 212 158 43 45 43
+2 2 2 84 83 72 72 73 67 58 59 55 41 42 42 38 39 37
+72 73 67 58 59 55 41 42 42 31 33 31 25 27 26 18 22 22
+14 17 17 12 15 15 12 14 14 10 12 12 9 12 12 9 11 11
+9 11 11 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 9 12 12 31 33 31 43 45 43 49 51 48 55 56 53
+110 109 94 251 251 187 251 251 187 251 251 187 251 251 187 168 163 120
+47 48 46 41 42 42 33 36 34 63 64 60 197 193 154 251 251 187
+251 251 187 184 179 149 13 13 13 12 12 12 12 12 12 16 16 16
+197 193 154 251 251 187 239 239 170 20 20 20 0 0 0 2 2 1
+108 107 93 110 109 94 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 1 1 1 4 5 5 11 11 11 18 19 18
+22 24 23 26 28 27 32 34 33 39 40 39 46 47 45 51 52 50
+55 57 54 60 60 56 63 64 60 63 64 60 63 64 60 58 59 55
+63 64 60 99 98 80 145 141 105 137 133 100 43 45 43 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 3 4 3 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 110 109 94 251 251 187
+251 251 187 184 179 149 25 27 26 0 0 0 0 0 0 0 0 0
+99 98 80 251 251 187 251 251 187 251 251 187 251 251 187 156 151 111
+25 27 26 84 83 72 65 66 61 47 48 46 32 34 33 39 40 39
+72 73 67 55 57 54 40 41 39 30 32 31 23 25 24 18 22 22
+14 17 17 12 15 15 11 13 13 10 12 12 9 11 11 9 11 11
+9 11 11 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+9 11 11 28 31 30 41 42 42 47 48 46 55 56 53 58 59 55
+137 133 100 251 251 187 251 251 187 251 251 187 210 208 158 137 133 100
+47 48 46 40 41 39 32 34 33 75 75 61 184 179 149 239 239 170
+251 251 187 177 172 135 13 13 13 12 12 12 12 12 12 43 44 41
+197 193 154 251 251 187 210 208 158 10 10 9 0 0 0 84 83 72
+251 251 187 84 83 72 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
+6 7 7 11 11 11 17 17 17 20 20 20 23 24 24 27 29 28
+32 34 33 38 39 37 43 45 43 47 48 46 51 52 50 55 56 53
+58 59 55 58 59 55 55 57 54 55 56 53 47 48 46 41 42 42
+35 37 36 31 33 31 47 48 46 14 14 13 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 66 65 55 99 98 80 20 20 20
+0 0 0 0 0 0 0 0 0 0 0 0 43 45 43 214 212 158
+251 251 187 251 251 187 145 141 105 3 3 3 0 0 0 0 0 0
+48 49 45 184 179 149 239 239 170 251 251 187 239 239 170 177 172 135
+84 83 72 72 73 67 55 56 53 39 40 39 26 28 27 39 40 39
+68 70 65 51 52 50 39 40 39 28 31 30 22 24 23 17 20 20
+14 17 17 12 14 14 10 13 13 9 11 11 9 11 11 9 11 11
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+27 29 28 40 41 39 46 47 45 51 52 50 55 57 54 63 64 60
+131 127 93 197 193 154 210 208 158 197 193 154 168 163 120 96 95 69
+47 48 46 40 41 39 32 34 33 71 71 57 145 141 105 184 179 149
+184 179 149 131 127 93 13 13 13 12 12 12 12 12 12 48 49 45
+168 163 120 184 179 149 156 151 111 6 7 7 14 14 13 177 172 135
+239 239 170 40 41 39 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 3 3 3 6 7 7 11 11 11 16 16 16
+18 19 18 21 22 21 23 24 24 27 29 28 32 34 33 37 39 37
+41 42 42 43 45 43 47 48 46 51 52 50 51 52 50 51 52 50
+51 52 50 49 51 48 46 47 45 40 41 39 32 34 33 25 27 26
+20 20 20 14 14 13 2 2 2 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 33 36 34 197 193 154 184 179 149
+41 42 42 0 0 0 0 0 0 0 0 0 3 3 3 184 179 149
+251 251 187 251 251 187 184 179 149 48 49 45 0 0 0 0 0 0
+16 17 12 121 119 87 177 172 135 194 189 146 188 184 146 145 141 105
+82 81 62 63 64 60 46 47 45 31 33 31 21 22 21 35 37 36
+68 70 65 51 52 50 37 39 37 27 30 29 22 24 23 17 20 20
+13 16 16 12 14 14 10 13 13 9 11 11 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 25 27 26
+38 39 37 43 45 43 51 52 50 55 56 53 60 60 56 63 64 60
+92 91 72 158 153 112 176 171 126 171 165 117 149 143 98 82 81 62
+44 46 43 38 39 37 30 32 31 71 71 57 131 127 93 160 154 106
+149 143 98 82 81 62 13 13 13 12 12 12 12 12 12 46 47 43
+121 119 87 134 131 96 96 95 69 7 7 6 38 39 37 131 127 93
+145 141 105 12 13 12 0 0 0 1 1 1 3 3 3 6 7 7
+10 10 9 12 12 12 14 14 13 16 16 16 18 19 18 21 22 21
+22 24 23 26 28 27 30 31 28 33 36 34 37 39 37 40 41 39
+41 42 42 43 45 43 46 47 45 46 47 45 46 47 45 43 45 43
+41 42 42 37 39 37 31 33 31 26 28 27 21 22 21 16 16 16
+6 7 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 177 172 135 251 251 187
+197 193 154 27 29 28 0 0 0 0 0 0 0 0 0 110 109 94
+239 239 170 239 239 170 184 179 149 87 86 72 2 2 1 0 0 0
+1 1 1 82 81 62 142 137 94 165 161 109 165 161 109 131 127 93
+75 75 61 55 56 53 37 39 37 25 27 26 19 20 19 32 34 33
+65 66 61 49 51 48 35 37 36 27 29 28 20 23 23 16 19 19
+13 16 16 13 13 13 10 12 12 9 11 11 8 10 10 8 10 10
+8 9 9 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 22 24 23 35 37 36
+41 42 42 47 48 46 55 56 53 58 59 55 63 64 60 65 66 61
+71 71 57 131 127 93 160 154 106 160 154 106 142 137 94 82 81 62
+46 47 43 40 41 39 33 36 34 66 65 55 125 122 87 149 143 98
+142 137 94 82 81 62 17 17 17 18 19 17 14 14 13 46 47 43
+118 116 76 125 122 87 96 95 69 16 17 12 71 71 57 103 101 77
+82 81 62 11 11 11 11 11 11 13 13 13 14 14 13 14 14 13
+15 15 15 16 16 16 17 17 17 19 20 19 21 22 21 23 24 24
+26 28 27 27 29 28 31 33 31 33 36 34 35 37 36 38 39 37
+39 40 39 39 40 39 38 39 37 37 39 37 35 37 36 31 33 31
+27 29 28 24 26 24 21 22 21 17 17 17 12 12 12 2 2 2
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 68 70 65 251 251 187
+251 251 187 156 151 111 2 2 1 0 0 0 0 0 0 43 44 41
+177 172 135 184 179 149 158 153 112 103 101 77 19 20 18 0 0 0
+0 0 0 46 47 43 131 127 93 160 154 106 160 154 106 131 127 93
+71 71 57 43 45 43 30 32 31 21 22 21 16 16 16 26 28 27
+63 64 60 47 48 46 35 37 36 26 28 27 20 23 23 16 19 19
+13 16 16 13 13 13 10 12 12 9 11 11 8 10 10 8 10 10
+7 9 9 7 9 9 8 9 9 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 20 20 20 33 36 34 40 41 39
+46 47 45 51 52 50 55 57 54 60 60 56 63 64 60 65 66 61
+66 65 55 118 116 76 151 147 98 165 161 109 151 147 98 121 119 87
+96 95 69 96 95 69 96 95 69 103 101 77 142 137 94 151 147 98
+142 137 94 103 101 77 82 81 62 82 81 62 82 81 62 96 95 69
+131 127 93 142 137 94 103 101 77 46 47 43 96 95 69 118 116 76
+71 71 57 14 14 13 14 14 13 15 15 15 15 15 15 16 16 16
+16 16 16 17 17 17 18 19 18 20 20 20 21 22 21 23 24 24
+25 27 26 27 29 28 30 31 28 30 32 31 31 33 31 31 33 31
+31 33 31 31 33 31 30 31 28 27 29 28 25 27 26 22 24 23
+20 20 20 16 16 16 13 13 13 6 7 7 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+58 59 55 68 70 65 8 8 7 0 0 0 10 10 9 210 208 158
+251 251 187 184 179 149 38 39 37 0 0 0 0 0 0 8 8 7
+103 101 77 149 143 98 149 143 98 118 116 76 40 41 39 25 27 25
+53 55 47 82 81 62 144 139 99 165 161 109 165 161 109 142 137 94
+71 71 57 35 37 36 24 26 24 18 19 18 15 15 15 22 24 23
+63 64 60 46 47 45 33 36 34 26 28 27 20 23 22 17 18 17
+12 15 15 11 13 13 10 12 12 9 11 11 8 10 10 8 10 10
+7 9 9 7 9 9 7 9 9 7 9 9 8 9 9 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 16 16 16 30 31 28 35 37 36 41 42 42
+47 48 46 55 56 53 58 59 55 63 64 60 65 66 61 65 66 61
+61 61 53 103 101 77 151 147 98 171 165 117 171 165 117 168 163 120
+158 153 112 158 153 112 155 149 109 151 147 98 151 147 98 160 154 106
+151 147 98 149 143 98 142 137 94 149 143 98 149 143 98 149 143 98
+155 149 109 151 147 98 131 127 93 103 101 77 125 122 87 118 116 76
+71 71 57 16 16 16 16 16 16 16 16 16 17 17 17 17 17 17
+17 17 17 17 17 17 18 19 18 19 20 19 20 20 20 21 22 21
+23 24 24 24 26 24 25 27 26 26 28 27 26 28 27 26 28 27
+25 27 26 24 26 24 22 24 23 21 22 21 19 20 19 16 16 16
+14 14 13 8 8 7 1 1 1 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+20 20 20 184 179 149 168 163 120 21 22 21 0 0 0 105 104 92
+177 172 135 145 141 105 71 71 57 0 0 0 0 0 0 0 0 0
+66 65 55 131 127 93 151 147 98 142 137 94 118 116 76 121 119 87
+145 141 105 158 153 112 176 171 126 178 174 128 176 171 126 149 145 103
+96 95 69 31 33 31 21 22 21 16 16 16 14 14 13 18 19 18
+60 60 56 46 47 45 33 36 34 25 27 26 21 22 21 15 18 18
+12 15 15 11 13 13 9 11 11 8 10 10 8 10 10 8 9 9
+7 9 9 7 9 9 7 9 9 7 9 9 7 9 9 8 9 9
+8 9 9 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 10 12 12 26 28 27 31 33 31 38 39 37 43 45 43
+51 52 50 55 56 53 60 60 56 63 64 60 65 66 61 68 70 65
+63 64 60 96 95 69 158 153 112 178 174 128 188 184 146 194 189 146
+194 189 146 188 184 146 184 181 136 176 171 126 171 165 117 173 167 111
+173 167 111 165 161 109 171 165 117 174 170 121 176 171 126 178 174 128
+178 174 128 174 170 121 160 154 106 149 143 98 149 143 98 125 122 87
+71 71 57 16 16 16 16 16 16 17 17 17 17 17 17 17 17 17
+17 17 17 17 17 17 17 17 17 18 19 18 19 20 19 20 20 20
+21 22 21 21 22 21 21 22 21 22 24 23 21 22 21 21 22 21
+21 22 21 19 20 19 18 19 18 16 16 16 14 14 13 11 11 11
+3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 105 104 92 197 193 154 110 109 94 9 9 8 36 38 35
+121 119 87 131 127 93 96 95 69 18 19 17 30 31 28 66 65 55
+96 95 69 142 137 94 160 154 106 160 154 106 160 154 106 168 163 120
+184 181 136 194 191 148 197 193 154 197 193 154 194 189 146 168 163 120
+125 122 87 46 47 43 18 19 18 15 15 15 13 13 13 14 14 13
+55 57 54 43 45 43 32 34 33 25 27 26 18 22 22 17 17 17
+12 14 14 10 12 12 9 11 11 8 10 10 8 9 9 7 9 9
+6 8 8 7 9 9 7 9 9 7 9 9 7 9 9 7 9 9
+7 9 9 8 9 9 8 9 9 8 10 10 8 10 10 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 32 34 33 41 42 42 35 37 36 39 40 39 37 39 37
+35 37 36 55 57 54 60 60 56 63 64 60 65 66 61 65 66 61
+61 63 57 115 113 82 168 163 120 194 191 148 204 201 155 210 208 158
+210 208 158 210 208 158 197 193 154 194 189 146 186 182 128 176 171 126
+174 170 121 176 171 126 186 182 128 190 186 136 194 191 148 197 193 154
+197 193 154 188 184 146 181 176 137 174 170 121 165 161 109 142 137 94
+82 81 62 24 26 24 16 16 16 16 16 16 16 16 16 16 16 16
+17 17 17 17 17 17 17 17 17 17 17 17 18 19 18 19 20 19
+19 20 19 19 20 19 20 20 20 19 20 19 19 20 19 18 19 18
+17 17 17 15 15 15 13 13 13 12 12 12 6 7 7 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 17 18 17 137 133 100 115 113 82 53 55 47 19 20 18
+103 101 77 144 139 99 137 133 100 115 113 82 137 133 100 156 151 111
+158 153 112 164 159 111 171 165 117 174 170 121 178 174 128 194 189 146
+204 201 155 214 212 158 214 212 158 214 212 158 210 208 158 188 184 146
+158 153 112 87 86 72 17 17 17 13 13 13 13 13 13 15 15 15
+55 56 53 43 45 43 32 34 33 24 26 24 17 20 20 16 16 16
+12 14 14 10 12 12 8 10 10 8 10 10 7 9 9 6 8 8
+6 8 8 6 8 8 6 8 8 7 9 9 7 9 9 7 9 9
+7 9 9 7 9 9 7 9 9 7 9 9 8 9 9 8 10 10
+8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10
+8 10 10 110 109 94 84 83 72 49 51 48 26 28 27 8 10 10
+8 9 9 51 52 50 58 59 55 63 64 60 63 64 60 63 64 60
+66 65 55 134 131 96 181 176 137 210 208 158 214 212 158 239 239 170
+239 239 170 224 223 159 210 208 158 204 201 155 194 189 146 186 182 128
+186 182 128 184 181 136 194 189 146 204 201 155 210 208 158 210 208 158
+210 208 158 210 208 158 197 193 154 190 186 136 176 171 126 155 149 109
+118 116 76 36 38 35 15 15 15 16 16 16 16 16 16 16 16 16
+16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 17 17 17
+17 17 17 17 17 17 17 17 17 16 16 16 16 16 16 15 15 15
+13 13 13 12 12 12 8 8 7 2 2 2 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 53 55 47 103 101 77 96 95 69 53 55 47
+103 101 77 158 153 112 177 172 135 184 179 149 188 184 146 197 193 154
+194 189 146 190 186 136 184 181 136 184 181 136 194 189 146 210 208 158
+214 212 158 239 239 170 251 251 187 251 251 187 224 223 159 204 201 155
+177 172 135 121 119 87 30 31 28 13 13 13 12 12 12 39 40 39
+60 60 56 43 45 43 32 34 33 23 25 24 18 19 18 13 16 16
+13 13 13 9 11 11 8 10 10 8 9 9 6 8 8 6 8 8
+6 8 8 6 8 8 6 8 8 6 8 8 6 8 8 7 9 9
+7 9 9 7 9 9 7 9 9 7 9 9 7 9 9 7 9 9
+7 9 9 8 9 9 8 9 9 8 10 10 8 10 10 8 10 10
+14 17 17 197 193 154 158 153 112 55 57 54 7 9 9 7 9 9
+8 10 10 51 52 50 58 59 55 60 60 56 63 64 60 63 64 60
+71 71 57 155 149 109 194 191 148 214 212 158 251 251 187 251 251 187
+251 251 187 251 251 187 239 239 170 210 208 158 197 193 154 190 186 136
+190 186 136 194 189 146 204 201 155 210 208 158 224 223 159 239 239 170
+239 239 170 224 223 159 210 208 158 204 201 155 190 186 136 164 159 111
+125 122 87 40 41 39 15 15 15 15 15 15 15 15 15 15 15 15
+16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
+16 16 16 16 16 16 15 15 15 14 14 13 13 13 13 12 12 12
+8 9 9 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 21 22 20 96 95 69 125 122 87 121 119 87
+144 139 99 177 172 135 197 193 154 210 208 158 214 212 158 214 212 158
+210 208 158 204 201 155 194 191 148 194 189 146 204 201 155 214 212 158
+239 239 170 251 251 187 251 251 187 251 251 187 251 251 187 214 212 158
+188 184 146 145 141 105 53 55 47 12 12 12 15 15 15 63 64 60
+63 64 60 41 42 42 31 33 31 23 24 24 17 18 17 12 15 15
+11 13 13 9 11 11 8 9 9 7 9 9 6 8 8 6 8 8
+6 7 7 6 7 7 6 8 8 6 8 8 6 8 8 6 8 8
+6 8 8 7 9 9 7 9 9 7 9 9 7 9 9 7 9 9
+7 9 9 7 9 9 7 9 9 7 9 9 7 9 9 8 8 7
+43 45 43 251 251 187 156 151 111 8 10 10 7 9 9 7 9 9
+21 22 21 51 52 50 55 56 53 55 57 54 58 59 55 58 59 55
+75 75 61 158 153 112 197 193 154 224 223 159 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 214 212 158 204 201 155 194 189 146
+190 186 136 197 193 154 210 208 158 224 223 159 251 251 187 251 251 187
+251 251 187 251 251 187 239 239 170 210 208 158 197 193 154 176 171 126
+125 122 87 36 38 35 14 14 13 14 14 13 15 15 15 15 15 15
+15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15
+15 15 15 14 14 13 13 13 13 12 12 12 10 10 9 3 4 4
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 7 7 5 71 71 57 131 127 93 158 153 112
+177 172 135 197 193 154 214 212 158 239 239 170 251 251 187 251 251 187
+238 237 168 210 208 158 204 201 155 197 193 154 204 201 155 214 212 158
+251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 214 212 158
+197 193 154 156 151 111 66 65 55 12 12 12 37 39 37 58 59 55
+58 59 55 41 42 42 31 33 31 22 24 23 17 17 17 12 14 14
+10 12 12 8 10 10 6 8 8 6 8 8 6 7 7 6 7 7
+6 7 7 5 7 7 6 7 7 6 7 7 6 8 8 6 8 8
+6 8 8 6 8 8 6 8 8 7 9 9 7 9 9 7 9 9
+7 9 9 6 8 8 6 8 8 6 8 8 6 8 8 6 8 8
+61 63 57 197 193 154 16 19 19 6 8 8 6 8 8 8 9 9
+41 42 42 47 48 46 51 52 50 51 52 50 55 56 53 55 56 53
+71 71 57 158 153 112 197 193 154 224 223 159 251 251 187 251 251 187
+251 251 187 251 251 187 239 239 170 214 212 158 204 201 155 194 189 146
+190 186 136 197 193 154 210 208 158 239 239 170 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 224 223 159 204 201 155 177 172 135
+121 119 87 30 31 28 13 13 13 14 14 13 14 14 13 14 14 13
+14 14 13 14 14 13 15 15 15 15 15 15 14 14 13 13 13 13
+12 12 12 12 12 12 10 10 9 4 5 5 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 48 49 45 131 127 93 174 170 121
+194 189 146 210 208 158 239 239 170 251 251 187 251 251 187 251 251 187
+251 251 187 214 212 158 204 201 155 197 193 154 204 201 155 210 208 158
+239 239 170 251 251 187 251 251 187 251 251 187 239 239 170 214 212 158
+194 191 148 156 151 111 71 71 57 19 20 19 51 52 50 51 52 50
+51 52 50 41 42 42 30 32 31 21 22 21 17 17 17 13 13 13
+9 11 11 8 9 9 6 8 8 6 7 7 6 7 7 5 7 7
+5 6 5 5 6 5 5 7 7 5 7 7 6 7 7 6 7 7
+6 8 8 6 8 8 6 8 8 6 7 7 6 7 7 6 7 7
+6 7 7 6 8 8 6 8 8 6 8 8 6 8 8 6 8 8
+55 56 53 43 45 43 6 8 8 6 8 8 6 8 8 47 48 46
+60 60 56 47 48 46 46 47 45 47 48 46 38 39 37 10 12 12
+66 65 55 145 141 105 197 193 154 214 212 158 251 251 187 251 251 187
+251 251 187 251 251 187 224 223 159 210 208 158 194 191 148 184 181 136
+184 181 136 194 189 146 204 201 155 224 223 159 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 239 239 170 210 208 158 181 176 137
+115 113 82 21 22 20 13 13 13 13 13 13 13 13 13 13 13 13
+14 14 13 13 13 13 13 13 13 13 13 13 12 12 12 11 11 11
+10 10 9 6 7 7 1 1 1 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 2 2 1 66 65 55 144 139 99 178 174 128
+204 201 155 214 212 158 251 251 187 251 251 187 251 251 187 251 251 187
+251 251 187 214 212 158 204 201 155 194 191 148 197 193 154 204 201 155
+214 212 158 239 239 170 239 239 170 239 239 170 214 212 158 210 208 158
+184 181 136 149 145 103 66 65 55 41 42 42 47 48 46 46 47 45
+43 45 43 39 40 39 28 31 30 21 22 21 16 16 16 10 12 12
+8 10 10 6 8 8 6 7 7 6 7 7 5 6 5 5 6 5
+5 6 5 5 6 5 5 6 5 5 6 5 5 7 7 5 7 7
+6 7 7 6 7 7 6 7 7 5 7 7 5 7 7 5 7 7
+5 7 7 6 7 7 6 7 7 6 7 7 6 7 7 6 8 8
+6 8 8 6 8 8 6 7 7 6 7 7 46 47 45 156 151 111
+105 104 92 58 59 55 43 45 43 32 34 33 6 8 8 6 8 8
+49 51 48 125 122 87 181 176 137 204 201 155 214 212 158 239 239 170
+239 239 170 214 212 158 210 208 158 197 193 154 181 176 137 176 171 126
+176 171 126 184 181 136 197 193 154 210 208 158 239 239 170 251 251 187
+251 251 187 251 251 187 251 251 187 251 251 187 210 208 158 177 172 135
+99 98 80 13 13 13 12 12 12 12 12 12 13 13 13 12 12 12
+12 12 12 12 12 12 11 11 11 11 11 11 8 9 9 4 5 5
+1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 1 1 0 61 61 53 142 137 94 181 176 137
+204 201 155 224 223 159 251 251 187 251 251 187 251 251 187 251 251 187
+251 251 187 214 212 158 197 193 154 190 186 136 184 181 136 188 184 146
+197 193 154 204 201 155 210 208 158 210 208 158 204 201 155 194 189 146
+176 171 126 134 131 96 66 65 55 43 45 43 41 42 42 39 40 39
+35 37 36 33 36 34 27 29 28 20 20 20 15 15 15 9 11 11
+8 9 9 6 7 7 5 6 5 5 6 5 4 5 5 4 5 5
+4 5 5 4 5 5 4 5 5 4 5 5 5 6 5 4 5 5
+4 5 5 5 6 5 4 5 5 5 6 5 5 6 5 5 6 5
+5 7 7 5 7 7 5 7 7 5 7 7 5 7 7 5 7 7
+6 7 7 6 7 7 6 7 7 28 31 30 184 179 149 184 179 149
+145 141 105 84 83 72 27 29 28 5 7 7 5 6 5 16 16 16
+43 44 41 96 95 69 158 153 112 188 184 146 204 201 155 210 208 158
+204 201 155 197 193 154 184 179 149 177 172 135 168 163 120 164 159 111
+164 159 111 174 170 121 184 181 136 197 193 154 214 212 158 251 251 187
+251 251 187 251 251 187 251 251 187 251 251 187 210 208 158 177 172 135
+71 71 57 11 11 11 12 12 12 11 11 11 11 11 11 11 11 11
+10 10 9 10 10 9 8 8 7 3 4 4 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 31 33 31 121 119 87 176 171 126
+197 193 154 214 212 158 251 251 187 251 251 187 251 251 187 251 251 187
+239 239 170 210 208 158 194 189 146 178 174 128 174 170 121 176 171 126
+177 172 135 181 176 137 184 179 149 184 179 149 181 176 137 178 174 128
+158 153 112 121 119 87 53 55 47 37 39 37 33 36 34 30 32 31
+27 29 28 25 27 26 24 26 24 19 20 19 13 13 13 8 10 10
+6 8 8 6 7 7 5 6 5 4 5 5 4 5 5 4 5 5
+4 5 5 4 5 5 4 5 5 3 4 4 3 4 4 4 5 5
+4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5
+5 6 5 5 6 5 5 6 5 5 6 5 5 6 5 5 6 5
+5 6 5 5 6 5 12 14 14 145 141 105 184 179 149 177 172 135
+90 89 73 21 22 21 5 6 5 5 6 5 4 5 5 37 39 37
+38 39 37 61 61 53 134 131 96 168 163 120 184 181 136 188 184 146
+184 179 149 177 172 135 168 163 120 164 159 111 155 149 109 151 147 98
+151 147 98 164 159 111 176 171 126 184 179 149 210 208 158 239 239 170
+251 251 187 251 251 187 251 251 187 239 239 170 210 208 158 158 153 112
+46 47 43 10 10 9 10 10 9 10 10 9 8 9 9 8 9 9
+6 7 7 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 13 12 7 82 81 62 158 153 112
+188 184 146 210 208 158 239 239 170 251 251 187 251 251 187 251 251 187
+224 223 159 204 201 155 184 181 136 171 165 117 164 159 111 160 154 106
+158 153 112 164 159 111 168 163 120 168 163 120 168 163 120 164 159 111
+142 137 94 96 95 69 43 44 41 27 29 28 26 28 27 23 24 24
+21 22 21 18 19 18 17 17 17 18 19 18 13 13 13 8 8 7
+6 7 7 5 6 5 4 5 5 3 4 4 3 4 4 3 4 4
+3 4 4 3 4 4 3 3 3 3 3 3 3 4 4 3 4 4
+3 4 4 3 4 4 4 5 5 4 5 5 4 5 5 4 5 5
+4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5
+4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5
+4 5 5 4 5 5 4 5 5 4 5 5 31 33 31 65 66 61
+37 39 37 38 39 37 96 95 69 144 139 99 168 163 120 174 170 121
+168 163 120 164 159 111 155 149 109 149 145 103 149 143 98 142 137 94
+149 143 98 151 147 98 164 159 111 177 172 135 197 193 154 210 208 158
+251 251 187 251 251 187 251 251 187 239 239 170 197 193 154 137 133 100
+24 26 24 8 9 9 8 9 9 8 8 7 6 7 7 2 2 2
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 46 47 43 125 122 87
+176 171 126 197 193 154 210 208 158 239 239 170 251 251 187 239 239 170
+214 212 158 197 193 154 181 176 137 164 159 111 151 147 98 149 143 98
+149 143 98 149 143 98 149 145 103 155 149 109 160 154 106 149 143 98
+118 116 76 82 81 62 30 31 28 21 22 21 19 20 19 17 17 17
+14 14 13 12 12 12 10 10 9 12 12 12 10 12 12 6 8 8
+4 5 5 3 4 4 3 4 4 3 4 4 3 3 3 3 3 3
+3 3 3 3 3 3 3 3 3 3 3 3 2 3 3 2 3 3
+3 4 4 3 4 4 3 4 4 3 4 4 3 4 4 4 5 5
+4 5 5 3 4 4 3 4 4 3 4 4 3 4 4 3 4 4
+4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5
+4 5 5 3 4 4 3 4 4 23 24 24 110 109 94 72 73 67
+39 40 39 22 24 23 46 47 43 103 101 77 142 137 94 155 149 109
+160 154 106 155 149 109 149 143 98 142 137 94 142 137 94 142 137 94
+142 137 94 149 143 98 155 149 109 176 171 126 184 179 149 210 208 158
+239 239 170 251 251 187 251 251 187 214 212 158 184 179 149 105 104 92
+10 10 9 6 7 7 3 4 4 1 1 1 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 12 12 9 82 81 62
+149 145 103 181 176 137 197 193 154 210 208 158 214 212 158 214 212 158
+210 208 158 197 193 154 177 172 135 158 153 112 149 143 98 142 137 94
+142 137 94 142 137 94 149 143 98 151 147 98 151 147 98 131 127 93
+103 101 77 71 71 57 22 24 23 15 15 15 13 13 13 11 11 11
+8 9 9 6 7 7 6 7 7 4 5 5 8 9 9 6 7 7
+4 5 5 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2
+2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3
+2 3 3 2 3 3 2 3 3 3 4 4 3 4 4 3 4 4
+3 4 4 3 4 4 3 3 3 3 4 4 3 4 4 3 4 4
+3 4 4 3 4 4 3 4 4 3 4 4 3 4 4 3 4 4
+3 4 4 3 4 4 21 22 21 145 141 105 145 141 105 72 73 67
+17 18 17 3 4 4 21 22 20 66 65 55 118 116 76 142 137 94
+149 143 98 151 147 98 149 143 98 142 137 94 142 137 94 142 137 94
+142 137 94 149 143 98 155 149 109 168 163 120 184 179 149 210 208 158
+239 239 170 251 251 187 251 251 187 210 208 158 177 172 135 71 71 57
+3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 38 35
+115 113 82 158 153 112 181 176 137 197 193 154 204 201 155 210 208 158
+204 201 155 188 184 146 177 172 135 164 159 111 149 145 103 142 137 94
+142 137 94 142 137 94 149 143 98 151 147 98 149 143 98 125 122 87
+96 95 69 61 61 53 16 17 12 8 9 9 8 8 7 6 7 7
+4 5 5 3 4 4 3 3 3 3 3 3 3 3 3 5 6 5
+3 4 4 2 3 3 2 2 2 2 2 2 2 2 2 2 2 2
+2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2
+2 2 2 2 2 2 2 3 3 2 3 3 2 3 3 2 3 3
+3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+3 3 3 2 3 3 2 3 3 3 4 4 3 4 4 3 4 4
+3 4 4 3 4 4 3 4 4 8 9 9 8 8 7 3 3 3
+3 3 3 3 3 3 9 9 8 36 38 35 82 81 62 118 116 76
+142 137 94 151 147 98 151 147 98 151 147 98 149 143 98 149 143 98
+149 143 98 151 147 98 160 154 106 176 171 126 188 184 146 210 208 158
+239 239 170 251 251 187 239 239 170 210 208 158 156 151 111 31 33 31
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 5
+66 65 55 125 122 87 158 153 112 181 176 137 194 189 146 197 193 154
+197 193 154 184 179 149 177 172 135 168 163 120 156 151 111 151 147 98
+151 147 98 151 147 98 151 147 98 161 156 96 149 143 98 118 116 76
+82 81 62 53 55 47 12 12 9 4 5 5 3 4 4 3 3 3
+3 3 3 3 3 3 2 2 2 2 2 2 1 1 1 1 2 2
+3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 2
+1 2 2 1 2 2 1 2 2 2 2 2 2 2 2 2 3 3
+2 3 3 2 3 3 2 3 3 2 3 3 2 2 2 2 2 2
+2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3
+2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 3 3 3
+3 3 3 3 3 3 72 73 67 61 61 53 53 55 47 96 95 69
+131 127 93 151 147 98 161 156 96 161 156 96 151 147 98 151 147 98
+161 156 96 160 154 106 164 159 111 177 172 135 197 193 154 210 208 158
+239 239 170 251 251 187 224 223 159 197 193 154 131 127 93 9 9 8
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+24 26 24 82 81 62 131 127 93 164 159 111 178 174 128 188 184 146
+188 184 146 188 184 146 181 176 137 176 171 126 168 163 120 164 159 111
+160 154 106 160 154 106 160 154 106 160 154 106 151 147 98 125 122 87
+82 81 62 61 61 53 12 12 9 3 3 3 3 3 3 2 2 2
+2 2 2 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
+0 0 0 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 2 2 1 2 2 1 2 2 1 2 2
+1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3
+2 3 3 30 32 31 72 73 67 31 33 31 36 38 35 82 81 62
+118 116 76 149 143 98 161 156 96 161 156 96 161 156 96 160 154 106
+165 161 109 165 161 109 176 171 126 188 184 146 204 201 155 214 212 158
+239 239 170 239 239 170 214 212 158 184 179 149 82 81 62 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+2 2 2 43 44 41 96 95 69 131 127 93 160 154 106 176 171 126
+184 181 136 184 181 136 184 181 136 181 176 137 178 174 128 174 170 121
+171 165 117 173 167 111 173 167 111 173 167 111 160 154 106 131 127 93
+96 95 69 66 65 55 16 17 12 2 2 2 1 1 1 1 1 1
+1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2
+2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+2 2 2 2 2 2 2 2 2 10 9 6 30 31 28 71 71 57
+118 116 76 149 143 98 165 161 109 165 161 109 165 161 109 173 167 111
+173 167 111 176 171 126 184 181 136 197 193 154 210 208 158 224 223 159
+251 251 187 239 239 170 210 208 158 168 163 120 40 41 39 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 13 12 7 61 61 53 96 95 69 131 127 93 160 154 106
+176 171 126 184 181 136 184 181 136 188 184 146 184 181 136 184 181 136
+184 181 136 186 182 128 186 182 128 178 174 128 174 170 121 149 145 103
+118 116 76 82 81 62 21 22 20 1 1 1 1 1 1 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2
+1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2
+2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+2 2 2 2 2 2 2 2 2 3 3 3 30 31 28 66 65 55
+118 116 76 149 143 98 165 161 109 173 167 111 173 167 111 174 170 121
+186 182 128 190 186 136 197 193 154 210 208 158 224 223 159 251 251 187
+251 251 187 239 239 170 197 193 154 137 133 100 12 12 9 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 30 31 28 71 71 57 103 101 77 134 131 96
+164 159 111 176 171 126 184 181 136 188 184 146 194 189 146 197 193 154
+197 193 154 197 193 154 194 191 148 194 189 146 190 186 136 176 171 126
+145 141 105 103 101 77 40 41 39 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 2
+1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2
+1 2 2 1 2 2 1 2 2 1 2 2 30 31 28 71 71 57
+118 116 76 160 154 106 173 167 111 178 174 128 186 182 128 190 186 136
+194 191 148 204 201 155 210 208 158 224 223 159 251 251 187 251 251 187
+251 251 187 214 212 158 184 179 149 84 83 72 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 5 5 3 43 44 41 82 81 62 103 101 77
+142 137 94 165 161 109 178 174 128 190 186 136 197 193 154 204 201 155
+210 208 158 210 208 158 210 208 158 210 208 158 210 208 158 197 193 154
+177 172 135 145 141 105 79 78 62 5 4 3 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 2 2 1 2 2 30 31 28 82 81 62
+142 137 94 165 161 109 178 174 128 190 186 136 194 191 148 204 201 155
+210 208 158 214 212 158 239 239 170 251 251 187 251 251 187 251 251 187
+251 251 187 210 208 158 168 163 120 36 38 35 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 16 17 12 53 55 47 82 81 62
+118 116 76 151 147 98 171 165 117 184 181 136 194 191 148 210 208 158
+214 212 158 224 223 159 239 239 170 239 239 170 224 223 159 214 212 158
+197 193 154 176 171 126 115 113 82 24 26 24 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 40 41 39 103 101 77
+151 147 98 176 171 126 190 186 136 197 193 154 210 208 158 214 212 158
+239 239 170 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187
+239 239 170 197 193 154 110 109 94 3 4 3 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 30 31 28 66 65 55
+96 95 69 125 122 87 160 154 106 178 174 128 194 189 146 204 201 155
+214 212 158 239 239 170 251 251 187 251 251 187 251 251 187 239 239 170
+210 208 158 188 184 146 149 145 103 61 61 53 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 61 61 53 131 127 93
+164 159 111 184 181 136 197 193 154 210 208 158 224 223 159 251 251 187
+251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187
+210 208 158 168 163 120 43 44 41 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 36 38 35
+71 71 57 96 95 69 142 137 94 165 161 109 184 181 136 197 193 154
+210 208 158 239 239 170 251 251 187 251 251 187 251 251 187 251 251 187
+214 212 158 197 193 154 168 163 120 103 101 77 7 7 5 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1 1 1 0 0 0 0 0 0 0 0 0 82 81 62 142 137 94
+174 170 121 194 189 146 210 208 158 224 223 159 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 224 223 159
+184 179 149 99 98 80 3 3 3 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 5
+43 44 41 82 81 62 118 116 76 142 137 94 171 165 117 190 186 136
+204 201 155 224 223 159 251 251 187 251 251 187 251 251 187 251 251 187
+214 212 158 197 193 154 174 170 121 125 122 87 30 31 28 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
+1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 3 4 3 82 81 62 149 143 98
+176 171 126 194 191 148 210 208 158 239 239 170 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 251 251 187 239 239 170 204 201 155
+145 141 105 30 31 28 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+10 9 6 46 47 43 82 81 62 118 116 76 149 143 98 174 170 121
+194 189 146 210 208 158 224 223 159 251 251 187 251 251 187 224 223 159
+210 208 158 194 191 148 174 170 121 134 131 96 53 55 47 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 7 7 5 96 95 69 149 143 98
+176 171 126 194 191 148 210 208 158 239 239 170 251 251 187 251 251 187
+251 251 187 251 251 187 251 251 187 239 239 170 210 208 158 177 172 135
+75 75 61 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 10 9 6 46 47 43 82 81 62 118 116 76 149 143 98
+176 171 126 194 191 148 210 208 158 214 212 158 214 212 158 210 208 158
+197 193 154 184 181 136 164 159 111 131 127 93 53 55 47 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 7 7 5 96 95 69 149 143 98
+174 170 121 194 189 146 204 201 155 214 212 158 239 239 170 251 251 187
+251 251 187 251 251 187 239 239 170 210 208 158 184 179 149 110 109 94
+12 12 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 10 9 6 43 44 41 82 81 62 115 113 82
+144 139 99 168 163 120 188 184 146 197 193 154 197 193 154 194 189 146
+184 181 136 174 170 121 151 147 98 118 116 76 36 38 35 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 4 3 2 82 81 62 142 137 94
+171 165 117 186 182 128 194 191 148 210 208 158 214 212 158 224 223 159
+239 239 170 224 223 159 210 208 158 184 179 149 137 133 100 36 38 35
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 7 7 5 36 38 35 71 71 57
+103 101 77 131 127 93 155 149 109 168 163 120 168 163 120 168 163 120
+164 159 111 149 143 98 125 122 87 82 81 62 13 12 7 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 61 61 53 125 122 87
+160 154 106 174 170 121 184 181 136 194 189 146 204 201 155 210 208 158
+210 208 158 204 201 155 184 179 149 145 141 105 61 61 53 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 3 3 2 30 31 28
+61 61 53 82 81 62 103 101 77 121 119 87 125 122 87 125 122 87
+118 116 76 103 101 77 79 78 62 24 26 24 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 25 27 25 96 95 69
+142 137 94 160 154 106 171 165 117 178 174 128 184 181 136 184 181 136
+181 176 137 177 172 135 145 141 105 75 75 61 5 5 3 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+16 17 12 40 41 39 61 61 53 71 71 57 71 71 57 71 71 57
+66 65 55 43 44 41 12 12 9 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 46 47 43
+96 95 69 125 122 87 142 137 94 149 145 103 155 149 109 155 149 109
+145 141 105 121 119 87 66 65 55 7 7 5 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 1 1 1 16 17 12 24 26 24 25 27 25 19 20 18
+7 7 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1
+25 27 25 61 61 53 82 81 62 96 95 69 96 95 69 82 81 62
+61 61 53 25 27 25 2 2 1 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 5 6 5 13 12 7 10 9 6 3 4 3
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0
diff --git a/drivers/video/logo/logo_linux_vga16.ppm b/drivers/video/logo/logo_linux_vga16.ppm
index 1850c15e6fe..12ac3a5454c 100644
--- a/drivers/video/logo/logo_linux_vga16.ppm
+++ b/drivers/video/logo/logo_linux_vga16.ppm
@@ -1,1604 +1,2739 @@
P3
-# Standard 16-color Linux logo
-80 80
+142 114
255
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 85 85 85 85 85 85 85 85 85
- 85 85 85 85 85 85 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 85 85 85
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 85 85 85 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 170 170 170 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
-170 170 170 170 170 170 85 85 85 0 0 0
- 0 0 0 0 0 0 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 85 85 85 170 170 170 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 170 170 170 170 170 170
-170 170 170 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 85 85 85 170 170 170 170 170 170 170 170 170
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 170 170 170 255 255 255 255 255 255
-255 255 255 170 170 170 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 85 85 85
-170 170 170 170 170 170 255 255 255 255 255 255
- 0 0 0 0 0 0 0 0 0 0 0 0
-170 170 170 255 255 255 170 170 170 170 170 170
-255 255 255 170 170 170 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 85 85 85
-170 170 170 0 0 0 0 0 0 255 255 255
- 85 85 85 0 0 0 0 0 0 0 0 0
-255 255 255 170 170 170 0 0 0 85 85 85
-170 170 170 255 255 255 170 170 170 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 85 85 85
- 85 85 85 0 0 0 0 0 0 170 170 170
- 85 85 85 0 0 0 0 0 0 0 0 0
-255 255 255 85 85 85 0 0 0 0 0 0
- 85 85 85 255 255 255 170 170 170 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 85 85 85
-170 170 170 0 0 0 0 0 0 170 170 170
- 85 85 85 85 85 85 85 85 85 85 85 85
-255 255 255 85 85 85 0 0 0 0 0 0
- 85 85 85 255 255 255 170 170 170 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
-255 255 255 0 0 0 0 0 0 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 0 0 0 0 0 0
- 85 85 85 255 255 255 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
-170 170 170 170 170 170 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 170 170 170 170 170 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 85 85 85 0 0 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 170 85 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 85 85 85 0 0 0
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 170 85 0
-170 85 0 170 85 0 85 85 85 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 85 85 85 0 0 0
- 85 85 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-170 85 0 170 85 0 170 85 0 170 85 0
-170 85 0 170 85 0 85 85 85 0 0 0
- 0 0 0 85 85 85 170 170 170 85 85 85
- 0 0 0 0 0 0 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 85 85 85 0 0 0
- 85 85 85 170 85 0 170 85 0 170 85 0
-170 85 0 170 85 0 170 85 0 170 85 0
-170 85 0 170 85 0 170 85 0 170 85 0
-170 170 170 170 170 170 170 170 170 0 0 0
- 0 0 0 0 0 0 170 170 170 170 170 170
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 85 85 85 170 170 170 170 85 0 170 85 0
-170 85 0 170 85 0 170 85 0 170 85 0
-170 85 0 170 85 0 170 170 170 170 170 170
-170 170 170 170 170 170 170 170 170 85 85 85
- 0 0 0 0 0 0 85 85 85 85 85 85
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 85 85 85 170 170 170 170 170 170 170 85 0
-170 85 0 170 85 0 170 85 0 170 85 0
-170 170 170 170 170 170 170 170 170 170 170 170
-255 255 255 255 255 255 255 255 255 170 170 170
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 85 85 85
-255 255 255 255 255 255 170 170 170 170 170 170
-170 170 170 170 170 170 170 170 170 170 170 170
-170 170 170 170 170 170 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 170 170 170
-255 255 255 255 255 255 170 170 170 170 170 170
-170 170 170 170 170 170 170 170 170 170 170 170
-170 170 170 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-170 170 170 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 85 85 85 255 255 255
-255 255 255 255 255 255 255 255 255 170 170 170
-170 170 170 170 170 170 170 170 170 170 170 170
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 0 0 0
- 0 0 0 85 85 85 170 170 170 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 85 85 85 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 170 170 170 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 85 85 85 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 85 85 85 170 170 170 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 170 170 170 170 170 170 170 170 170
-255 255 255 255 255 255 255 255 255 170 170 170
-170 170 170 170 170 170 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-170 170 170 170 170 170 170 170 170 170 170 170
-170 170 170 170 170 170 170 170 170 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
-170 170 170 170 170 170 170 170 170 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-170 170 170 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 170 170 170
-170 170 170 170 170 170 170 170 170 85 85 85
- 0 0 0 0 0 0 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
-170 170 170 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 170 170 170 170 170 170 170 170 170
- 0 0 0 0 0 0 0 0 0 85 85 85
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 0 0 0
- 85 85 85 0 0 0 0 0 0 85 85 85
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 170 170 170
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 170 170 170
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-170 170 170 85 85 85 0 0 0 0 0 0
- 0 0 0 85 85 85 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 85 85 85
- 0 0 0 0 0 0 85 85 85 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 170 170 170 0 0 0 85 85 85
- 85 85 85 0 0 0 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 85 85 85
- 0 0 0 85 85 85 170 170 170 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 170 170 170 0 0 0 85 85 85
- 85 85 85 0 0 0 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 85 85 85
- 0 0 0 170 170 170 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 85 85 85 0 0 0
- 0 0 0 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 85 85 85 0 0 0
- 85 85 85 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 85 85 85 0 0 0 0 0 0
-170 170 170 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 85 85 85
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 85 85 85
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 85 85 85
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 0 0 0
- 85 85 85 85 85 85 85 85 85 85 85 85
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 0 0 0 170 85 0
-255 255 85 170 85 0 0 0 0 0 0 0
- 85 85 85 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 85 85 85 85 85 85 0 0 0
- 0 0 0 85 85 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 0 0 0
- 0 0 0 85 85 85 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 85 170 85 0 255 255 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 85 85 85
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
- 0 0 0 0 0 0 85 85 85 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 85
-170 85 0 255 255 85 170 85 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
-170 85 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 0 0 0 0 0 0 85 85 85
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 170 85 0
-255 255 85 170 85 0 255 255 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 170 85 0
-255 255 85 170 85 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 0 0 0 0 0 0 0 0 0
- 85 85 85 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 85
-170 85 0 255 255 85 170 85 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 255 255 85
-170 85 0 255 255 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 0 0 0 0 0 0
- 0 0 0 85 85 85 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 255 255 85 170 85 0
-255 255 85 170 85 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 0 0 0
- 0 0 0 0 0 0 85 85 85 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 170 170 170 170 170 170 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 170 170 170 170 170 170 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 170 170 170 170 170 170 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 0 0 0 0 0 0 0 0 0
- 0 0 0 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 170 170 170 170 170 170 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 0 0 0 0 0 0 0 0 0
- 85 85 85 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 170 170 170 85 85 85 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 85 85 85 85 85 85
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-170 170 170 85 85 85 85 85 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 170 170 170
- 85 85 85 0 0 0 0 0 0 170 85 0
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 85 85 85
- 0 0 0 0 0 0 0 0 0 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-170 170 170 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-170 170 170 85 85 85 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 170 85 0
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 170 85 0
-170 85 0 170 170 170 255 255 255 255 255 255
-255 255 255 255 255 255 255 255 255 255 255 255
-255 255 255 255 255 255 170 170 170 85 85 85
- 85 85 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-170 85 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 170 85 0
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 170 85 0 170 85 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 170 85 0
-170 85 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-170 85 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-170 85 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 85 85 85 170 85 0
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 170 85 0 170 85 0 170 85 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 170 85 0 170 85 0
-170 85 0 170 85 0 170 85 0 170 85 0
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 170 85 0
-170 85 0 0 0 0 0 0 0 0 0 0
- 85 85 85 85 85 85 85 85 85 85 85 85
- 85 85 85 85 85 85 85 85 85 85 85 85
- 85 85 85 85 85 85 85 85 85 0 0 0
- 0 0 0 0 0 0 0 0 0 170 85 0
-170 85 0 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 255 255 85 170 85 0
-170 85 0 170 85 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 170 85 0 170 85 0
-170 85 0 170 85 0 170 85 0 170 85 0
-170 85 0 170 85 0 255 255 85 170 85 0
-255 255 85 170 85 0 170 85 0 170 85 0
- 85 85 85 85 85 85 85 85 85 85 85 85
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 85 85 85
- 85 85 85 85 85 85 85 85 85 170 85 0
-170 85 0 170 85 0 170 85 0 255 255 85
-170 85 0 255 255 85 170 85 0 170 85 0
-170 85 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 170 85 0
-170 85 0 170 85 0 170 85 0 170 85 0
-170 85 0 170 85 0 170 85 0 170 85 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 170 85 0
-170 85 0 170 85 0 170 85 0 170 85 0
-170 85 0 170 85 0 170 85 0 170 85 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 170 85 0 170 85 0 170 85 0
-170 85 0 170 85 0 170 85 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
-170 85 0 170 85 0 170 85 0 170 85 0
-170 85 0 170 85 0 170 85 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 85 85 85 0 0 0 85 85 85 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 85 85 85 85 85 85 85 85 85
+0 0 0 85 85 85 85 85 85 0 0 0 85 85 85 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170
+85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+85 85 85 0 0 0 85 85 85 85 85 85 85 85 85 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 170 170 170 170 85 0 170 170 170 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+170 170 170 255 255 85 170 170 170 170 170 170 170 170 170 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170
+255 255 85 170 170 170 170 170 170 170 85 0 85 255 85 170 85 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 170 170 170 170 85 0
+170 170 170 170 170 170 255 255 85 170 170 170 170 170 170 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 85 85 85 170 85 0 170 170 170
+170 170 170 170 85 0 170 170 170 170 170 170 170 85 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 85 85 85 85 85 85 85 255 85
+255 85 85 85 255 85 170 170 170 170 85 0 170 170 170 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 170 85 0 85 85 85 85 85 85
+170 170 170 170 85 0 170 170 170 85 85 85 170 85 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 85 85 85 170 85 0
+85 85 85 85 85 85 170 85 0 85 255 85 85 85 85 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 170 85 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 170 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+170 85 0 85 255 85 170 85 0 170 85 0 170 85 0 85 255 85
+170 85 0 170 85 0 0 170 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 170 0 170 85 0
+255 255 85 170 85 0 255 255 85 255 255 85 255 255 85 170 85 0
+255 255 85 85 255 85 170 85 0 170 85 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 170 85 0 255 255 85
+85 255 85 255 255 85 255 255 85 170 85 0 255 255 85 255 255 85
+255 255 85 170 85 0 255 255 85 85 255 85 170 85 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 255 255 85 170 85 0
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 170 85 0
+255 255 85 255 255 85 255 255 85 255 255 85 170 85 0 85 255 85
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 170 170 170 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 170 85 0 255 255 85 255 255 85
+255 255 85 255 255 85 170 85 0 255 255 85 85 255 85 255 255 85
+255 255 85 170 85 0 255 255 85 170 85 0 255 255 85 170 85 0
+170 85 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 170 170 170 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 170 85 0 255 255 85 85 255 85 255 255 85
+170 170 170 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 255 255 85 85 255 85 255 255 85 255 255 85 255 255 85
+85 255 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 170 85 0 255 255 85 255 255 85 255 255 85
+255 255 255 255 255 85 255 255 85 170 85 0 255 255 85 170 85 0
+255 255 85 255 255 85 255 255 85 255 255 85 170 85 0 255 255 85
+170 85 0 170 85 0 0 170 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 170 85 0 85 255 85 255 255 85 170 170 170 255 255 255
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 255 255 85 170 85 0 255 255 85 85 255 85 255 255 85
+255 255 85 85 255 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 255 255 85 255 255 85 255 255 85 255 255 255 255 255 85
+255 255 85 255 255 85 85 255 85 255 255 85 255 255 85 85 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 170 85 0
+255 255 85 170 85 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+85 85 85 0 0 0 85 85 85 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+170 85 0 170 85 0 255 255 85 255 255 85 255 255 255 170 170 170
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+170 85 0 255 255 85 255 255 85 170 85 0 255 255 85 255 255 85
+255 255 85 85 255 85 170 85 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+255 255 85 85 255 85 255 255 85 170 170 170 255 255 255 255 255 85
+255 255 85 255 255 85 170 85 0 255 255 85 255 255 85 255 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 85 255 85 170 85 0
+255 255 85 170 85 0 170 85 0 0 0 0 85 85 85 0 0 0
+85 85 85 85 85 85 85 85 85 170 170 170 170 170 170 170 170 170
+85 255 85 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 170 170 170 255 255 85 170 170 170
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 170 0
+170 85 0 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 255 255 85 85 255 85 255 255 85 170 85 0 170 85 0
+170 85 0 85 255 85 255 255 85 85 85 85 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 85 255 85 170 170 170 170 170 170
+85 85 85 170 170 170 170 170 170 170 85 0 170 170 170 170 170 170
+85 255 85 170 170 170 170 85 0 170 170 170 85 255 85 255 85 85
+85 255 85 170 170 170 255 255 85 85 85 85 255 255 85 170 170 170
+85 255 85 170 170 170 255 255 85 170 170 170 170 170 170 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 255 255 85
+255 255 85 255 255 85 255 255 85 255 255 255 255 255 85 255 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 170 85 0
+255 255 85 255 255 85 255 255 85 170 85 0 0 170 0 85 85 85
+170 170 170 170 170 170 255 255 85 170 170 170 170 170 170 85 255 85
+255 85 85 85 255 85 85 85 85 255 85 85 85 85 85 170 170 170
+170 85 0 170 170 170 85 85 85 85 255 85 85 85 85 85 85 85
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 255 255 85
+170 85 0 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 255 255 85 170 85 0 255 255 85 85 85 85 85 85 85
+255 255 85 170 170 170 85 85 85 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 85 85 85 170 170 170 170 85 0 170 170 170
+170 170 170 255 255 85 170 170 170 85 85 85 85 85 85 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 170 85 0 255 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 255 255 85 255 255 85 170 85 0 170 85 0 0 170 0
+0 0 0 170 85 0 170 85 0 0 170 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 85 85 85 170 170 170 85 85 85
+170 170 170 85 85 85 85 85 85 170 170 170 170 85 0 85 85 85
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 255 255 85 170 85 0
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 170 85 0
+255 255 85 255 255 85 255 255 85 170 85 0 255 255 85 255 255 85
+170 85 0 255 255 85 85 255 85 255 255 85 255 255 85 170 85 0
+170 85 0 255 255 85 170 85 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 255 255 85 255 255 85
+255 255 85 255 255 85 170 85 0 255 255 85 255 255 85 255 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 255 255 85 255 255 85 170 85 0 255 255 85 255 255 85
+85 255 85 170 85 0 0 170 0 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 170 0 170 85 0 255 255 85
+85 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+170 85 0 255 255 85 85 255 85 255 255 85 255 255 85 170 85 0
+85 255 85 170 85 0 170 85 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 170 85 0 255 255 85 255 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 170 85 0 255 255 85 85 255 85 255 255 85 170 85 0
+255 255 85 255 255 85 170 85 0 255 255 85 170 85 0 85 255 85
+170 85 0 170 85 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 255 255 85 170 85 0
+255 255 85 170 85 0 255 255 85 170 85 0 255 255 85 85 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 170 85 0 255 255 85 85 255 85 170 85 0 170 85 0
+0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 170 85 0 255 255 85 255 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 255 255 85 170 85 0 255 255 85 170 85 0 85 255 85
+255 255 85 85 255 85 170 85 0 170 85 0 85 255 85 170 85 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 255 255 85 85 255 85
+255 255 85 255 255 85 85 255 85 255 255 85 255 255 85 255 255 85
+255 255 85 170 85 0 255 255 85 85 255 85 255 255 85 255 255 85
+170 85 0 170 85 0 85 255 85 170 85 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 85 85 85 170 170 170 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 85 85 85
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 255 255 85 255 255 85
+170 85 0 255 255 85 255 255 85 170 85 0 255 255 85 170 85 0
+255 255 85 85 255 85 170 85 0 255 255 85 170 85 0 85 255 85
+170 85 0 170 85 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 170 170 170 170 170 170 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 85 85 85 85 85 85 85 85 85
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 170 85 0 255 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 255 255 85 85 255 85
+170 85 0 255 255 85 170 85 0 85 255 85 170 85 0 170 85 0
+0 170 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 170 170 170 170 170 170 255 255 255 170 170 170
+170 170 170 170 170 170 85 85 85 85 85 85 85 85 85 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 255 85 255 255 85
+170 85 0 255 255 85 255 255 85 170 85 0 85 255 85 170 85 0
+255 255 85 170 85 0 0 170 0 170 85 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 170 170 170 170 170 170 170 170 170 85 85 85
+85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 255 255 85
+255 255 85 255 255 85 255 255 85 255 255 85 170 85 0 170 85 0
+0 170 0 85 85 85 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+255 255 85 255 255 85 170 85 0 0 170 0 85 85 85 85 85 85
+85 85 85 85 85 85 0 0 0 85 85 85 85 85 85 0 0 0
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 85 85 85 85 85 85 170 170 170 170 170 170 85 85 85
+170 170 170 170 170 170 170 170 170 170 170 170 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 170 85 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 85 85 85 85 85 85 170 170 170 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85
+170 170 170 170 170 170 170 170 170 170 170 170 255 255 255 255 255 255
+255 255 255 255 255 255 255 255 255 170 170 170 255 255 255 170 170 170
+170 170 170 170 170 170 170 170 170 85 85 85 85 85 85 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 170 170 170 170 170 170
+255 255 255 255 255 255 255 255 255 170 170 170 255 255 255 170 170 170
+255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
+255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
+255 255 255 255 255 255 170 170 170 255 255 255 170 170 170 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 170 170 170 170 170 170
+255 255 255 170 170 170 255 255 255 255 255 255 255 255 255 255 255 255
+255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 170 170 170
+255 255 255 255 255 255 170 170 170 255 255 255 255 255 255 255 255 255
+255 255 255 255 255 255 255 255 255 255 255 255 170 170 170 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 170 170 170
+170 170 170 170 170 170 255 255 255 170 170 170 255 255 255 170 170 170
+255 255 255 170 170 170 255 255 255 170 170 170 255 255 255 255 255 255
+255 255 255 170 170 170 255 255 255 170 170 170 255 255 255 170 170 170
+170 170 170 170 170 170 170 170 170 170 170 170 85 85 85 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+85 85 85 85 85 85 85 85 85 0 0 0 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 170 170 170 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 170 170 170 85 85 85 170 170 170
+170 170 170 170 170 170 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+170 170 170 85 85 85 85 85 85 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 85 85 85
+85 85 85 85 85 85 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 85 85 85 170 170 170 85 85 85
+85 85 85 85 85 85 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 85 85 85 170 170 170 85 85 85 85 85 85
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 170 170 170 170 170 170
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 170 170 170 85 85 85 85 85 85 85 85 85
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 170 170 170 255 255 255 170 170 170
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 170 170 170
+170 170 170 255 255 255 170 170 170 170 170 170
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 170 170 170 85 85 85 85 85 85 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 170 170 170
+255 255 255 255 255 255 170 170 170 170 170 170
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 170 170 170 170 170 170 255 255 255
+255 255 255 170 170 170 170 170 170 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+170 170 170 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 170 170 170 255 255 255 255 255 255 255 255 255
+170 170 170 170 170 170 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+170 170 170 170 170 170 255 255 255 255 255 255 255 255 255 170 170 170
+170 170 170 170 170 170 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 170 170 170
+170 170 170 255 255 255 255 255 255 255 255 255 170 170 170 170 170 170
+170 170 170 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 85 85 85 85 85 85 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 170 170 170 170 170 170 170 170 170
+255 255 255 255 255 255 255 255 255 255 255 255 170 170 170 170 170 170
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 170 170 170 170 170 170 255 255 255 255 255 255 255 255 255
+255 255 255 255 255 255 170 170 170 170 170 170 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 170 170 170 255 255 255 85 85 85 85 85 85
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 170 170 170 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+170 170 170 170 170 170 255 255 255 170 170 170 255 255 255 255 255 255
+255 255 255 255 255 255 170 170 170 170 170 170 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 170 170 170 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 170 170 170 255 255 255 170 170 170 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+255 255 255 170 170 170 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
+170 170 170 170 170 170 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 255 255 255 170 170 170 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 85 85 85 85 85 85 0 0 0
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 255 255 255 255 255 255 255 255 255 85 85 85
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 170 170 170
+255 255 255 170 170 170 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 170 170 170 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 170 170 170
+170 170 170 255 255 255 255 255 255 255 255 255 255 255 255 170 170 170
+170 170 170 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+170 170 170 255 255 255 255 255 255 170 170 170 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 85 85 85 85 85 85 0 0 0
+85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+85 85 85 170 170 170 255 255 255 255 255 255 255 255 255 85 85 85
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 255 255 255
+255 255 255 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 170 170 170 170 170 170 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 85 85 85 85 85 85 85 85 85
+170 170 170 255 255 255 255 255 255 255 255 255 170 170 170 170 170 170
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 170 170 170
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+170 170 170 255 255 255 255 255 255 255 255 255 85 85 85 0 0 0
+0 0 0 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 170 170 170 255 255 255 255 255 255 255 255 255 170 170 170
+0 0 0 85 85 85 0 0 0 85 85 85 170 170 170 255 255 255
+255 255 255 170 170 170 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 255 255 255 255 255 255 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 85 85 85 0 0 0 85 85 85 85 85 85
+170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 255 255 255
+170 170 170 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 255 255 255 255 255 255 255 255 255 255 255 255 0 0 0
+0 0 0 85 85 85 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85
+85 85 85 255 255 255 255 255 255 255 255 255 170 170 170 170 170 170
+85 85 85 0 0 0 0 0 0 85 85 85 170 170 170 255 255 255
+255 255 255 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0
+170 170 170 255 255 255 170 170 170 0 0 0 0 0 0 0 0 0
+85 85 85 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 85 85 85 0 0 0 85 85 85 85 85 85 0 0 0
+85 85 85 85 85 85 170 170 170 85 85 85 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170
+255 255 255 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 170 170 170 255 255 255 255 255 255 255 255 255 170 170 170
+0 0 0 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+170 170 170 170 170 170 255 255 255 170 170 170 255 255 255 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 170 170 170 255 255 255
+170 170 170 170 170 170 0 0 0 0 0 0 0 0 0 85 85 85
+170 170 170 255 255 255 255 255 255 0 0 0 0 0 0 85 85 85
+255 255 255 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 85 85 85
+85 85 85 0 0 0 85 85 85 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 255 255 255
+255 255 255 255 255 255 170 170 170 0 0 0 0 0 0 0 0 0
+85 85 85 170 170 170 255 255 255 170 170 170 170 170 170 170 170 170
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 85 85 85
+85 85 85 170 170 170 255 255 255 170 170 170 170 170 170 85 85 85
+85 85 85 0 0 0 85 85 85 85 85 85 85 85 85 170 170 170
+170 170 170 85 85 85 85 85 85 0 0 0 0 0 0 85 85 85
+170 170 170 170 170 170 85 85 85 0 0 0 0 0 0 170 170 170
+170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 170 170 170
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 170 170 170
+255 255 255 170 170 170 170 170 170 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 170 170 170 170 170 170 255 255 85 85 85 85
+85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 85 85 85 0 0 0 85 85 85
+85 85 85 170 170 170 170 170 170 170 170 170 170 85 0 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 170 170 170 170 85 0
+170 170 170 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+170 85 0 170 170 170 85 85 85 0 0 0 85 85 85 85 85 85
+170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 255 255 255
+170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+255 255 255 170 170 170 170 170 170 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 170 85 0 170 170 170 170 170 170 85 85 85
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 85 85 85
+85 85 85 170 85 0 85 255 85 170 85 0 170 170 170 85 85 85
+85 85 85 0 0 0 0 0 0 85 85 85 170 85 0 85 255 85
+170 85 0 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+85 85 85 85 85 85 170 85 0 0 0 0 85 85 85 85 85 85
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 255 255 255
+255 255 255 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0
+170 170 170 170 170 170 170 170 170 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 170 170 170 170 85 0 170 170 170 170 85 0
+85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 85 85 85 85 85 85 0 0 0
+85 85 85 85 85 85 255 85 85 170 170 170 85 255 85 170 85 0
+85 85 85 85 85 85 170 85 0 85 85 85 170 170 170 85 85 85
+170 170 170 170 85 0 85 85 85 85 85 85 85 85 85 85 85 85
+170 85 0 85 255 85 85 85 85 85 85 85 85 85 85 170 85 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 170 170 170
+255 255 255 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 170 85 0 170 170 170 170 85 0 85 85 85 0 0 0
+85 85 85 85 85 85 85 255 85 170 170 170 170 170 170 170 85 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+0 0 0 85 85 85 85 85 85 0 0 0 85 85 85 85 85 85
+85 85 85 85 85 85 85 255 85 255 85 85 170 170 170 170 170 170
+170 170 170 85 255 85 170 170 170 170 85 0 170 170 170 170 85 0
+170 170 170 85 85 85 85 255 85 170 85 0 170 170 170 170 85 0
+170 170 170 170 170 170 170 85 0 85 85 85 85 85 85 85 255 85
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 170 170 170 170 170 170 0 0 0 0 0 0 85 85 85
+170 170 170 170 170 170 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 255 255 85 85 85 85 85 85 85 85 85 85
+85 255 85 255 85 85 170 170 170 170 85 0 170 170 170 85 255 85
+85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 85 85 85 85 85 85 0 0 0
+85 85 85 85 85 85 170 85 0 170 170 170 170 170 170 255 255 85
+170 170 170 255 85 85 170 170 170 170 170 170 255 255 85 170 170 170
+85 255 85 170 170 170 255 85 85 170 170 170 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 170 85 0 170 170 170 170 85 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 170 170 170 85 85 85 0 0 0 85 85 85
+85 85 85 170 85 0 85 85 85 0 0 0 85 85 85 85 85 85
+85 85 85 170 85 0 170 170 170 170 170 170 255 255 85 170 170 170
+170 170 170 170 170 170 255 255 85 170 170 170 170 170 170 255 85 85
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 85 85 85 0 0 0 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 170 170 170 255 255 85 170 170 170 170 170 170
+170 170 170 255 255 85 170 170 170 170 170 170 170 170 170 170 85 0
+170 170 170 255 255 85 170 170 170 255 255 85 170 170 170 255 255 85
+170 170 170 255 255 85 170 170 170 170 170 170 85 255 85 170 85 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 170 170 170 85 85 85 85 85 85 0 0 0
+85 85 85 85 85 85 170 170 170 85 85 85 170 170 170 170 85 0
+170 170 170 85 255 85 170 170 170 170 85 0 170 170 170 170 170 170
+255 255 85 170 170 170 170 170 170 255 255 255 255 255 85 170 170 170
+255 255 85 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 170 85 0 170 170 170 170 170 170 170 170 170 255 255 255
+170 170 170 255 255 255 255 255 85 170 170 170 255 255 85 170 170 170
+255 255 85 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 255 85 85 170 170 170 170 170 170
+85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 85 85 85 170 85 0 85 85 85
+85 85 85 255 255 85 170 170 170 170 170 170 170 170 170 170 170 170
+255 255 85 170 170 170 170 170 170 255 255 85 170 170 170 170 170 170
+170 170 170 255 255 255 255 255 255 170 170 170 255 255 255 170 170 170
+170 170 170 85 85 85 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 170 170 170 170 170 170 85 85 85 0 0 0 0 0 0
+0 0 0 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 85 255 85 170 170 170 255 255 85 255 255 255 255 255 255
+255 255 255 170 170 170 255 255 255 170 170 170 170 170 170 170 170 170
+170 170 170 170 170 170 255 255 85 170 170 170 255 255 85 255 255 255
+255 255 85 255 255 255 255 255 85 170 170 170 170 170 170 170 85 0
+170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85
+85 85 85 170 170 170 255 255 85 170 170 170 255 255 85 170 170 170
+170 170 170 255 255 85 170 170 170 170 170 170 170 170 170 255 255 85
+255 255 255 255 255 255 255 255 85 255 255 255 255 255 255 170 170 170
+255 255 85 85 85 85 85 85 85 0 0 0 0 0 0 85 85 85
+85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+85 85 85 170 170 170 170 170 170 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 170 170 170 170 170 170 170 170 170 255 255 255 170 170 170
+255 255 255 255 255 255 255 255 255 170 170 170 170 170 170 255 255 85
+170 170 170 255 255 85 170 170 170 255 255 255 170 170 170 255 255 255
+255 255 255 255 255 255 170 170 170 255 255 85 170 170 170 255 255 85
+85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 170 85 0 170 170 170
+255 255 85 170 170 170 170 170 170 255 255 255 255 255 255 255 255 255
+170 170 170 170 170 170 170 170 170 255 255 85 170 170 170 170 170 170
+255 255 255 170 170 170 255 255 255 255 255 255 170 170 170 255 255 255
+170 170 170 170 170 170 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 85 85 85 85 85 85 0 0 0
+85 85 85 170 85 0 255 255 255 170 170 170 255 255 255 255 255 255
+255 255 85 255 255 255 170 170 170 255 255 85 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 255 255 85 255 255 255 255 255 255
+170 170 170 255 255 255 255 255 255 170 170 170 170 170 170 170 170 170
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 255 85 170 170 170
+170 170 170 255 255 85 170 170 170 255 255 255 170 170 170 255 255 255
+255 255 255 255 255 255 255 255 85 170 170 170 170 170 170 255 255 255
+170 170 170 255 255 255 255 255 255 170 170 170 255 255 255 255 255 85
+170 170 170 170 85 0 85 85 85 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 170 170 170 170 170 170 255 255 85 170 170 170 255 255 255
+255 255 255 170 170 170 255 255 255 170 170 170 170 170 170 255 255 85
+170 170 170 255 255 85 170 170 170 255 255 255 170 170 170 255 255 255
+255 255 255 255 255 255 255 255 255 255 255 255 170 170 170 255 255 85
+85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 170 85 0 170 170 170
+170 170 170 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
+170 170 170 170 170 170 170 170 170 170 170 170 255 255 85 170 170 170
+255 255 85 255 255 255 170 170 170 255 255 255 170 170 170 170 170 170
+170 170 170 170 170 170 85 85 85 0 0 0 85 85 85 85 85 85
+0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+85 85 85 85 85 85 170 170 170 170 170 170 255 255 255 170 170 170
+255 255 255 170 170 170 255 255 85 170 170 170 170 170 170 170 170 170
+255 85 85 170 170 170 170 170 170 170 170 170 255 255 255 255 255 255
+170 170 170 255 255 255 255 255 255 170 170 170 255 255 255 170 170 170
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 170 170 170
+255 255 85 170 170 170 255 255 255 170 170 170 255 255 255 255 255 255
+255 255 85 255 255 255 170 170 170 255 255 85 170 170 170 170 170 170
+170 170 170 170 170 170 255 255 85 170 170 170 170 170 170 255 255 85
+170 170 170 170 85 0 85 85 85 0 0 0 85 85 85 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 170 170 170
+170 170 170 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 170 170 170 255 255 85 170 170 170 170 170 170
+255 255 85 170 170 170 170 170 170 170 170 170 170 170 170 255 85 85
+85 255 85 170 170 170 170 170 170 170 170 170 255 255 85 170 170 170
+255 255 255 255 255 255 255 255 255 255 255 85 170 170 170 170 170 170
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 255 255 85
+170 170 170 170 170 170 255 255 255 255 255 255 255 255 255 170 170 170
+255 255 255 170 170 170 170 170 170 170 170 170 170 170 170 255 85 85
+170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170
+170 170 170 85 85 85 85 85 85 0 0 0 85 85 85 0 0 0
+85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 170 170 170 170 170 170 170 170 170
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 170 85 0 170 170 170 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 170 85 0 170 170 170 85 255 85
+255 85 85 170 170 170 255 255 85 170 170 170 170 170 170 255 255 255
+255 255 255 170 170 170 255 255 255 255 255 255 170 170 170 170 170 170
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170
+170 170 170 255 255 85 170 170 170 255 255 85 255 255 255 255 255 255
+170 170 170 170 170 170 255 255 85 170 170 170 255 85 85 85 255 85
+170 170 170 170 85 0 170 170 170 170 170 170 255 255 85 170 170 170
+170 85 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 85 85 85 85 85 85 85 85 85 170 170 170 255 255 85
+170 170 170 170 85 0 170 170 170 170 170 170 170 85 0 85 85 85
+170 170 170 170 85 0 85 85 85 170 170 170 170 170 170 170 170 170
+170 170 170 255 255 255 255 255 255 255 255 85 170 170 170 170 170 170
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 85 0
+170 170 170 170 170 170 255 255 255 170 170 170 255 255 255 170 170 170
+255 255 255 170 170 170 170 170 170 170 85 0 170 170 170 85 85 85
+170 170 170 170 170 170 170 85 0 170 170 170 170 85 0 85 85 85
+85 255 85 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85
+85 85 85 0 0 0 85 85 85 170 85 0 85 85 85 170 170 170
+170 85 0 170 170 170 85 255 85 170 85 0 170 170 170 85 85 85
+170 85 0 170 170 170 170 170 170 255 255 85 170 170 170 255 255 255
+255 255 85 255 255 255 170 170 170 170 170 170 170 170 170 170 85 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 255 255 85
+170 170 170 255 255 85 170 170 170 170 170 170 85 255 85 170 170 170
+170 85 0 170 85 0 170 170 170 85 255 85 85 85 85 170 170 170
+170 85 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 85 85 85
+0 0 0 0 0 0 0 0 0 85 85 85 170 85 0 85 85 85
+170 170 170 170 85 0 170 170 170 85 85 85 170 170 170 170 85 0
+170 170 170 85 255 85 170 85 0 170 170 170 170 170 170 170 170 170
+255 255 255 170 170 170 255 255 255 255 255 255 170 170 170 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+170 85 0 170 170 170 255 255 85 170 170 170 255 255 255 170 170 170
+170 170 170 170 170 170 170 170 170 170 85 0 170 170 170 170 85 0
+170 170 170 85 255 85 170 85 0 170 170 170 170 85 0 85 85 85
+85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85
+85 255 85 170 170 170 170 85 0 170 170 170 170 85 0 85 255 85
+170 170 170 170 85 0 170 170 170 170 170 170 170 170 170 255 255 85
+170 170 170 255 255 255 170 170 170 170 170 170 170 170 170 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 170 85 0 85 85 85 170 170 170 255 255 85 170 170 170
+170 170 170 255 255 85 170 170 170 170 170 170 170 170 170 170 85 0
+170 170 170 85 85 85 170 170 170 170 85 0 170 170 170 85 85 85
+170 85 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 170 85 0
+85 85 85 255 85 85 85 255 85 170 85 0 170 170 170 170 170 170
+170 85 0 170 170 170 85 85 85 255 255 85 170 170 170 170 170 170
+255 255 255 170 170 170 255 255 255 255 255 85 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 170 170 170 170 85 0 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 255 255 85 85 85 85 170 170 170
+85 255 85 255 85 85 170 170 170 85 255 85 255 85 85 85 255 85
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 85 85 85 0 0 0 85 85 85
+85 85 85 85 255 85 255 85 85 170 170 170 85 255 85 170 85 0
+170 170 170 170 170 170 255 255 85 170 170 170 170 170 170 255 255 255
+170 170 170 255 255 255 170 170 170 170 170 170 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 170 170 170 85 85 85 255 255 85
+170 170 170 255 255 85 170 170 170 170 170 170 170 170 170 255 255 85
+85 85 85 255 255 85 170 170 170 170 85 0 170 170 170 85 85 85
+170 85 0 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+170 170 170 170 85 0 170 170 170 170 85 0 170 170 170 170 170 170
+170 85 0 170 170 170 170 170 170 170 170 170 255 255 85 170 170 170
+255 255 85 255 255 255 170 170 170 170 170 170 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 170 85 0 85 85 85 170 170 170
+170 85 0 170 170 170 170 170 170 255 255 85 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 255 255 85 170 170 170 170 85 0
+85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+170 85 0 85 255 85 170 170 170 170 170 170 255 255 85 170 170 170
+255 255 85 170 170 170 170 170 170 170 170 170 255 255 255 255 255 255
+255 255 255 170 170 170 255 255 85 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 170 85 0
+170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 255 255 85
+170 170 170 255 255 85 170 170 170 170 170 170 170 170 170 170 170 170
+170 170 170 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+85 85 85 170 85 0 170 170 170 170 85 0 170 170 170 170 170 170
+170 170 170 255 255 85 170 170 170 255 255 85 170 170 170 255 255 255
+170 170 170 255 255 255 170 170 170 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85
+170 85 0 170 170 170 170 85 0 255 255 85 170 170 170 170 170 170
+170 170 170 170 170 170 255 255 85 170 170 170 255 255 85 170 170 170
+255 255 85 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+85 85 85 170 170 170 255 255 85 170 170 170 255 255 85 170 170 170
+170 170 170 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255
+170 170 170 170 170 170 170 170 170 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 170 0 85 85 85
+170 85 0 85 255 85 170 170 170 170 170 170 170 170 170 255 255 85
+255 255 255 170 170 170 255 255 255 170 170 170 255 255 255 170 170 170
+170 170 170 255 255 85 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+170 85 0 170 170 170 170 170 170 170 170 170 170 170 170 255 255 85
+170 170 170 255 255 255 170 170 170 255 255 255 170 170 170 255 255 255
+255 255 255 255 255 85 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+85 85 85 170 85 0 170 170 170 170 170 170 255 255 85 170 170 170
+170 170 170 255 255 255 255 255 255 255 255 255 170 170 170 255 255 255
+170 170 170 170 170 170 170 170 170 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 255 85
+170 170 170 255 255 85 170 170 170 255 255 85 255 255 255 255 255 255
+255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 170 170 170
+170 170 170 170 170 170 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 85 85 85 170 85 0 170 170 170 170 170 170
+255 255 85 170 170 170 255 255 255 255 255 85 255 255 255 255 255 255
+170 170 170 255 255 85 170 170 170 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 85 0
+170 170 170 170 170 170 170 170 170 255 255 255 170 170 170 255 255 255
+170 170 170 255 255 255 170 170 170 255 255 255 255 255 85 255 255 255
+170 170 170 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 170 85 0 85 85 85 170 170 170 170 170 170 170 170 170
+170 170 170 255 255 255 170 170 170 255 255 255 255 255 255 170 170 170
+255 255 85 170 170 170 170 170 170 170 85 0 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170
+255 255 85 170 170 170 255 255 85 170 170 170 255 255 255 255 255 255
+255 255 255 255 255 255 255 255 255 255 255 255 170 170 170 170 170 170
+170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 85 85 85 85 85 85 170 85 0 170 170 170
+255 255 85 170 170 170 255 255 85 255 255 255 170 170 170 255 255 255
+170 170 170 170 170 170 170 170 170 170 170 170 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170
+170 85 0 170 170 170 255 255 255 170 170 170 255 255 255 170 170 170
+255 255 255 255 255 255 170 170 170 255 255 255 255 255 85 170 170 170
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 85 85 85 170 85 0 85 85 85 170 170 170
+170 170 170 170 170 170 170 170 170 170 170 170 255 255 85 170 170 170
+255 255 85 170 170 170 170 85 0 85 255 85 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 85 0
+170 170 170 170 170 170 255 255 85 170 170 170 255 255 255 255 255 255
+255 255 85 255 255 255 170 170 170 255 255 255 170 170 170 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+170 85 0 170 170 170 170 170 170 255 255 85 170 170 170 170 170 170
+170 170 170 170 170 170 170 170 170 170 85 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+255 255 85 170 170 170 170 170 170 170 170 170 255 255 85 170 170 170
+255 255 255 170 170 170 255 255 85 170 170 170 85 85 85 85 85 85
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+85 85 85 170 85 0 170 170 170 170 170 170 170 170 170 170 170 170
+170 85 0 170 170 170 170 85 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85
+170 170 170 170 170 170 255 255 85 170 170 170 170 170 170 170 170 170
+170 170 170 255 255 255 170 170 170 170 170 170 85 85 85 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+85 85 85 85 85 85 85 85 85 170 85 0 85 85 85 170 85 0
+85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 170 85 0
+85 85 85 170 85 0 170 170 170 170 170 170 170 170 170 255 255 85
+170 170 170 170 170 170 170 85 0 85 85 85 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85
+85 85 85 85 255 85 170 85 0 170 170 170 170 85 0 170 170 170
+85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85
+85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0