diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2013-10-22 10:46:59 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-10-23 16:25:12 -0400 |
| commit | de926800b155886c61b06146e28c0ba2e6fafc39 (patch) | |
| tree | 23c09dcf7a8d4b988fc7a443988c5d1a5fc40dd0 /drivers | |
| parent | 579123fdfc23ad2147f041dfec305c2308f068ba (diff) | |
drm/radeon: use sw CTS/N values for audio on DCE4+
Use the driver calculated CTS and N values rather than
having hardware generate them. This allows us to use
the modeline pixel clock rather than the actual pll clock
when setting up the dto for audio. Fixes problems with
audio playback rate on certain asics if the pll clock
does not match the pixel clock exactly.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen_hdmi.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index fe1de855775..57fcc4b16a5 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c @@ -291,6 +291,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ WREG32(HDMI_ACR_PACKET_CONTROL + offset, + HDMI_ACR_SOURCE | /* select SW CTS value */ HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ evergreen_hdmi_update_ACR(encoder, mode->clock); |