diff options
| author | Scott Wood <scottwood@freescale.com> | 2009-11-13 14:12:16 -0600 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2009-11-30 09:53:32 +0000 |
| commit | b3a70f0bc32d1b70584bcaa6019fa4260b0da92e (patch) | |
| tree | 7940647011ed8d3270d037c6ac746219323e3807 /drivers | |
| parent | 54c69cc25064c1d333a12b5883aaa3bfa3041dee (diff) | |
mtd: eLBC NAND: increase bus timeout to maximum
When a NAND operation is in progress, all other localbus operations
(including NOR flash) will have to wait for access to the bus. However, the
NAND operation may take longer to complete than the default timeout. Thus,
if NOR is accessed while a NAND operation is in progress, the NAND operation
will fail.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/nand/fsl_elbc_nand.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index ddd37d2554e..58db2785512 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -946,6 +946,13 @@ static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl) { struct fsl_lbc_regs __iomem *lbc = ctrl->regs; + /* + * NAND transactions can tie up the bus for a long time, so set the + * bus timeout to max by clearing LBCR[BMT] (highest base counter + * value) and setting LBCR[BMTPS] to the highest prescaler value. + */ + clrsetbits_be32(&lbc->lbcr, LBCR_BMT, 15); + /* clear event registers */ setbits32(&lbc->ltesr, LTESR_NAND_MASK); out_be32(&lbc->lteatr, 0); |