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authorJesse Barnes <jbarnes@virtuousgeek.org>2009-09-17 17:06:47 -0700
committerJesse Barnes <jbarnes@virtuousgeek.org>2009-09-17 17:06:47 -0700
commitedb81956422c9926553bb97e3e56b849da0f4bb5 (patch)
treeb8592223d0c9523ec3ab164e22f1fdcb6653686a /drivers
parent7121413f2accf14cf05b38539fb7a8be77543370 (diff)
drm/i915: correct FBC update when pipe base update occurs
We usually don't have an SAREA, and we always want to update the FBC status anyway, so move the update up above the various master/sarea checks. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 44234150e84..cb0f4f96439 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1260,6 +1260,9 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
I915_READ(dspbase);
}
+ if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
+ intel_update_fbc(crtc, &crtc->mode);
+
intel_wait_for_vblank(dev);
if (old_fb) {
@@ -1286,9 +1289,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
master_priv->sarea_priv->pipeA_y = y;
}
- if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
- intel_update_fbc(crtc, &crtc->mode);
-
return 0;
}