diff options
| author | Mikko Tiihonen <mikko.tiihonen@iki.fi> | 2013-01-30 14:10:04 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-01-30 14:10:04 -0500 |
| commit | f689e3acbd2e48cc4101e0af454193f81af4baaf (patch) | |
| tree | 39cd14fa86616b7dca061d3211079f235386e02e /drivers | |
| parent | f7eb97300832f4fe5fe916c5d84cd2e25169330e (diff) | |
drm/radeon: protect against div by 0 in backend setup
Make sure at least one RB is enabled in
r6xx_remap_render_backend() to avoid an division by
zero in some corner cases.
See:
https://bugzilla.redhat.com/show_bug.cgi?id=892233
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index bc2540b17c5..becb03e8b32 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -1462,12 +1462,15 @@ u32 r6xx_remap_render_backend(struct radeon_device *rdev, u32 disabled_rb_mask) { u32 rendering_pipe_num, rb_num_width, req_rb_num; - u32 pipe_rb_ratio, pipe_rb_remain; + u32 pipe_rb_ratio, pipe_rb_remain, tmp; u32 data = 0, mask = 1 << (max_rb_num - 1); unsigned i, j; /* mask out the RBs that don't exist on that asic */ - disabled_rb_mask |= (0xff << max_rb_num) & 0xff; + tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); + /* make sure at least one RB is available */ + if ((tmp & 0xff) != 0xff) + disabled_rb_mask = tmp; rendering_pipe_num = 1 << tiling_pipe_num; req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); |