diff options
| author | Maciej Patelczyk <maciej.patelczyk@intel.com> | 2011-04-27 17:50:50 +0000 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2011-07-03 04:00:38 -0700 |
| commit | e76d80579c2b5b4ecac107b83c22ceeb9e23bd1b (patch) | |
| tree | bdd8f946c25d9aa087d07359e068c1ee0750e649 /drivers | |
| parent | d2d61433a85f814c7bc0b20993bb39e97f2dde76 (diff) | |
isci: Implement SCU AFE recipe 10.
Updated SCU AFE initialization values accordingly to the recipe 10.
Signed-off-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/scsi/isci/core/scic_sds_controller.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/scsi/isci/core/scic_sds_controller.c b/drivers/scsi/isci/core/scic_sds_controller.c index c684d9ec8c9..5e8dea57b5e 100644 --- a/drivers/scsi/isci/core/scic_sds_controller.c +++ b/drivers/scsi/isci/core/scic_sds_controller.c @@ -442,11 +442,20 @@ static void scic_sds_controller_afe_initialization(struct scic_sds_controller *s writel(0x0081000f, &scic->scu_registers->afe.afe_dfx_master_control0); udelay(AFE_REGISTER_WRITE_DELAY); + if (is_b0()) { + /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement + * Timer, PM Stagger Timer */ + writel(0x0007BFFF, &scic->scu_registers->afe.afe_pmsn_master_control2); + udelay(AFE_REGISTER_WRITE_DELAY); + } + /* Configure bias currents to normal */ if (is_a0()) writel(0x00005500, &scic->scu_registers->afe.afe_bias_control); - else + else if (is_a2()) writel(0x00005A00, &scic->scu_registers->afe.afe_bias_control); + else if (is_b0()) + writel(0x00005F00, &scic->scu_registers->afe.afe_bias_control); udelay(AFE_REGISTER_WRITE_DELAY); @@ -464,7 +473,7 @@ static void scic_sds_controller_afe_initialization(struct scic_sds_controller *s udelay(AFE_REGISTER_WRITE_DELAY); } while ((afe_status & 0x00001000) == 0); - if (is_b0()) { + if (is_a0() || is_a2()) { /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */ writel(0x7bcc96ad, &scic->scu_registers->afe.afe_pmsn_master_control0); udelay(AFE_REGISTER_WRITE_DELAY); |