diff options
| author | Kevin Liu <kliu5@marvell.com> | 2012-10-17 19:04:45 +0800 |
|---|---|---|
| committer | Chris Ball <cjb@laptop.org> | 2012-12-06 13:54:45 -0500 |
| commit | 35d110e71a6f1d1d336a18be50bde755abebe3fb (patch) | |
| tree | a5ec95b2bc63a80fb05332d83be766d810e88391 /drivers | |
| parent | 5f1a4dd0372038f2490afa4540cd66b8d092839e (diff) | |
mmc: sdhci-pxav3: Add base clock quirk
Enable the quirk SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN since
SD_CAPABILITIES_1[15:8](BASE_FREQ) can't get correct base clock value.
It returns a fixed pre-set value like 200 on some sdhci-pxav3 based
platforms like MMP3 while return 0 on the other sdhci-pxav3 based
platforms. So we enable the quirk and get the base clock via function
get_max_clock. Also add get_max_clock.
Reported-by: Philip Rakity <prakity@marvell.com>
Reviewed-by: Philip Rakity <prakity@Marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Kevin Liu <kliu5@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/host/sdhci-pxav3.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index e918a2bb3af..ccd190619e6 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -163,10 +163,18 @@ static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) return 0; } +static u32 pxav3_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + + return clk_get_rate(pltfm_host->clk); +} + static struct sdhci_ops pxav3_sdhci_ops = { .platform_reset_exit = pxav3_set_private_registers, .set_uhs_signaling = pxav3_set_uhs_signaling, .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, + .get_max_clock = pxav3_get_max_clock, }; #ifdef CONFIG_OF @@ -249,7 +257,8 @@ static int __devinit sdhci_pxav3_probe(struct platform_device *pdev) host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC - | SDHCI_QUIRK_32BIT_ADMA_SIZE; + | SDHCI_QUIRK_32BIT_ADMA_SIZE + | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; /* enable 1/8V DDR capable */ host->mmc->caps |= MMC_CAP_1_8V_DDR; |