diff options
| author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2006-05-16 20:16:41 +0400 |
|---|---|---|
| committer | David Woodhouse <dwmw2@infradead.org> | 2006-05-16 17:25:19 +0100 |
| commit | 155285c4775b7027b01a5b744c721ae43cced798 (patch) | |
| tree | 4bbfba4b281c3368c2544eafa1e93b63b517c509 /drivers | |
| parent | c41ff6e5f38b02ff927d0d510e28dc1392bb4690 (diff) | |
NAND: AMD Au1550 driver reads write-only register
During the last cleanup of the AMD Au1550 NAND driver the old buglet was
reintroduced: as the MEM_STNDCTL register is write-only and seem to always
read as 0x31, read-modify-write to it done in au1xxx_nand_init() will have the
side effect of enabling -RCS0/1 pin override (via bits 4/5 of this reg.), thus
possibly causing a contention on the static bus when the NOR flash (using
-RCS0) or board control status registers (using -RCS2) are read. Luckily, this
goes away with a first NAND access, since au1550_hwcontrol() doesn't try to
read this register before writing anymore.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/nand/au1550nd.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 861fb961d94..839b35a386b 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -347,11 +347,9 @@ static int __init au1xxx_nand_init(void) au1550_mtd->priv = this; au1550_mtd->owner = THIS_MODULE; - /* disable interrupts */ - au_writel(au_readl(MEM_STNDCTL) & ~(1 << 8), MEM_STNDCTL); - /* disable NAND boot */ - au_writel(au_readl(MEM_STNDCTL) & ~(1 << 0), MEM_STNDCTL); + /* MEM_STNDCTL: disable ints, disable nand boot */ + au_writel(0, MEM_STNDCTL); #ifdef CONFIG_MIPS_PB1550 /* set gpio206 high */ |