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authorDamien Lespiau <damien.lespiau@intel.com>2012-10-31 19:23:16 +0000
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-11-21 17:45:01 +0100
commit42d42e7e4220753bab3eb7b857721f203a4cd821 (patch)
treea7cf287a5c9067ee93204e8b86d024bb721771f6 /drivers
parent607a6f7a6621f65706ff536b2615ee65b5c2f575 (diff)
drm/i915: Only check for valid PP_{ON, OFF}_DELAYS on pre ILK hardware
ILK+ have this register on the PCH. This check was triggering unclaimed writes. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 0ed6baff4b0..87e9b92039d 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -762,7 +762,8 @@ void intel_setup_bios(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
/* Set the Panel Power On/Off timings if uninitialized. */
- if ((I915_READ(PP_ON_DELAYS) == 0) && (I915_READ(PP_OFF_DELAYS) == 0)) {
+ if (!HAS_PCH_SPLIT(dev) &&
+ I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) {
/* Set T2 to 40ms and T5 to 200ms */
I915_WRITE(PP_ON_DELAYS, 0x019007d0);