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authorMarek Szyprowski <m.szyprowski@samsung.com>2010-07-19 16:01:41 +0200
committerGreg Kroah-Hartman <gregkh@suse.de>2010-08-10 14:35:43 -0700
commit1eb838d3e2a473acbb9b21278e75b79640fb2c7b (patch)
treec702eb55341116e5c48518bbabc373cc82e92a71 /drivers
parent4d47166c975382f5e95086e8a88d4a39d27b34b5 (diff)
USB: s3c-hsotg: modify only selected bits in S3C_PHYPWR register
S5PV210 SoCs has 2 USB PHY interfaces, both enabled by writing zero to S3C_PHYPWR register. HS/OTG driver uses only PHY0, so do not touch bits related to PHY1. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/usb/gadget/s3c-hsotg.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index ce272b4d79c..258ca01ac67 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -2801,9 +2801,11 @@ static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
{
struct clk *xusbxti;
- u32 osc;
+ u32 pwr, osc;
- writel(0, S3C_PHYPWR);
+ pwr = readl(S3C_PHYPWR);
+ pwr &= ~0x19;
+ writel(pwr, S3C_PHYPWR);
mdelay(1);
osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;