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authorOlof Johansson <olof@lixom.net>2014-07-12 21:19:21 -0700
committerOlof Johansson <olof@lixom.net>2014-07-12 21:19:21 -0700
commitcacadb4ff969a82628d47db87b5a531be466b134 (patch)
treeb006cfae86bd141db07ba212b6d6d4b81f3e51a9 /drivers
parent363d4ddc17320ad0906778924d40ba5955ccf194 (diff)
parentbed7118988ef48063c72f67cc2701c72663b3870 (diff)
Merge tag 'samsung-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
Merge "Samsung fixes-3 for 3.16" from Kukjin Kim: Samsung fixes-3 for v3.16 - update the parent for Auudss clock because kernel will be hang during late boot if the parent clock is disabled in bootloader. - enable clk handing in power domain because while power domain on/off, its regarding clock source will be reset and it causes a problem so need to handle it. - add mux clocks to be used by power domain for exynos5420-mfc during power domain on/off and property in device tree also. - register cpuidle only for exynos4210 and exynos5250 because a system failure will be happened on other exynos SoCs. * tag 'samsung-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Register cpuidle device only on exynos4210 and 5250 ARM: dts: Add clock property for mfc_pd in exynos5420 clk: exynos5420: Add IDs for clocks used in PD mfc ARM: EXYNOS: Add support for clock handling in power domain ARM: dts: Update the parent for Audss clocks in Exynos5420 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 9d7d7eed03f..f74f882f7f2 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -631,7 +631,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
SRC_TOP4, 16, 1),
MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
- MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1),
+ MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
+ SRC_TOP4, 28, 1),
MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
SRC_TOP5, 0, 1),
@@ -684,7 +685,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
SRC_TOP11, 12, 1),
MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
- MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1),
+ MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
+ SRC_TOP11, 28, 1),
MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
SRC_TOP12, 4, 1),