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authorJosh Boyer <jwboyer@linux.vnet.ibm.com>2008-05-16 00:43:46 +1000
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2008-05-19 09:36:40 -0500
commit13c501e69c3fba3ca0651abcc4aa7c9091fda70a (patch)
tree2bfc238f089495e6d64d15e772ea354054f3a1d3 /fs/compat.c
parentb8291ad07a7f3b5b990900f0001198ac23ba893e (diff)
[POWERPC] 4xx: Workaround for CHIP_11 Errata
The PowerPC 440EP, 440GR, 440EPx, and 440GRx chips have an issue that causes the PLB3-to-PLB4 bridge to wait indefinitely for transaction requests that cross the end-of-memory-range boundary. Since the DDR controller only returns the valid portion of a read request, the bridge will prevent other PLB masters from completing their transactions. This implements the recommended workaround for this errata for chips that use older versions of firmware that do not already handle it. The last 4KiB of memory are hidden from the kernel to prevent the problem transactions from occurring. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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