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authorZhang Wei <wei.zhang@freescale.com>2008-03-18 18:45:00 -0700
committerDan Williams <dan.j.williams@intel.com>2008-03-18 17:00:59 -0700
commitf79abb627f033c85a6088231f20c85bc4a9bd757 (patch)
tree151538a3a33026ae516606240a13404d1f1e7037 /fs/ufs
parentf920bb6f5fe21047e669381fe4dd346f6a9d3562 (diff)
fsldma: Fix the DMA halt when using DMA_INTERRUPT async_tx transfer.
The DMA_INTERRUPT async_tx is a NULL transfer, thus the BCR(count register) is 0. When the transfer started with a byte count of zero, the DMA controller will triger a PE(programming error) event and halt, not a normal interrupt. I add special codes for PE event and DMA_INTERRUPT async_tx testing. Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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