diff options
| author | Jeff Garzik <jgarzik@pobox.com> | 2006-01-17 10:29:06 -0500 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@pobox.com> | 2006-01-17 10:29:06 -0500 |
| commit | ea9b395fe20ac74be788f415af2622ac8f0c35c7 (patch) | |
| tree | d1653e1a4cbe360aa7132ea4e29ab92a02038224 /include/asm-arm/arch-ixp2000/ixp2000-regs.h | |
| parent | 61420e147a706ee7c7a902008045547fb2a2a330 (diff) | |
| parent | 1bc4ccfff8675adc3d96f91245eb7e2dc0043ca9 (diff) | |
Merge branch 'upstream'
Diffstat (limited to 'include/asm-arm/arch-ixp2000/ixp2000-regs.h')
| -rw-r--r-- | include/asm-arm/arch-ixp2000/ixp2000-regs.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h index fc5ac6aec4f..2b57f91b4eb 100644 --- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h +++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h @@ -26,6 +26,8 @@ * fc000000 da000000 16M PCI CFG0 * fd000000 d8000000 16M PCI I/O * fe[0-7]00000 8M per-platform mappings + * fe900000 80000000 1M SRAM #0 (first MB) + * fea00000 cb400000 1M SCRATCH ring get/put * feb00000 c8000000 1M MSF * fec00000 df000000 1M PCI CSRs * fed00000 de000000 1M PCI CREG @@ -91,6 +93,14 @@ #define IXP2000_MSF_VIRT_BASE 0xfeb00000 #define IXP2000_MSF_SIZE 0x00100000 +#define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000 +#define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000 +#define IXP2000_SCRATCH_RING_SIZE 0x00100000 + +#define IXP2000_SRAM0_PHYS_BASE 0x80000000 +#define IXP2000_SRAM0_VIRT_BASE 0xfe900000 +#define IXP2000_SRAM0_SIZE 0x00100000 + #define IXP2000_PCI_IO_PHYS_BASE 0xd8000000 #define IXP2000_PCI_IO_VIRT_BASE 0xfd000000 #define IXP2000_PCI_IO_SIZE 0x01000000 @@ -156,6 +166,14 @@ #define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84) #define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88) #define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c) +#define IXP2000_IRQ_THD_STATUS_A_0 IXP2000_INTCTL_REG(0xe0) +#define IXP2000_IRQ_THD_STATUS_A_1 IXP2000_INTCTL_REG(0xe4) +#define IXP2000_IRQ_THD_STATUS_A_2 IXP2000_INTCTL_REG(0xe8) +#define IXP2000_IRQ_THD_STATUS_A_3 IXP2000_INTCTL_REG(0xec) +#define IXP2000_IRQ_THD_STATUS_B_0 IXP2000_INTCTL_REG(0x100) +#define IXP2000_IRQ_THD_STATUS_B_1 IXP2000_INTCTL_REG(0x104) +#define IXP2000_IRQ_THD_STATUS_B_2 IXP2000_INTCTL_REG(0x108) +#define IXP2000_IRQ_THD_STATUS_B_3 IXP2000_INTCTL_REG(0x10c) #define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160) #define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164) #define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168) |