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authorSteven Whitehouse <swhiteho@redhat.com>2006-04-03 09:08:57 -0400
committerSteven Whitehouse <swhiteho@redhat.com>2006-04-03 09:08:57 -0400
commit76467874b83835129dc454e3a7a8e5d1186101b0 (patch)
tree162129f0c36c35be4aa323cf00626db0e804c3fc /include/asm-arm/arch-ixp23xx/memory.h
parent8628de0583504138551a05ad44ca388467f0f552 (diff)
parent6246b6128bbe34d0752f119cf7c5111c85fe481d (diff)
Merge branch 'master'
Diffstat (limited to 'include/asm-arm/arch-ixp23xx/memory.h')
-rw-r--r--include/asm-arm/arch-ixp23xx/memory.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h
index bebcf0aa0d7..6e19f46d54d 100644
--- a/include/asm-arm/arch-ixp23xx/memory.h
+++ b/include/asm-arm/arch-ixp23xx/memory.h
@@ -28,6 +28,7 @@
* to an address that the kernel can use.
*/
#ifndef __ASSEMBLY__
+#include <asm/mach-types.h>
#define __virt_to_bus(v) \
({ unsigned int ret; \
@@ -40,6 +41,22 @@
data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \
__phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); })
+/*
+ * Coherency support. Only supported on A2 CPUs or on A1
+ * systems that have the cache coherency workaround.
+ */
+static inline int __ixp23xx_arch_is_coherent(void)
+{
+ extern unsigned int processor_id;
+
+ if (((processor_id & 15) >= 2) || machine_is_roadrunner())
+ return 1;
+
+ return 0;
+}
+
+#define arch_is_coherent() __ixp23xx_arch_is_coherent()
+
#endif