diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2007-02-14 19:14:56 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-02-15 14:44:10 +0000 |
| commit | b3a1bde4db9889feb116330bff21214811c940e4 (patch) | |
| tree | 6b8174332407ac8f4d2c5f6445912b935ff06110 /include/asm-arm/hardware/gic.h | |
| parent | ae0a846e411dc0b568e8ccda584896310ee5f369 (diff) | |
[ARM] 4108/2: Allow multiple GIC interrupt controllers in a system
The current implementation only assumes one GIC to be present in the
system. However, there are platforms with more than one cascaded interrupt
controllers (RealView/EB MPCore for example).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/hardware/gic.h')
| -rw-r--r-- | include/asm-arm/hardware/gic.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/asm-arm/hardware/gic.h b/include/asm-arm/hardware/gic.h index 3fa5eb70f64..966e428ad32 100644 --- a/include/asm-arm/hardware/gic.h +++ b/include/asm-arm/hardware/gic.h @@ -33,8 +33,9 @@ #define GIC_DIST_SOFTINT 0xf00 #ifndef __ASSEMBLY__ -void gic_dist_init(void __iomem *base); -void gic_cpu_init(void __iomem *base); +void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start); +void gic_cpu_init(unsigned int gic_nr, void __iomem *base); +void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); void gic_raise_softirq(cpumask_t cpumask, unsigned int irq); #endif |