diff options
| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-04-02 13:34:00 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-04-02 13:34:00 -0700 |
| commit | 1810b6cb162e0c19e0ecbbacbcfd66f578f335ec (patch) | |
| tree | 810494ca945483bf669a062d445d49d3bfb7d6a7 /include/asm-arm | |
| parent | ef7a4567dc542d8cc563755478464ea928fede41 (diff) | |
| parent | 9b6553cd01ce3ea7a6a532f7b7e62e3535d6b102 (diff) | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (27 commits)
[ARM] 3433/1: ARM: OMAP: 8/8 Update board files
[ARM] 3455/1: ARM: OMAP: 7/8 Misc updates, take 2
[ARM] 3454/1: ARM: OMAP: 6/8 Update framebuffer low-level init code, take 2
[ARM] 3430/1: ARM: OMAP: 5/8 Update PM
[ARM] 3429/1: ARM: OMAP: 4/8 Update GPIO
[ARM] 3428/1: ARM: OMAP: 3/8 Update pin multiplexing
[ARM] 3427/1: ARM: OMAP: 2/8 Update timers
[ARM] 3426/1: ARM: OMAP: 1/8 Update clock framework
[ARM] 3396/2: AT91RM9200 Platform devices update
[ARM] 3395/2: AT91RM9200 Dataflash Card vs MMC selection
[ARM] 3393/2: AT91RM9200 LED support
[ARM] 3453/1: Poodle: Correctly set the memory size
[ARM] 3446/1: i.MX: MMC/SD SDHC controller registration for i.MX/MX1 MX1ADS board
[ARM] 3444/1: i.MX: Scatter-gather DMA emulation for i.MX/MX1
[ARM] 3451/1: ep93xx: use the m48t86 rtc driver on the ts72xx platform
[ARM] 3450/1: ep93xx: use the ep93xx rtc driver
[ARM] 3452/1: [S3C2410] RX3715 - add nand information
[ARM] 3449/1: [S3C2410] Anubis - fix NAND timings
[ARM] 3448/1: [S3C2410] Settle delay when _enabling_ USB PLL
[ARM] 3442/1: [S3C2410] SMDK: NAND device setup
...
Diffstat (limited to 'include/asm-arm')
43 files changed, 994 insertions, 630 deletions
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h index 2e7d1139a79..4fdef13d01d 100644 --- a/include/asm-arm/arch-at91rm9200/board.h +++ b/include/asm-arm/arch-at91rm9200/board.h @@ -38,6 +38,8 @@ extern unsigned long at91_master_clock; extern int at91_serial_map[AT91_NR_UART]; extern int at91_console_port; +#include <linux/mtd/partitions.h> + /* USB Device */ struct at91_udc_data { u8 vbus_pin; /* high == host powering us */ @@ -77,4 +79,26 @@ struct at91_usbh_data { }; extern void __init at91_add_device_usbh(struct at91_usbh_data *data); + /* NAND / SmartMedia */ +struct at91_nand_data { + u8 enable_pin; /* chip enable */ + u8 det_pin; /* card detect */ + u8 rdy_pin; /* ready/busy */ + u8 ale; /* address line number connected to ALE */ + u8 cle; /* address line number connected to CLE */ + struct mtd_partition* (*partition_info)(int, int*); +}; +extern void __init at91_add_device_nand(struct at91_nand_data *data); + + /* I2C*/ +void __init at91_add_device_i2c(void); + + /* RTC */ +void __init at91_add_device_rtc(void); + + /* LEDs */ +extern u8 at91_leds_cpu; +extern u8 at91_leds_timer; +extern void __init at91_init_leds(u8 cpu_led, u8 timer_led); + #endif diff --git a/include/asm-arm/arch-ep93xx/ts72xx.h b/include/asm-arm/arch-ep93xx/ts72xx.h index 412215e77f4..a94f63ff053 100644 --- a/include/asm-arm/arch-ep93xx/ts72xx.h +++ b/include/asm-arm/arch-ep93xx/ts72xx.h @@ -12,6 +12,8 @@ * febfc000 [67]0000000 4K NAND data register * febfb000 [67]0400000 4K NAND control register * febfa000 [67]0800000 4K NAND busy register + * febf9000 10800000 4K TS-5620 RTC index register + * febf8000 11700000 4K TS-5620 RTC data register */ #define TS72XX_MODEL_PHYS_BASE 0x22000000 @@ -58,6 +60,15 @@ #define TS72XX_NAND_BUSY_SIZE 0x00001000 +#define TS72XX_RTC_INDEX_VIRT_BASE 0xfebf9000 +#define TS72XX_RTC_INDEX_PHYS_BASE 0x10800000 +#define TS72XX_RTC_INDEX_SIZE 0x00001000 + +#define TS72XX_RTC_DATA_VIRT_BASE 0xfebf8000 +#define TS72XX_RTC_DATA_PHYS_BASE 0x11700000 +#define TS72XX_RTC_DATA_SIZE 0x00001000 + + #ifndef __ASSEMBLY__ #include <asm/io.h> diff --git a/include/asm-arm/arch-imx/dma.h b/include/asm-arm/arch-imx/dma.h index b45fa367d71..621ff2c730f 100644 --- a/include/asm-arm/arch-imx/dma.h +++ b/include/asm-arm/arch-imx/dma.h @@ -17,27 +17,16 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H -/* - * DMA registration - */ - typedef enum { DMA_PRIO_HIGH = 0, - DMA_PRIO_MEDIUM = 3, - DMA_PRIO_LOW = 6 + DMA_PRIO_MEDIUM = 1, + DMA_PRIO_LOW = 2 } imx_dma_prio; -int imx_request_dma(char *name, imx_dma_prio prio, - void (*irq_handler) (int, void *, struct pt_regs *), - void (*err_handler) (int, void *, struct pt_regs *), - void *data); - -void imx_free_dma(int dma_ch); - - #define DMA_REQ_UART3_T 2 #define DMA_REQ_UART3_R 3 #define DMA_REQ_SSI2_T 4 diff --git a/include/asm-arm/arch-imx/imx-dma.h b/include/asm-arm/arch-imx/imx-dma.h new file mode 100644 index 00000000000..f2063c1d610 --- /dev/null +++ b/include/asm-arm/arch-imx/imx-dma.h @@ -0,0 +1,90 @@ +/* + * linux/include/asm-arm/imxads/dma.h + * + * Copyright (C) 1997,1998 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <asm/dma.h> + +#ifndef __ASM_ARCH_IMX_DMA_H +#define __ASM_ARCH_IMX_DMA_H + +#define IMX_DMA_CHANNELS 11 + +/* + * struct imx_dma_channel - i.MX specific DMA extension + * @name: name specified by DMA client + * @irq_handler: client callback for end of transfer + * @err_handler: client callback for error condition + * @data: clients context data for callbacks + * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE + * @sg: pointer to the actual read/written chunk for scatter-gather emulation + * @sgbc: counter of processed bytes in the actual read/written chunk + * @resbytes: total residual number of bytes to transfer + * (it can be lower or same as sum of SG mapped chunk sizes) + * @sgcount: number of chunks to be read/written + * + * Structure is used for IMX DMA processing. It would be probably good + * @struct dma_struct in the future for external interfacing and use + * @struct imx_dma_channel only as extension to it. + */ + +struct imx_dma_channel { + const char *name; + void (*irq_handler) (int, void *, struct pt_regs *); + void (*err_handler) (int, void *, struct pt_regs *); + void *data; + dmamode_t dma_mode; + struct scatterlist *sg; + unsigned int sgbc; + unsigned int sgcount; + unsigned int resbytes; + int dma_num; +}; + +extern struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; + + +/* The type to distinguish channel numbers parameter from ordinal int type */ +typedef int imx_dmach_t; + +int +imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, + unsigned int dma_length, unsigned int dev_addr, dmamode_t dmamode); + +int +imx_dma_setup_sg(imx_dmach_t dma_ch, + struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, + unsigned int dev_addr, dmamode_t dmamode); + +int +imx_dma_setup_handlers(imx_dmach_t dma_ch, + void (*irq_handler) (int, void *, struct pt_regs *), + void (*err_handler) (int, void *, struct pt_regs *), void *data); + +void imx_dma_enable(imx_dmach_t dma_ch); + +void imx_dma_disable(imx_dmach_t dma_ch); + +int imx_dma_request(imx_dmach_t dma_ch, const char *name); + +void imx_dma_free(imx_dmach_t dma_ch); + +int imx_dma_request_by_prio(imx_dmach_t *pdma_ch, const char *name, imx_dma_prio prio); + + +#endif /* _ASM_ARCH_IMX_DMA_H */ diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h index bebcf0aa0d7..6e19f46d54d 100644 --- a/include/asm-arm/arch-ixp23xx/memory.h +++ b/include/asm-arm/arch-ixp23xx/memory.h @@ -28,6 +28,7 @@ * to an address that the kernel can use. */ #ifndef __ASSEMBLY__ +#include <asm/mach-types.h> #define __virt_to_bus(v) \ ({ unsigned int ret; \ @@ -40,6 +41,22 @@ data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \ __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); }) +/* + * Coherency support. Only supported on A2 CPUs or on A1 + * systems that have the cache coherency workaround. + */ +static inline int __ixp23xx_arch_is_coherent(void) +{ + extern unsigned int processor_id; + + if (((processor_id & 15) >= 2) || machine_is_roadrunner()) + return 1; + + return 0; +} + +#define arch_is_coherent() __ixp23xx_arch_is_coherent() + #endif diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h index f85b4685a49..e4d99060a04 100644 --- a/include/asm-arm/arch-ixp23xx/platform.h +++ b/include/asm-arm/arch-ixp23xx/platform.h @@ -22,6 +22,7 @@ void ixp23xx_sys_init(void); int ixp23xx_pci_setup(int, struct pci_sys_data *); void ixp23xx_pci_preinit(void); struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*); +void ixp23xx_pci_slave_init(void); extern struct sys_timer ixp23xx_timer; diff --git a/include/asm-arm/arch-omap/aic23.h b/include/asm-arm/arch-omap/aic23.h index 590bac25b7c..6513065941d 100644 --- a/include/asm-arm/arch-omap/aic23.h +++ b/include/asm-arm/arch-omap/aic23.h @@ -57,6 +57,7 @@ #define LHV_MIN 0x0000 // Analog audio path control register +#define STA_REG(x) ((x)<<6) #define STE_ENABLED 0x0020 #define DAC_SELECTED 0x0010 #define BYPASS_ON 0x0008 @@ -109,4 +110,7 @@ #define TLV320AIC23ID1 (0x1a) // cs low #define TLV320AIC23ID2 (0x1b) // cs high +void tlv320aic23_power_up(void); +void tlv320aic23_power_down(void); + #endif /* __ASM_ARCH_AIC23_H */ diff --git a/include/asm-arm/arch-omap/board-ams-delta.h b/include/asm-arm/arch-omap/board-ams-delta.h new file mode 100644 index 00000000000..0070f6d3b75 --- /dev/null +++ b/include/asm-arm/arch-omap/board-ams-delta.h @@ -0,0 +1,65 @@ +/* + * linux/include/asm-arm/arch-omap/board-ams-delta.h + * + * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H +#define __ASM_ARCH_OMAP_AMS_DELTA_H + +#if defined (CONFIG_MACH_AMS_DELTA) + +#define AMS_DELTA_LATCH1_PHYS 0x01000000 +#define AMS_DELTA_LATCH1_VIRT 0xEA000000 +#define AMS_DELTA_MODEM_PHYS 0x04000000 +#define AMS_DELTA_MODEM_VIRT 0xEB000000 +#define AMS_DELTA_LATCH2_PHYS 0x08000000 +#define AMS_DELTA_LATCH2_VIRT 0xEC000000 + +#define AMS_DELTA_LATCH1_LED_CAMERA 0x01 +#define AMS_DELTA_LATCH1_LED_ADVERT 0x02 +#define AMS_DELTA_LATCH1_LED_EMAIL 0x04 +#define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08 +#define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10 +#define AMS_DELTA_LATCH1_LED_VOICE 0x20 + +#define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001 +#define AMS_DELTA_LATCH2_LCD_NDISP 0x0002 +#define AMS_DELTA_LATCH2_NAND_NCE 0x0004 +#define AMS_DELTA_LATCH2_NAND_NRE 0x0008 +#define AMS_DELTA_LATCH2_NAND_NWP 0x0010 +#define AMS_DELTA_LATCH2_NAND_NWE 0x0020 +#define AMS_DELTA_LATCH2_NAND_ALE 0x0040 +#define AMS_DELTA_LATCH2_NAND_CLE 0x0080 +#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000 +#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000 + +#define AMS_DELTA_GPIO_PIN_NAND_RB 12 + +#ifndef __ASSEMBLY__ +void ams_delta_latch1_write(u8 mask, u8 value); +void ams_delta_latch2_write(u16 mask, u16 value); +#endif + +#endif /* CONFIG_MACH_AMS_DELTA */ + +#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */ diff --git a/include/asm-arm/arch-omap/board-apollon.h b/include/asm-arm/arch-omap/board-apollon.h new file mode 100644 index 00000000000..de0c5b792c5 --- /dev/null +++ b/include/asm-arm/arch-omap/board-apollon.h @@ -0,0 +1,45 @@ +/* + * linux/include/asm-arm/arch-omap/board-apollon.h + * + * Hardware definitions for Samsung OMAP24XX Apollon board. + * + * Initial creation by Kyungmin Park <kyungmin.park@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP_APOLLON_H +#define __ASM_ARCH_OMAP_APOLLON_H + +/* Placeholder for APOLLON specific defines */ +/* GPMC CS0 */ +#define APOLLON_CS0_BASE 0x00000000 +/* GPMC CS1 */ +#define APOLLON_CS1_BASE 0x08000000 +#define APOLLON_ETHR_START (APOLLON_CS1_BASE + 0x300) +#define APOLLON_ETHR_GPIO_IRQ 74 +/* GPMC CS2 - reserved for OneNAND */ +#define APOLLON_CS2_BASE 0x10000000 +/* GPMC CS3 - reserved for NOR or NAND */ +#define APOLLON_CS3_BASE 0x18000000 + +#endif /* __ASM_ARCH_OMAP_APOLLON_H */ + diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h index 39ca5a31aee..b2888ef9e9b 100644 --- a/include/asm-arm/arch-omap/board-h2.h +++ b/include/asm-arm/arch-omap/board-h2.h @@ -34,9 +34,5 @@ /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ #define OMAP1610_ETHR_START 0x04000300 -/* Samsung NAND flash at CS2B or CS3(NAND Boot) */ -#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */ -#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */ - #endif /* __ASM_ARCH_OMAP_H2_H */ diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h index 1b12c1dcc2f..761ea0a1789 100644 --- a/include/asm-arm/arch-omap/board-h3.h +++ b/include/asm-arm/arch-omap/board-h3.h @@ -30,10 +30,6 @@ /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ #define OMAP1710_ETHR_START 0x04000300 -/* Samsung NAND flash at CS2B or CS3(NAND Boot) */ -#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */ -#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */ - #define MAXIRQNUM (IH_BOARD_BASE) #define MAXFIQNUM MAXIRQNUM #define MAXSWINUM MAXIRQNUM diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h index 33ea29a4165..7ef664bc9e3 100644 --- a/include/asm-arm/arch-omap/board-h4.h +++ b/include/asm-arm/arch-omap/board-h4.h @@ -33,12 +33,6 @@ /* GPMC CS1 */ #define OMAP24XX_ETHR_START 0x08000300 #define OMAP24XX_ETHR_GPIO_IRQ 92 - -#define H4_CS0_BASE 0x04000000 - -#define H4_CS0_BASE 0x04000000 - -#define H4_CS0_BASE 0x04000000 - +#define H4_CS0_BASE 0x04000000 #endif /* __ASM_ARCH_OMAP_H4_H */ diff --git a/include/asm-arm/arch-omap/board-netstar.h b/include/asm-arm/arch-omap/board-netstar.h deleted file mode 100644 index 77cc0fb54d5..00000000000 --- a/include/asm-arm/arch-omap/board-netstar.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz> - * - * Hardware definitions for OMAP5910 based NetStar board. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_NETSTAR_H -#define __ASM_ARCH_NETSTAR_H - -#include <asm/arch/tc.h> - -#define OMAP_NAND_FLASH_START1 OMAP_CS1_PHYS + (1 << 23) -#define OMAP_NAND_FLASH_START2 OMAP_CS1_PHYS + (2 << 23) - -#endif /* __ASM_ARCH_NETSTAR_H */ diff --git a/include/asm-arm/arch-omap/board-nokia.h b/include/asm-arm/arch-omap/board-nokia.h new file mode 100644 index 00000000000..72deea20349 --- /dev/null +++ b/include/asm-arm/arch-omap/board-nokia.h @@ -0,0 +1,54 @@ +/* + * linux/include/asm-arm/arch-omap/board-nokia.h + * + * Information structures for Nokia-specific board config data + * + * Copyright (C) 2005 Nokia Corporation + */ + +#ifndef _OMAP_BOARD_NOKIA_H +#define _OMAP_BOARD_NOKIA_H + +#include <linux/types.h> + +#define OMAP_TAG_NOKIA_BT 0x4e01 +#define OMAP_TAG_WLAN_CX3110X 0x4e02 +#define OMAP_TAG_CBUS 0x4e03 +#define OMAP_TAG_EM_ASIC_BB5 0x4e04 + + +#define BT_CHIP_CSR 1 +#define BT_CHIP_TI 2 + +#define BT_SYSCLK_12 1 +#define BT_SYSCLK_38_4 2 + +struct omap_bluetooth_config { + u8 chip_type; + u8 bt_wakeup_gpio; + u8 host_wakeup_gpio; + u8 reset_gpio; + u8 bt_uart; + u8 bd_addr[6]; + u8 bt_sysclk; +}; + +struct omap_wlan_cx3110x_config { + u8 chip_type; + s16 power_gpio; + s16 irq_gpio; + s16 spi_cs_gpio; +}; + +struct omap_cbus_config { + s16 clk_gpio; + s16 dat_gpio; + s16 sel_gpio; +}; + +struct omap_em_asic_bb5_config { + s16 retu_irq_gpio; + s16 tahvo_irq_gpio; +}; + +#endif diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h index 691e52a52b4..eb74420cb43 100644 --- a/include/asm-arm/arch-omap/board-perseus2.h +++ b/include/asm-arm/arch-omap/board-perseus2.h @@ -42,8 +42,4 @@ #define NR_IRQS (MAXIRQNUM + 1) -/* Samsung NAND flash at CS2B or CS3(NAND Boot) */ -#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */ -#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */ - #endif diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h index a0040cd8663..6d6240a4681 100644 --- a/include/asm-arm/arch-omap/board.h +++ b/include/asm-arm/arch-omap/board.h @@ -21,9 +21,12 @@ #define OMAP_TAG_LCD 0x4f05 #define OMAP_TAG_GPIO_SWITCH 0x4f06 #define OMAP_TAG_UART 0x4f07 +#define OMAP_TAG_FBMEM 0x4f08 +#define OMAP_TAG_STI_CONSOLE 0x4f09 #define OMAP_TAG_BOOT_REASON 0x4f80 #define OMAP_TAG_FLASH_PART 0x4f81 +#define OMAP_TAG_VERSION_STR 0x4f82 struct omap_clock_config { /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */ @@ -54,6 +57,11 @@ struct omap_serial_console_config { u32 console_speed; }; +struct omap_sti_console_config { + unsigned enable:1; + u8 channel; +}; + struct omap_usb_config { /* Configure drivers according to the connectors on your board: * - "A" connector (rectagular) @@ -87,6 +95,13 @@ struct omap_lcd_config { char ctrl_name[16]; }; +struct omap_fbmem_config { + u32 fb_sram_start; + u32 fb_sram_size; + u32 fb_sdram_start; + u32 fb_sdram_size; +}; + /* Cover: * high -> closed * low -> open @@ -106,6 +121,12 @@ struct omap_gpio_switch_config { int key_code:24; /* Linux key code */ }; +struct omap_uart_config { + /* Bit field of UARTs present; bit 0 --> UART1 */ + unsigned int enabled_uarts; +}; + + struct omap_flash_part_config { char part_table[0]; }; @@ -114,11 +135,14 @@ struct omap_boot_reason_config { char reason_str[12]; }; -struct omap_uart_config { - /* Bit field of UARTs present; bit 0 --> UART1 */ - unsigned int enabled_uarts; +struct omap_version_config { + char component[12]; + char version[12]; }; + +#include <asm-arm/arch-omap/board-nokia.h> + struct omap_board_config_entry { u16 tag; u16 len; diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index 46a0402696d..3c4eb9fbe48 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -19,6 +19,7 @@ struct clk { struct list_head node; struct module *owner; const char *name; + int id; struct clk *parent; unsigned long rate; __u32 flags; @@ -57,6 +58,7 @@ extern void propagate_rate(struct clk *clk); extern void followparent_recalc(struct clk * clk); extern void clk_allow_idle(struct clk *clk); extern void clk_deny_idle(struct clk *clk); +extern int clk_get_usecount(struct clk *clk); /* Clock flags */ #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ @@ -80,10 +82,11 @@ extern void clk_deny_idle(struct clk *clk); #define CM_PLL_SEL1 (1 << 18) #define CM_PLL_SEL2 (1 << 19) #define CM_SYSCLKOUT_SEL1 (1 << 20) -#define CLOCK_IN_OMAP730 (1 << 21) -#define CLOCK_IN_OMAP1510 (1 << 22) -#define CLOCK_IN_OMAP16XX (1 << 23) -#define CLOCK_IN_OMAP242X (1 << 24) -#define CLOCK_IN_OMAP243X (1 << 25) +#define CLOCK_IN_OMAP310 (1 << 21) +#define CLOCK_IN_OMAP730 (1 << 22) +#define CLOCK_IN_OMAP1510 (1 << 23) +#define CLOCK_IN_OMAP16XX (1 << 24) +#define CLOCK_IN_OMAP242X (1 << 25) +#define CLOCK_IN_OMAP243X (1 << 26) #endif diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index d4e73efcb81..ca1202312a4 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h @@ -404,6 +404,7 @@ extern void omap_free_lcd_dma(void); extern void omap_setup_lcd_dma(void); extern void omap_enable_lcd_dma(void); extern void omap_stop_lcd_dma(void); +extern int omap_lcd_dma_ext_running(void); extern void omap_set_lcd_dma_ext_controller(int external); extern void omap_set_lcd_dma_single_transfer(int single); extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h index 11772c792f3..e6522e6a383 100644 --- a/include/asm-arm/arch-omap/dmtimer.h +++ b/include/asm-arm/arch-omap/dmtimer.h @@ -88,5 +88,6 @@ unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer); void omap_dm_timer_reset_counter(struct omap_dm_timer *timer); int omap_dm_timers_active(void); +u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); #endif /* __ASM_ARCH_TIMER_H */ diff --git a/include/asm-arm/arch-omap/dsp.h b/include/asm-arm/arch-omap/dsp.h index 57bf4f39ca5..06dad83dd41 100644 --- a/include/asm-arm/arch-omap/dsp.h +++ b/include/asm-arm/arch-omap/dsp.h @@ -181,10 +181,16 @@ struct omap_dsp_varinfo { #define OMAP_DSP_MBCMD_PM_ENABLE 0x01 #define OMAP_DSP_MBCMD_KFUNC_FBCTL 0x00 +#define OMAP_DSP_MBCMD_KFUNC_AUDIO_PWR 0x01 +#define OMAP_DSP_MBCMD_FBCTL_UPD 0x0000 #define OMAP_DSP_MBCMD_FBCTL_ENABLE 0x0002 #define OMAP_DSP_MBCMD_FBCTL_DISABLE 0x0003 +#define OMAP_DSP_MBCMD_AUDIO_PWR_UP 0x0000 +#define OMAP_DSP_MBCMD_AUDIO_PWR_DOWN1 0x0001 +#define OMAP_DSP_MBCMD_AUDIO_PWR_DOWN2 0x0002 + #define OMAP_DSP_MBCMD_TDEL_SAFE 0x0000 #define OMAP_DSP_MBCMD_TDEL_KILL 0x0001 diff --git a/include/asm-arm/arch-omap/dsp_common.h b/include/asm-arm/arch-omap/dsp_common.h index 4fcce694405..16a459dfa71 100644 --- a/include/asm-arm/arch-omap/dsp_common.h +++ b/include/asm-arm/arch-omap/dsp_common.h @@ -27,11 +27,12 @@ #ifndef ASM_ARCH_DSP_COMMON_H #define ASM_ARCH_DSP_COMMON_H -void omap_dsp_pm_suspend(void); -void omap_dsp_pm_resume(void); -void omap_dsp_request_mpui(void); -void omap_dsp_release_mpui(void); -int omap_dsp_request_mem(void); -int omap_dsp_release_mem(void); +extern void omap_dsp_request_mpui(void); +extern void omap_dsp_release_mpui(void); +extern int omap_dsp_request_mem(void); +extern int omap_dsp_release_mem(void); + +extern void (*omap_dsp_audio_pwr_up_request)(int stage); +extern void (*omap_dsp_audio_pwr_down_request)(int stage); #endif /* ASM_ARCH_DSP_COMMON_H */ diff --git a/include/asm-arm/arch-omap/gpioexpander.h b/include/asm-arm/arch-omap/gpioexpander.h new file mode 100644 index 00000000000..7a43b0a912e --- /dev/null +++ b/include/asm-arm/arch-omap/gpioexpander.h @@ -0,0 +1,24 @@ +/* + * linux/include/asm-arm/arch-omap/gpioexpander.h + * + * + * Copyright (C) 2004 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef __ASM_ARCH_OMAP_GPIOEXPANDER_H +#define __ASM_ARCH_OMAP_GPIOEXPANDER_H + +/* Function Prototypes for GPIO Expander functions */ + +int read_gpio_expa(u8 *, int); +int write_gpio_expa(u8 , int); + +#endif /* __ASM_ARCH_OMAP_GPIOEXPANDER_H */ diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h index 5406b875c42..7909b729826 100644 --- a/include/asm-arm/arch-omap/hardware.h +++ b/include/asm-arm/arch-omap/hardware.h @@ -306,6 +306,10 @@ #include "board-h4.h" #endif +#ifdef CONFIG_MACH_OMAP_APOLLON +#include "board-apollon.h" +#endif + #ifdef CONFIG_MACH_OMAP_OSK #include "board-osk.h" #endif @@ -314,10 +318,6 @@ #include "board-voiceblue.h" #endif -#ifdef CONFIG_MACH_NETSTAR -#include "board-netstar.h" -#endif - #endif /* !__ASSEMBLER__ */ #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/include/asm-arm/arch-omap/irda.h b/include/asm-arm/arch-omap/irda.h new file mode 100644 index 00000000000..805ae3575e4 --- /dev/null +++ b/include/asm-arm/arch-omap/irda.h @@ -0,0 +1,36 @@ +/* + * linux/include/asm-arm/arch-omap/irda.h + * + * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef ASMARM_ARCH_IRDA_H +#define ASMARM_ARCH_IRDA_H + +/* board specific transceiver capabilities */ + +#define IR_SEL 1 /* Selects IrDA */ +#define IR_SIRMODE 2 +#define IR_FIRMODE 4 +#define IR_MIRMODE 8 + +struct omap_irda_config { + int transceiver_cap; + int (*transceiver_mode)(struct device *dev, int mode); + int (*select_irda)(struct device *dev, int state); + /* Very specific to the needs of some platforms (h3,h4) + * having calls which can sleep in irda_set_speed. + */ + struct work_struct gpio_expa; + int rx_channel; + int tx_channel; + unsigned long dest_start; + unsigned long src_start; + int tx_trigger; + int rx_trigger; +}; + +#endif diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h index 4ffce1d7775..42098d99f30 100644 --- a/include/asm-arm/arch-omap/irqs.h +++ b/include/asm-arm/arch-omap/irqs.h @@ -242,6 +242,11 @@ #define INT_24XX_GPIO_BANK2 30 #define INT_24XX_GPIO_BANK3 31 #define INT_24XX_GPIO_BANK4 32 +#define INT_24XX_MCBSP1_IRQ_TX 59 +#define INT_24XX_MCBSP1_IRQ_RX 60 +#define INT_24XX_MCBSP2_IRQ_TX 62 +#define INT_24XX_MCBSP2_IRQ_RX 63 +#define INT_24XX_UART3_IRQ 74 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and * 16 MPUIO lines */ diff --git a/include/asm-arm/arch-omap/keypad.h b/include/asm-arm/arch-omap/keypad.h new file mode 100644 index 00000000000..8a023a984ac --- /dev/null +++ b/include/asm-arm/arch-omap/keypad.h @@ -0,0 +1,36 @@ +/* + * linux/include/asm-arm/arch-omap/keypad.h + * + * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef ASMARM_ARCH_KEYPAD_H +#define ASMARM_ARCH_KEYPAD_H + +struct omap_kp_platform_data { + int rows; + int cols; + int *keymap; + unsigned int rep:1; + /* specific to OMAP242x*/ + unsigned int *row_gpios; + unsigned int *col_gpios; +}; + +/* Group (0..3) -- when multiple keys are pressed, only the + * keys pressed in the same group are considered as pressed. This is + * in order to workaround certain crappy HW designs that produce ghost + * keypresses. */ +#define GROUP_0 (0 << 16) +#define GROUP_1 (1 << 16) +#define GROUP_2 (2 << 16) +#define GROUP_3 (3 << 16) +#define GROUP_MASK GROUP_3 + +#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val)) + +#endif + diff --git a/include/asm-arm/arch-omap/lcd_lph8923.h b/include/asm-arm/arch-omap/lcd_lph8923.h new file mode 100644 index 00000000000..004e67e22ca --- /dev/null +++ b/include/asm-arm/arch-omap/lcd_lph8923.h @@ -0,0 +1,14 @@ +#ifndef __LCD_LPH8923_H +#define __LCD_LPH8923_H + +enum lcd_lph8923_test_num { + LCD_LPH8923_TEST_RGB_LINES, +}; + +enum lcd_lph8923_test_result { + LCD_LPH8923_TEST_SUCCESS, + LCD_LPH8923_TEST_INVALID, + LCD_LPH8923_TEST_FAILED, +}; + +#endif diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h index e79d98ab2ab..ed0dde4f721 100644 --- a/include/asm-arm/arch-omap/mcbsp.h +++ b/include/asm-arm/arch-omap/mcbsp.h @@ -37,6 +37,11 @@ #define OMAP1610_MCBSP2_BASE 0xfffb1000 #define OMAP1610_MCBSP3_BASE 0xe1017000 +#define OMAP24XX_MCBSP1_BASE 0x48074000 +#define OMAP24XX_MCBSP2_BASE 0x48076000 + +#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) + #define OMAP_MCBSP_REG_DRR2 0x00 #define OMAP_MCBSP_REG_DRR1 0x02 #define OMAP_MCBSP_REG_DXR2 0x04 @@ -71,9 +76,62 @@ #define OMAP_MAX_MCBSP_COUNT 3 +#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) +#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) + +#define AUDIO_MCBSP OMAP_MCBSP1 +#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX +#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX + +#elif defined(CONFIG_ARCH_OMAP24XX) + +#define OMAP_MCBSP_REG_DRR2 0x00 +#define OMAP_MCBSP_REG_DRR1 0x04 +#define OMAP_MCBSP_REG_DXR2 0x08 +#define OMAP_MCBSP_REG_DXR1 0x0C +#define OMAP_MCBSP_REG_SPCR2 0x10 +#define OMAP_MCBSP_REG_SPCR1 0x14 +#define OMAP_MCBSP_REG_RCR2 0x18 +#define OMAP_MCBSP_REG_RCR1 0x1C +#define OMAP_MCBSP_REG_XCR2 0x20 +#define OMAP_MCBSP_REG_XCR1 0x24 +#define OMAP_MCBSP_REG_SRGR2 0x28 +#define OMAP_MCBSP_REG_SRGR1 0x2C +#define OMAP_MCBSP_REG_MCR2 0x30 +#define OMAP_MCBSP_REG_MCR1 0x34 +#define OMAP_MCBSP_REG_RCERA 0x38 +#define OMAP_MCBSP_REG_RCERB 0x3C +#define OMAP_MCBSP_REG_XCERA 0x40 +#define OMAP_MCBSP_REG_XCERB 0x44 +#define OMAP_MCBSP_REG_PCR0 0x48 +#define OMAP_MCBSP_REG_RCERC 0x4C +#define OMAP_MCBSP_REG_RCERD 0x50 +#define OMAP_MCBSP_REG_XCERC 0x54 +#define OMAP_MCBSP_REG_XCERD 0x58 +#define OMAP_MCBSP_REG_RCERE 0x5C +#define OMAP_MCBSP_REG_RCERF 0x60 +#define OMAP_MCBSP_REG_XCERE 0x64 +#define OMAP_MCBSP_REG_XCERF 0x68 +#define OMAP_MCBSP_REG_RCERG 0x6C +#define OMAP_MCBSP_REG_RCERH 0x70 +#define OMAP_MCBSP_REG_XCERG 0x74 +#define OMAP_MCBSP_REG_XCERH 0x78 + +#define OMAP_MAX_MCBSP_COUNT 2 + +#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) +#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) + +#define AUDIO_MCBSP OMAP_MCBSP2 +#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX +#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX + +#endif + #define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg) #define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg) + /************************** McBSP SPCR1 bit definitions ***********************/ #define RRST 0x0001 #define RRDY 0x0002 @@ -195,6 +253,10 @@ typedef enum { OMAP_MCBSP3, } omap_mcbsp_id; +typedef int __bitwise omap_mcbsp_io_type_t; +#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1) +#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2) + typedef enum { OMAP_MCBSP_WORD_8 = 0, OMAP_MCBSP_WORD_12, @@ -246,6 +308,9 @@ u32 omap_mcbsp_recv_word(unsigned int id); int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); +int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word); +int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word); + /* SPI specific API */ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); diff --git a/include/asm-arm/arch-omap/mcspi.h b/include/asm-arm/arch-omap/mcspi.h new file mode 100644 index 00000000000..9e7f40a88e1 --- /dev/null +++ b/include/asm-arm/arch-omap/mcspi.h @@ -0,0 +1,16 @@ +#ifndef _OMAP2_MCSPI_H +#define _OMAP2_MCSPI_H + +struct omap2_mcspi_platform_config { + unsigned long base; + unsigned short num_cs; +}; + +struct omap2_mcspi_device_config { + unsigned turbo_mode:1; + + /* Do we want one channel enabled at the same time? */ + unsigned single_channel:1; +}; + +#endif diff --git a/include/asm-arm/arch-omap/menelaus.h b/include/asm-arm/arch-omap/menelaus.h index 46be8b8d634..88cd4c87f0d 100644 --- a/include/asm-arm/arch-omap/menelaus.h +++ b/include/asm-arm/arch-omap/menelaus.h @@ -7,7 +7,7 @@ #ifndef __ASM_ARCH_MENELAUS_H #define __ASM_ARCH_MENELAUS_H -extern void menelaus_mmc_register(void (*callback)(u8 card_mask), +extern void menelaus_mmc_register(void (*callback)(unsigned long data, u8 card_mask), unsigned long data); extern void menelaus_mmc_remove(void); extern void menelaus_mmc_opendrain(int enable); diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index 13415a9aab0..0dc24d4ba59 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -112,14 +112,13 @@ * as mux config */ #define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \ - pull_reg, pull_bit, pull_status, \ - pu_pd_reg, pu_pd_status, debug_status)\ + pull_bit, pull_status, debug_status)\ { \ .name = desc, \ .debug = debug_status, \ MUX_REG_730(mux_reg, mode_offset, mode) \ PULL_REG_730(mux_reg, pull_bit, pull_status) \ - PU_PD_REG(pu_pd_reg, pu_pd_status) \ + PU_PD_REG(NA, 0) \ }, #define MUX_CFG_24XX(desc, reg_offset, mode, \ @@ -172,6 +171,11 @@ enum omap730_index { E4_730_KBC2, F4_730_KBC3, E3_730_KBC4, + + /* USB */ + AA17_730_USB_DM, + W16_730_USB_PU_EN, + W17_730_USB_VBUSI, }; enum omap1xxx_index { @@ -403,9 +407,53 @@ enum omap24xx_index { /* 24xx Menelaus interrupt */ W19_24XX_SYS_NIRQ, + /* 24xx clock */ + W14_24XX_SYS_CLKOUT, + + /* 242X McBSP */ + Y15_24XX_MCBSP2_CLKX, + R14_24XX_MCBSP2_FSX, + W15_24XX_MCBSP2_DR, + V15_24XX_MCBSP2_DX, + /* 24xx GPIO */ + M21_242X_GPIO11, + AA10_242X_GPIO13, + AA6_242X_GPIO14, + AA4_242X_GPIO15, + Y11_242X_GPIO16, + AA12_242X_GPIO17, + AA8_242X_GPIO58, Y20_24XX_GPIO60, + W4__24XX_GPIO74, M15_24XX_GPIO92, + V14_24XX_GPIO117, + + P20_24XX_TSC_IRQ, + + /* UART3 */ + K15_24XX_UART3_TX, + K14_24XX_UART3_RX, + + /* Keypad GPIO*/ + T19_24XX_KBR0, + R19_24XX_KBR1, + V18_24XX_KBR2, + M21_24XX_KBR3, + E5__24XX_KBR4, + M18_24XX_KBR5, + R20_24XX_KBC0, + M14_24XX_KBC1, + H19_24XX_KBC2, + V17_24XX_KBC3, + P21_24XX_KBC4, + L14_24XX_KBC5, + N19_24XX_KBC6, + + /* 24xx Menelaus Keypad GPIO */ + B3__24XX_KBR5, + AA4_24XX_KBC2, + B13_24XX_KBC6, }; #ifdef CONFIG_OMAP_MUX diff --git a/include/asm-arm/arch-omap/omap-alsa.h b/include/asm-arm/arch-omap/omap-alsa.h new file mode 100644 index 00000000000..df4695474e3 --- /dev/null +++ b/include/asm-arm/arch-omap/omap-alsa.h @@ -0,0 +1,124 @@ +/* + * linux/include/asm-arm/arch-omap/omap-alsa.h + * + * Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards. + * + * Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi> + * + * Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil + * Written by Daniel Petrini, David Cohen, Anderson Briglia + * {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * History + * ------- + * + * 2005/07/25 INdT-10LE Kernel Team - Alsa driver for omap osk, + * original version based in sa1100 driver + * and omap oss driver. + */ + +#ifndef __OMAP_ALSA_H +#define __OMAP_ALSA_H + +#include <sound/driver.h> +#include <asm/arch/dma.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <asm/arch/mcbsp.h> +#include <linux/platform_device.h> + +#define DMA_BUF_SIZE (1024 * 8) + +/* + * Buffer management for alsa and dma + */ +struct audio_stream { + char *id; /* identification string */ + int stream_id; /* numeric identification */ + int dma_dev; /* dma number of that device */ + int *lch; /* Chain of channels this stream is linked to */ + char started; /* to store if the chain was started or not */ + int dma_q_head; /* DMA Channel Q Head */ + int dma_q_tail; /* DMA Channel Q Tail */ + char dma_q_count; /* DMA Channel Q Count */ + int active:1; /* we are using this stream for transfer now */ + int period; /* current transfer period */ + int periods; /* current count of periods registerd in the DMA engine */ + spinlock_t dma_lock; /* for locking in DMA operations */ + snd_pcm_substream_t *stream; /* the pcm stream */ + unsigned linked:1; /* dma channels linked */ + int offset; /* store start position of the last period in the alsa buffer */ + int (*hw_start)(void); /* interface to start HW interface, e.g. McBSP */ + int (*hw_stop)(void); /* interface to stop HW interface, e.g. McBSP */ +}; + +/* + * Alsa card structure for aic23 + */ +struct snd_card_omap_codec { + snd_card_t *card; + snd_pcm_t *pcm; + long samplerate; + struct audio_stream s[2]; /* playback & capture */ +}; + +/* Codec specific information and function pointers. + * Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c) + * are responsible for defining the function pointers. + */ +struct omap_alsa_codec_config { + char *name; + struct omap_mcbsp_reg_cfg *mcbsp_regs_alsa; + snd_pcm_hw_constraint_list_t *hw_constraints_rates; + snd_pcm_hardware_t *snd_omap_alsa_playback; + snd_pcm_hardware_t *snd_omap_alsa_capture; + void (*codec_configure_dev)(void); + void (*codec_set_samplerate)(long); + void (*codec_clock_setup)(void); + int (*codec_clock_on)(void); + int (*codec_clock_off)(void); + int (*get_default_samplerate)(void); +}; + +/*********** Mixer function prototypes *************************/ +int snd_omap_mixer(struct snd_card_omap_codec *); +void snd_omap_init_mixer(void); + +#ifdef CONFIG_PM +void snd_omap_suspend_mixer(void); +void snd_omap_resume_mixer(void); +#endif + +int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config); +int snd_omap_alsa_remove(struct platform_device *pdev); +#ifdef CONFIG_PM +int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state); +int snd_omap_alsa_resume(struct platform_device *pdev); +#else +#define snd_omap_alsa_suspend NULL +#define snd_omap_alsa_resume NULL +#endif + +void callback_omap_alsa_sound_dma(void *); + +#endif diff --git a/include/asm-arm/arch-omap/omapfb.h b/include/asm-arm/arch-omap/omapfb.h index 4ba2622cc14..fccdb3db025 100644 --- a/include/asm-arm/arch-omap/omapfb.h +++ b/include/asm-arm/arch-omap/omapfb.h @@ -34,9 +34,10 @@ #define OMAPFB_MIRROR OMAP_IOW(31, int) #define OMAPFB_SYNC_GFX OMAP_IO(37) #define OMAPFB_VSYNC OMAP_IO(38) -#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, enum omapfb_update_mode) +#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int) +#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(41, struct omapfb_update_window_old) #define OMAPFB_GET_CAPS OMAP_IOR(42, unsigned long) -#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, enum omapfb_update_mode) +#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int) #define OMAPFB_LCD_TEST OMAP_IOW(45, int) #define OMAPFB_CTRL_TEST OMAP_IOW(46, int) #define OMAPFB_UPDATE_WINDOW OMAP_IOW(47, struct omapfb_update_window) @@ -66,9 +67,14 @@ enum omapfb_color_format { }; struct omapfb_update_window { - u32 x, y; - u32 width, height; - u32 format; + __u32 x, y; + __u32 width, height; + __u32 format; +}; + +struct omapfb_update_window_old { + __u32 x, y; + __u32 width, height; }; enum omapfb_plane { @@ -83,17 +89,17 @@ enum omapfb_channel_out { }; struct omapfb_setup_plane { - u8 plane; - u8 channel_out; - u32 offset; - u32 pos_x, pos_y; - u32 width, height; - u32 color_mode; + __u8 plane; + __u8 channel_out; + __u32 offset; + __u32 pos_x, pos_y; + __u32 width, height; + __u32 color_mode; }; struct omapfb_enable_plane { - u8 plane; - u8 enable; + __u8 plane; + __u8 enable; }; enum omapfb_color_key_type { @@ -103,10 +109,10 @@ enum omapfb_color_key_type { }; struct omapfb_color_key { - u8 channel_out; - u32 background; - u32 trans_key; - u8 key_type; + __u8 channel_out; + __u32 background; + __u32 trans_key; + __u8 key_type; }; enum omapfb_update_mode { @@ -120,6 +126,9 @@ enum omapfb_update_mode { #include <linux/completion.h> #include <linux/interrupt.h> #include <linux/fb.h> +#include <linux/mutex.h> + +#include <asm/arch/board.h> #define OMAP_LCDC_INV_VSYNC 0x0001 #define OMAP_LCDC_INV_HSYNC 0x0002 @@ -184,19 +193,38 @@ struct extif_timings { int re_cycle_time; int cs_pulse_width; int access_time; + + int clk_div; + + u32 tim[5]; /* set by extif->convert_timings */ + + int converted; }; struct lcd_ctrl_extif { int (*init) (void); void (*cleanup) (void); + void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div); + int (*convert_timings) (struct extif_timings *timings); void (*set_timings) (const struct extif_timings *timings); - void (*write_command) (u32 cmd); - u32 (*read_data) (void); - void (*write_data) (u32 data); + void (*set_bits_per_cycle)(int bpc); + void (*write_command) (const void *buf, unsigned int len); + void (*read_data) (void *buf, unsigned int len); + void (*write_data) (const void *buf, unsigned int len); void (*transfer_area) (int width, int height, void (callback)(void * data), void *data); + unsigned long max_transmit_size; }; +struct omapfb_notifier_block { + struct notifier_block nb; + void *data; +}; + +typedef int (*omapfb_notifier_callback_t)(struct omapfb_notifier_block *, + unsigned long event, + struct omapfb_device *fbdev); + struct lcd_ctrl { const char *name; void *data; @@ -204,9 +232,11 @@ struct lcd_ctrl { int (*init) (struct omapfb_device *fbdev, int ext_mode, int req_vram_size); void (*cleanup) (void); + void (*bind_client) (struct omapfb_notifier_block *nb); void (*get_vram_layout)(unsigned long *size, void **virt_base, dma_addr_t *phys_base); + int (*mmap) (struct vm_area_struct *vma); unsigned long (*get_caps) (void); int (*set_update_mode)(enum omapfb_update_mode mode); enum omapfb_update_mode (*get_update_mode)(void); @@ -240,7 +270,7 @@ struct omapfb_device { int state; int ext_lcdc; /* Using external LCD controller */ - struct semaphore rqueue_sema; + struct mutex rqueue_mutex; void *vram_virt_base; dma_addr_t vram_phys_base; @@ -261,12 +291,13 @@ struct omapfb_device { struct device *dev; }; -extern struct lcd_panel h3_panel; -extern struct lcd_panel h2_panel; -extern struct lcd_panel p2_panel; -extern struct lcd_panel osk_panel; -extern struct lcd_panel innovator1610_panel; -extern struct lcd_panel innovator1510_panel; +struct omapfb_platform_data { + struct omap_lcd_config lcd; + struct omap_fbmem_config fbmem; +}; + +#define OMAPFB_EVENT_READY 1 +#define OMAPFB_EVENT_DISABLED 2 #ifdef CONFIG_ARCH_OMAP1 extern struct lcd_ctrl omap1_lcd_ctrl; @@ -274,7 +305,20 @@ extern struct lcd_ctrl omap1_lcd_ctrl; extern struct lcd_ctrl omap2_disp_ctrl; #endif +extern void omapfb_register_panel(struct lcd_panel *panel); extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval); +extern void omapfb_notify_clients(struct omapfb_device *fbdev, + unsigned long event); +extern int omapfb_register_client(struct omapfb_notifier_block *nb, + omapfb_notifier_callback_t callback, + void *callback_data); +extern int omapfb_unregister_client(struct omapfb_notifier_block *nb); +extern int omapfb_update_window_async(struct omapfb_update_window *win, + void (*callback)(void *), + void *callback_data); + +/* in arch/arm/plat-omap/devices.c */ +extern void omapfb_reserve_mem(void); #endif /* __KERNEL__ */ diff --git a/include/asm-arm/arch-omap/param.h b/include/asm-arm/arch-omap/param.h new file mode 100644 index 00000000000..face9ad41e9 --- /dev/null +++ b/include/asm-arm/arch-omap/param.h @@ -0,0 +1,8 @@ +/* + * linux/include/asm-arm/arch-omap/param.h + * + */ + +#ifdef CONFIG_OMAP_32K_TIMER_HZ +#define HZ CONFIG_OMAP_32K_TIMER_HZ +#endif diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h index 7c790425e36..05b003f3a94 100644 --- a/include/asm-arm/arch-omap/pm.h +++ b/include/asm-arm/arch-omap/pm.h @@ -49,7 +49,7 @@ /* * ---------------------------------------------------------------------------- - * Powermanagement bitmasks + * Power management bitmasks * ---------------------------------------------------------------------------- */ #define IDLE_WAIT_CYCLES 0x00000fff @@ -112,32 +112,59 @@ #endif #ifndef __ASSEMBLER__ + +#include <linux/clk.h> + +extern void prevent_idle_sleep(void); +extern void allow_idle_sleep(void); + +/** + * clk_deny_idle - Prevents the clock from being idled during MPU idle + * @clk: clock signal handle + */ +void clk_deny_idle(struct clk *clk); + +/** + * clk_allow_idle - Counters previous clk_deny_idle + * @clk: clock signal handle + */ +void clk_deny_idle(struct clk *clk); + extern void omap_pm_idle(void); extern void omap_pm_suspend(void); extern void omap730_cpu_suspend(unsigned short, unsigned short); extern void omap1510_cpu_suspend(unsigned short, unsigned short); extern void omap1610_cpu_suspend(unsigned short, unsigned short); +extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision); extern void omap730_idle_loop_suspend(void); extern void omap1510_idle_loop_suspend(void); extern void omap1610_idle_loop_suspend(void); +extern void omap24xx_idle_loop_suspend(void); + +extern unsigned int omap730_cpu_suspend_sz; +extern unsigned int omap1510_cpu_suspend_sz; +extern unsigned int omap1610_cpu_suspend_sz; +extern unsigned int omap24xx_cpu_suspend_sz; +extern unsigned int omap730_idle_loop_suspend_sz; +extern unsigned int omap1510_idle_loop_suspend_sz; +extern unsigned int omap1610_idle_loop_suspend_sz; +extern unsigned int omap24xx_idle_loop_suspend_sz; #ifdef CONFIG_OMAP_SERIAL_WAKE extern void omap_serial_wake_trigger(int enable); #else +#define omap_serial_wakeup_init() {} #define omap_serial_wake_trigger(x) {} #endif /* CONFIG_OMAP_SERIAL_WAKE */ -extern unsigned int omap730_cpu_suspend_sz; -extern unsigned int omap730_idle_loop_suspend_sz; -extern unsigned int omap1510_cpu_suspend_sz; -extern unsigned int omap1510_idle_loop_suspend_sz; -extern unsigned int omap1610_cpu_suspend_sz; -extern unsigned int omap1610_idle_loop_suspend_sz; - #define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x) #define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x)) #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] +#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x) +#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x)) +#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] + #define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x) #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] @@ -154,6 +181,10 @@ extern unsigned int omap1610_idle_loop_suspend_sz; #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x)) #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] +#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x +#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] +#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] + /* * List of global OMAP registers to preserve. * More ones like CP and general purpose register values are preserved @@ -176,6 +207,15 @@ enum arm_save_state { ARM_SLEEP_SAVE_SIZE }; +enum dsp_save_state { + DSP_SLEEP_SAVE_START = 0, + /* + * DSP registers 16 bits + */ + DSP_SLEEP_SAVE_DSP_IDLECT2, + DSP_SLEEP_SAVE_SIZE +}; + enum ulpd_save_state { ULPD_SLEEP_SAVE_START = 0, /* @@ -254,5 +294,30 @@ enum mpui1610_save_state { #endif }; +enum omap24xx_save_state { + OMAP24XX_SLEEP_SAVE_START = 0, + OMAP24XX_SLEEP_SAVE_INTC_MIR0, + OMAP24XX_SLEEP_SAVE_INTC_MIR1, + OMAP24XX_SLEEP_SAVE_INTC_MIR2, + OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE, + OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE, + OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE, + OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE, + OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE, + OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1, + OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1, + OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1, + OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1, + OMAP24XX_SLEEP_SAVE_GPIO3_OE, + OMAP24XX_SLEEP_SAVE_GPIO4_OE, + OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT, + OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT, + OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2, + OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX, + OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX, + OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0, + OMAP24XX_SLEEP_SAVE_SIZE +}; + #endif /* ASSEMBLER */ #endif /* __ASM_ARCH_OMAP_PM_H */ diff --git a/include/asm-arm/arch-omap/prcm.h b/include/asm-arm/arch-omap/prcm.h index 7b48a5cbb15..7bcaf94bde9 100644 --- a/include/asm-arm/arch-omap/prcm.h +++ b/include/asm-arm/arch-omap/prcm.h @@ -1,5 +1,7 @@ /* - * prcm.h - Access definations for use in OMAP24XX clock and power management + * linux/include/asm-arm/arch-omap/prcm.h + * + * Access definations for use in OMAP24XX clock and power management * * Copyright (C) 2005 Texas Instruments, Inc. * @@ -21,405 +23,7 @@ #ifndef __ASM_ARM_ARCH_DPM_PRCM_H #define __ASM_ARM_ARCH_DPM_PRCM_H -/* SET_PERFORMANCE_LEVEL PARAMETERS */ -#define PRCM_HALF_SPEED 1 -#define PRCM_FULL_SPEED 2 - -#ifndef __ASSEMBLER__ - -#define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset)) - -#define PRCM_REVISION PRCM_REG32(0x000) -#define PRCM_SYSCONFIG PRCM_REG32(0x010) -#define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018) -#define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C) -#define PRCM_VOLTCTRL PRCM_REG32(0x050) -#define PRCM_VOLTST PRCM_REG32(0x054) -#define PRCM_CLKSRC_CTRL PRCM_REG32(0x060) -#define PRCM_CLKOUT_CTRL PRCM_REG32(0x070) -#define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078) -#define PRCM_CLKCFG_CTRL PRCM_REG32(0x080) -#define PRCM_CLKCFG_STATUS PRCM_REG32(0x084) -#define PRCM_VOLTSETUP PRCM_REG32(0x090) -#define PRCM_CLKSSETUP PRCM_REG32(0x094) -#define PRCM_POLCTRL PRCM_REG32(0x098) - -/* GENERAL PURPOSE */ -#define GENERAL_PURPOSE1 PRCM_REG32(0x0B0) -#define GENERAL_PURPOSE2 PRCM_REG32(0x0B4) -#define GENERAL_PURPOSE3 PRCM_REG32(0x0B8) -#define GENERAL_PURPOSE4 PRCM_REG32(0x0BC) -#define GENERAL_PURPOSE5 PRCM_REG32(0x0C0) -#define GENERAL_PURPOSE6 PRCM_REG32(0x0C4) -#define GENERAL_PURPOSE7 PRCM_REG32(0x0C8) -#define GENERAL_PURPOSE8 PRCM_REG32(0x0CC) -#define GENERAL_PURPOSE9 PRCM_REG32(0x0D0) -#define GENERAL_PURPOSE10 PRCM_REG32(0x0D4) -#define GENERAL_PURPOSE11 PRCM_REG32(0x0D8) -#define GENERAL_PURPOSE12 PRCM_REG32(0x0DC) -#define GENERAL_PURPOSE13 PRCM_REG32(0x0E0) -#define GENERAL_PURPOSE14 PRCM_REG32(0x0E4) -#define GENERAL_PURPOSE15 PRCM_REG32(0x0E8) -#define GENERAL_PURPOSE16 PRCM_REG32(0x0EC) -#define GENERAL_PURPOSE17 PRCM_REG32(0x0F0) -#define GENERAL_PURPOSE18 PRCM_REG32(0x0F4) -#define GENERAL_PURPOSE19 PRCM_REG32(0x0F8) -#define GENERAL_PURPOSE20 PRCM_REG32(0x0FC) - -/* MPU */ -#define CM_CLKSEL_MPU PRCM_REG32(0x140) -#define CM_CLKSTCTRL_MPU PRCM_REG32(0x148) -#define RM_RSTST_MPU PRCM_REG32(0x158) -#define PM_WKDEP_MPU PRCM_REG32(0x1C8) -#define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4) -#define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8) -#define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC) -#define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0) -#define PM_PWSTST_MPU PRCM_REG32(0x1E4) - -/* CORE */ -#define CM_FCLKEN1_CORE PRCM_REG32(0x200) -#define CM_FCLKEN2_CORE PRCM_REG32(0x204) -#define CM_FCLKEN3_CORE PRCM_REG32(0x208) -#define CM_ICLKEN1_CORE PRCM_REG32(0x210) -#define CM_ICLKEN2_CORE PRCM_REG32(0x214) -#define CM_ICLKEN3_CORE PRCM_REG32(0x218) -#define CM_ICLKEN4_CORE PRCM_REG32(0x21C) -#define CM_IDLEST1_CORE PRCM_REG32(0x220) -#define CM_IDLEST2_CORE PRCM_REG32(0x224) -#define CM_IDLEST3_CORE PRCM_REG32(0x228) -#define CM_IDLEST4_CORE PRCM_REG32(0x22C) -#define CM_AUTOIDLE1_CORE PRCM_REG32(0x230) -#define CM_AUTOIDLE2_CORE PRCM_REG32(0x234) -#define CM_AUTOIDLE3_CORE PRCM_REG32(0x238) -#define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C) -#define CM_CLKSEL1_CORE PRCM_REG32(0x240) -#define CM_CLKSEL2_CORE PRCM_REG32(0x244) -#define CM_CLKSTCTRL_CORE PRCM_REG32(0x248) -#define PM_WKEN1_CORE PRCM_REG32(0x2A0) -#define PM_WKEN2_CORE PRCM_REG32(0x2A4) -#define PM_WKST1_CORE PRCM_REG32(0x2B0) -#define PM_WKST2_CORE PRCM_REG32(0x2B4) -#define PM_WKDEP_CORE PRCM_REG32(0x2C8) -#define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0) -#define PM_PWSTST_CORE PRCM_REG32(0x2E4) - -/* GFX */ -#define CM_FCLKEN_GFX PRCM_REG32(0x300) -#define CM_ICLKEN_GFX PRCM_REG32(0x310) -#define CM_IDLEST_GFX PRCM_REG32(0x320) -#define CM_CLKSEL_GFX PRCM_REG32(0x340) -#define CM_CLKSTCTRL_GFX PRCM_REG32(0x348) -#define RM_RSTCTRL_GFX PRCM_REG32(0x350) -#define RM_RSTST_GFX PRCM_REG32(0x358) -#define PM_WKDEP_GFX PRCM_REG32(0x3C8) -#define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0) -#define PM_PWSTST_GFX PRCM_REG32(0x3E4) - -/* WAKE-UP */ -#define CM_FCLKEN_WKUP PRCM_REG32(0x400) -#define CM_ICLKEN_WKUP PRCM_REG32(0x410) -#define CM_IDLEST_WKUP PRCM_REG32(0x420) -#define CM_AUTOIDLE_WKUP PRCM_REG32(0x430) -#define CM_CLKSEL_WKUP PRCM_REG32(0x440) -#define RM_RSTCTRL_WKUP PRCM_REG32(0x450) -#define RM_RSTTIME_WKUP PRCM_REG32(0x454) -#define RM_RSTST_WKUP PRCM_REG32(0x458) -#define PM_WKEN_WKUP PRCM_REG32(0x4A0) -#define PM_WKST_WKUP PRCM_REG32(0x4B0) - -/* CLOCKS */ -#define CM_CLKEN_PLL PRCM_REG32(0x500) -#define CM_IDLEST_CKGEN PRCM_REG32(0x520) -#define CM_AUTOIDLE_PLL PRCM_REG32(0x530) -#define CM_CLKSEL1_PLL PRCM_REG32(0x540) -#define CM_CLKSEL2_PLL PRCM_REG32(0x544) - -/* DSP */ -#define CM_FCLKEN_DSP PRCM_REG32(0x800) -#define CM_ICLKEN_DSP PRCM_REG32(0x810) -#define CM_IDLEST_DSP PRCM_REG32(0x820) -#define CM_AUTOIDLE_DSP PRCM_REG32(0x830) -#define CM_CLKSEL_DSP PRCM_REG32(0x840) -#define CM_CLKSTCTRL_DSP PRCM_REG32(0x848) -#define RM_RSTCTRL_DSP PRCM_REG32(0x850) -#define RM_RSTST_DSP PRCM_REG32(0x858) -#define PM_WKEN_DSP PRCM_REG32(0x8A0) -#define PM_WKDEP_DSP PRCM_REG32(0x8C8) -#define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0) -#define PM_PWSTST_DSP PRCM_REG32(0x8E4) -#define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0) -#define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4) - -/* IVA */ -#define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8) -#define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC) - -/* Modem on 2430 */ -#define CM_FCLKEN_MDM PRCM_REG32(0xC00) -#define CM_ICLKEN_MDM PRCM_REG32(0xC10) -#define CM_IDLEST_MDM PRCM_REG32(0xC20) -#define CM_CLKSEL_MDM PRCM_REG32(0xC40) - -/* FIXME: Move to header for 2430 */ -#define DISP_BASE (OMAP24XX_L4_IO_BASE+0x50000) -#define DISP_REG32(offset) __REG32(DISP_BASE + (offset)) - -#define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000) -#define GPMC_BASE (OMAP24XX_GPMC_BASE) -#define GPMC_REG32(offset) __REG32(GPMC_BASE + (offset)) - -#define GPT1_BASE (OMAP24XX_GPT1) -#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset)) - -/* Misc sysconfig */ -#define DISPC_SYSCONFIG DISP_REG32(0x410) -#define SPI_BASE (OMAP24XX_L4_IO_BASE+0x98000) -#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10) -#define MCSPI2_SYSCONFIG __REG32(SPI_BASE+0x2000 + 0x10) - -//#define DSP_MMU_SYSCONFIG 0x5A000010 -#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE+0x2C10) -//#define IVA_MMU_SYSCONFIG 0x5D000010 -//#define DSP_DMA_SYSCONFIG 0x00FCC02C -#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE+0x282C) -#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE+0x602C) -#define GPMC_SYSCONFIG GPMC_REG32(0x010) -#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x94010) -#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6A054) -#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6C054) -#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6E054) -//#define IVA_SYSCONFIG 0x5C060010 -#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE+0x10) -#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE+0x10) -#define SSI_SYSCONFIG __REG32(DISP_BASE+0x8010) -//#define VLYNQ_SYSCONFIG 0x67FFFE10 - -/* rkw - good cannidates for PM_ to start what nm was trying */ -#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000) -#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000) -#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000) -#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000) -#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000) -#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000) -#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000) -#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000) -#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000) -#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000) -#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000) - -#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010) -#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10) -#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10) -#define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10) -#define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10) -#define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10) -#define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10) -#define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10) -#define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10) -#define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10) -#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10) -#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10) - -#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE+(0x2000*((X)-1))) - -#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1)+0x10)) -#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2)+0x10)) -#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3)+0x10)) -#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4)+0x10)) - -/* GP TIMER 1 */ -#define GPTIMER1_TISTAT GPT1_REG32(0x014) -#define GPTIMER1_TISR GPT1_REG32(0x018) -#define GPTIMER1_TIER GPT1_REG32(0x01C) -#define GPTIMER1_TWER GPT1_REG32(0x020) -#define GPTIMER1_TCLR GPT1_REG32(0x024) -#define GPTIMER1_TCRR GPT1_REG32(0x028) -#define GPTIMER1_TLDR GPT1_REG32(0x02C) -#define GPTIMER1_TTGR GPT1_REG32(0x030) -#define GPTIMER1_TWPS GPT1_REG32(0x034) -#define GPTIMER1_TMAR GPT1_REG32(0x038) -#define GPTIMER1_TCAR1 GPT1_REG32(0x03C) -#define GPTIMER1_TSICR GPT1_REG32(0x040) -#define GPTIMER1_TCAR2 GPT1_REG32(0x044) - -/* rkw -- base fix up please... */ -#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE+0x78018) - -/* SDRC */ -#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE+0x060) -#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE+0x064) -#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE+0x068) -#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE+0x06C) -#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE+0x070) -#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE+0x084) - -/* GPIO 1 */ -#define GPIO1_BASE GPIOX_BASE(1) -#define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset)) -#define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C) -#define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018) -#define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C) -#define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028) -#define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020) -#define GPIO1_RISINGDETECT GPIO1_REG32(0x048) -#define GPIO1_DATAIN GPIO1_REG32(0x038) -#define GPIO1_OE GPIO1_REG32(0x034) -#define GPIO1_DATAOUT GPIO1_REG32(0x03C) - -/* GPIO2 */ -#define GPIO2_BASE GPIOX_BASE(2) -#define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset)) -#define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C) -#define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018) -#define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C) -#define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028) -#define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020) -#define GPIO2_RISINGDETECT GPIO2_REG32(0x048) -#define GPIO2_DATAIN GPIO2_REG32(0x038) -#define GPIO2_OE GPIO2_REG32(0x034) -#define GPIO2_DATAOUT GPIO2_REG32(0x03C) - -/* GPIO 3 */ -#define GPIO3_BASE GPIOX_BASE(3) -#define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset)) -#define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C) -#define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018) -#define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C) -#define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028) -#define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020) -#define GPIO3_RISINGDETECT GPIO3_REG32(0x048) -#define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C) -#define GPIO3_DATAIN GPIO3_REG32(0x038) -#define GPIO3_OE GPIO3_REG32(0x034) -#define GPIO3_DATAOUT GPIO3_REG32(0x03C) -#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050) -#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054) - -/* GPIO 4 */ -#define GPIO4_BASE GPIOX_BASE(4) -#define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset)) -#define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C) -#define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018) -#define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C) -#define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028) -#define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020) -#define GPIO4_RISINGDETECT GPIO4_REG32(0x048) -#define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C) -#define GPIO4_DATAIN GPIO4_REG32(0x038) -#define GPIO4_OE GPIO4_REG32(0x034) -#define GPIO4_DATAOUT GPIO4_REG32(0x03C) -#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050) -#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054) - - -/* IO CONFIG */ -#define CONTROL_BASE (OMAP24XX_CTRL_BASE) -#define CONTROL_REG32(offset) __REG32(CONTROL_BASE + (offset)) - -#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104) -#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134) -#define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8) -#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C) -#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090) -#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8) -#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) -#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0) -#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC) - -/* CONTROL */ -#define CONTROL_DEVCONF CONTROL_REG32(0x274) - -/* INTERRUPT CONTROLLER */ -#define INTC_BASE (OMAP24XX_L4_IO_BASE+0xfe000) -#define INTC_REG32(offset) __REG32(INTC_BASE + (offset)) - -#define INTC1_U_BASE INTC_REG32(0x000) -#define INTC_MIR0 INTC_REG32(0x084) -#define INTC_MIR_SET0 INTC_REG32(0x08C) -#define INTC_MIR_CLEAR0 INTC_REG32(0x088) -#define INTC_ISR_CLEAR0 INTC_REG32(0x094) -#define INTC_MIR1 INTC_REG32(0x0A4) -#define INTC_MIR_SET1 INTC_REG32(0x0AC) -#define INTC_MIR_CLEAR1 INTC_REG32(0x0A8) -#define INTC_ISR_CLEAR1 INTC_REG32(0x0B4) -#define INTC_MIR2 INTC_REG32(0x0C4) -#define INTC_MIR_SET2 INTC_REG32(0x0CC) -#define INTC_MIR_CLEAR2 INTC_REG32(0x0C8) -#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4) -#define INTC_SIR_IRQ INTC_REG32(0x040) -#define INTC_CONTROL INTC_REG32(0x048) -#define INTC_ILR11 INTC_REG32(0x12C) -#define INTC_ILR32 INTC_REG32(0x180) -#define INTC_ILR37 INTC_REG32(0x194) -#define INTC_SYSCONFIG INTC_REG32(0x010) - -/* RAM FIREWALL */ -#define RAMFW_BASE (0x68005000) -#define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset)) - -#define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048) -#define RAMFW_READPERM0 RAMFW_REG32(0x050) -#define RAMFW_WRITEPERM0 RAMFW_REG32(0x058) - -/* GPMC CS1 FPGA ON USER INTERFACE MODULE */ -//#define DEBUG_BOARD_LED_REGISTER 0x04000014 - -/* GPMC CS0 */ -#define GPMC_CONFIG1_0 GPMC_REG32(0x060) -#define GPMC_CONFIG2_0 GPMC_REG32(0x064) -#define GPMC_CONFIG3_0 GPMC_REG32(0x068) -#define GPMC_CONFIG4_0 GPMC_REG32(0x06C) -#define GPMC_CONFIG5_0 GPMC_REG32(0x070) -#define GPMC_CONFIG6_0 GPMC_REG32(0x074) -#define GPMC_CONFIG7_0 GPMC_REG32(0x078) - -/* GPMC CS1 */ -#define GPMC_CONFIG1_1 GPMC_REG32(0x090) -#define GPMC_CONFIG2_1 GPMC_REG32(0x094) -#define GPMC_CONFIG3_1 GPMC_REG32(0x098) -#define GPMC_CONFIG4_1 GPMC_REG32(0x09C) -#define GPMC_CONFIG5_1 GPMC_REG32(0x0a0) -#define GPMC_CONFIG6_1 GPMC_REG32(0x0a4) -#define GPMC_CONFIG7_1 GPMC_REG32(0x0a8) - -/* DSS */ -#define DSS_CONTROL DISP_REG32(0x040) -#define DISPC_CONTROL DISP_REG32(0x440) -#define DISPC_SYSSTATUS DISP_REG32(0x414) -#define DISPC_IRQSTATUS DISP_REG32(0x418) -#define DISPC_IRQENABLE DISP_REG32(0x41C) -#define DISPC_CONFIG DISP_REG32(0x444) -#define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C) -#define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450) -#define DISPC_TRANS_COLOR0 DISP_REG32(0x454) -#define DISPC_TRANS_COLOR1 DISP_REG32(0x458) -#define DISPC_LINE_NUMBER DISP_REG32(0x460) -#define DISPC_TIMING_H DISP_REG32(0x464) -#define DISPC_TIMING_V DISP_REG32(0x468) -#define DISPC_POL_FREQ DISP_REG32(0x46C) -#define DISPC_DIVISOR DISP_REG32(0x470) -#define DISPC_SIZE_DIG DISP_REG32(0x478) -#define DISPC_SIZE_LCD DISP_REG32(0x47C) -#define DISPC_GFX_BA0 DISP_REG32(0x480) -#define DISPC_GFX_BA1 DISP_REG32(0x484) -#define DISPC_GFX_POSITION DISP_REG32(0x488) -#define DISPC_GFX_SIZE DISP_REG32(0x48C) -#define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0) -#define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4) -#define DISPC_GFX_ROW_INC DISP_REG32(0x4AC) -#define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0) -#define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4) -#define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8) -#define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4) -#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8) -#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC) - -/* Wake up define for board */ -#define GPIO97 (1 << 1) -#define GPIO88 (1 << 24) - -#endif /* __ASSEMBLER__ */ +u32 omap_prcm_get_reset_sources(void); #endif diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h index e72ccbf0fe0..6fc0dd57b7c 100644 --- a/include/asm-arm/arch-omap/sram.h +++ b/include/asm-arm/arch-omap/sram.h @@ -20,6 +20,8 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type); extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); +extern unsigned long omap_fb_sram_start; +extern unsigned long omap_fb_sram_size; /* Do not use these */ extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl); diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h index 6724a81bd10..67970d1a202 100644 --- a/include/asm-arm/arch-omap/system.h +++ b/include/asm-arm/arch-omap/system.h @@ -9,12 +9,13 @@ #include <asm/mach-types.h> #include <asm/hardware.h> -#include <asm/arch/prcm.h> #ifndef CONFIG_MACH_VOICEBLUE #define voiceblue_reset() do {} while (0) #endif +extern void omap_prcm_arch_reset(char mode); + static inline void arch_idle(void) { cpu_do_idle(); @@ -38,24 +39,12 @@ static inline void omap1_arch_reset(char mode) omap_writew(1, ARM_RSTCT1); } -static inline void omap2_arch_reset(char mode) -{ - u32 rate; - struct clk *vclk, *sclk; - - vclk = clk_get(NULL, "virt_prcm_set"); - sclk = clk_get(NULL, "sys_ck"); - rate = clk_get_rate(sclk); - clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */ - RM_RSTCTRL_WKUP |= 2; -} - static inline void arch_reset(char mode) { if (!cpu_is_omap24xx()) omap1_arch_reset(mode); else - omap2_arch_reset(mode); + omap_prcm_arch_reset(mode); } #endif diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S index cc06b1bd37b..894c35cf3b1 100644 --- a/include/asm-arm/arch-s3c2410/entry-macro.S +++ b/include/asm-arm/arch-s3c2410/entry-macro.S @@ -6,116 +6,83 @@ * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. +*/ + +/* We have a problem that the INTOFFSET register does not always + * show one interrupt. Occasionally we get two interrupts through + * the prioritiser, and this causes the INTOFFSET register to show + * what looks like the logical-or of the two interrupt numbers. + * + * Thanks to Klaus, Shannon, et al for helping to debug this problem +*/ + +#define INTPND (0x10) +#define INTOFFSET (0x14) +#define EXTINTPEND (0xa8) +#define EXTINTMASK (0xa4) - * Modifications: - * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA - */ #include <asm/hardware.h> #include <asm/arch/irqs.h> - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov \tmp, #S3C24XX_VA_IRQ - ldr \irqnr, [ \tmp, #0x14 ] @ get irq no -30000: - teq \irqnr, #4 - teqne \irqnr, #5 - beq 1002f @ external irq reg - - @ debug check to see if interrupt reported is the same - @ as the offset.... - - teq \irqnr, #0 - beq 20002f - ldr \irqstat, [ \tmp, #0x10 ] @ INTPND - mov \irqstat, \irqstat, lsr \irqnr - tst \irqstat, #1 - bne 20002f - - /* debug/warning if we get an invalud response from the - * INTOFFSET register */ -#if 1 - stmfd r13!, { r0 - r4 , r8-r12, r14 } - ldr r1, [ \tmp, #0x14 ] @ INTOFFSET - ldr r2, [ \tmp, #0x10 ] @ INTPND - ldr r3, [ \tmp, #0x00 ] @ SRCPND - adr r0, 20003f - bl printk - b 20004f - -20003: - .ascii "<7>irq: err - bad offset %d, intpnd=%08x, srcpnd=%08x\n" - .byte 0 - .align 4 -20004: - mov r1, #1 - mov \tmp, #S3C24XX_VA_IRQ - ldmfd r13!, { r0 - r4 , r8-r12, r14 } -#endif - - @ try working out interrupt number for ourselves - mov \irqnr, #0 - ldr \irqstat, [ \tmp, #0x10 ] @ INTPND -10021: - movs \irqstat, \irqstat, lsr#1 - bcs 30000b @ try and re-start the proccess - add \irqnr, \irqnr, #1 - cmp \irqnr, #32 - ble 10021b - - @ found no interrupt, set Z flag and leave - movs \irqnr, #0 - b 1001f - -20005: -20002: @ exit - @ we base the s3c2410x interrupts at 16 and above to allow - @ isa peripherals to have their standard interrupts, also - @ ensure that Z flag is un-set on exit - - @ note, we cannot be sure if we get IRQ_EINT0 (0) that - @ there is simply no interrupt pending, so in all other - @ cases we jump to say we have found something, otherwise - @ we check to see if the interrupt really is assrted - adds \irqnr, \irqnr, #IRQ_EINT0 - teq \irqnr, #IRQ_EINT0 - bne 1001f @ exit - ldr \irqstat, [ \tmp, #0x10 ] @ INTPND - teq \irqstat, #0 - moveq \irqnr, #0 - b 1001f - - @ we get here from no main or external interrupts pending -1002: - add \tmp, \tmp, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ - ldr \irqstat, [ \tmp, # 0xa8 ] @ EXTINTPEND - ldr \irqnr, [ \tmp, # 0xa4 ] @ EXTINTMASK - - bic \irqstat, \irqstat, \irqnr @ clear masked irqs - - mov \irqnr, #IRQ_EINT4 @ start extint nos - mov \irqstat, \irqstat, lsr#4 @ ignore bottom 4 bits -10021: - movs \irqstat, \irqstat, lsr#1 - bcs 1004f - add \irqnr, \irqnr, #1 - cmp \irqnr, #IRQ_EINT23 - ble 10021b - - @ found no interrupt, set Z flag and leave - movs \irqnr, #0 - -1004: @ ensure Z flag clear in case our MOVS shifted out the last bit - teq \irqnr, #0 + mov \base, #S3C24XX_VA_IRQ + + ldr \irqstat, [ \base, #INTPND] + bics \irqnr, \irqstat, #3<<4 @@ only an GPIO IRQ + beq 2000f + + @@ try the interrupt offset register, since it is there + + ldr \irqnr, [ \base, #INTOFFSET ] + mov \tmp, #1 + tst \irqstat, \tmp, lsl \irqnr + addne \irqnr, \irqnr, #IRQ_EINT0 + bne 1001f + + @@ the number specified is not a valid irq, so try + @@ and work it out for ourselves + + mov \irqnr, #IRQ_EINT0 @@ start here + b 3000f + +2000: + @@ load the GPIO interrupt register, and check it + + add \tmp, \base, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ + ldr \irqstat, [ \tmp, # EXTINTPEND ] + ldr \irqnr, [ \tmp, # EXTINTMASK ] + bics \irqstat, \irqstat, \irqnr + beq 1001f + + mov \irqnr, #(IRQ_EINT4 - 4) + + @@ work out which irq (if any) we got +3000: + movs \tmp, \irqstat, lsl#16 + addeq \irqnr, \irqnr, #16 + moveq \irqstat, \irqstat, lsr#16 + tst \irqstat, #0xff + addeq \irqnr, \irqnr, #8 + moveq \irqstat, \irqstat, lsr#8 + tst \irqstat, #0xf + addeq \irqnr, \irqnr, #4 + moveq \irqstat, \irqstat, lsr#4 + tst \irqstat, #0x3 + addeq \irqnr, \irqnr, #2 + moveq \irqstat, \irqstat, lsr#2 + tst \irqstat, #0x1 + addeq \irqnr, \irqnr, #1 + + @@ we have the value + movs \irqnr, \irqnr + 1001: - @ exit irq routine - .endm + @@ exit here, Z flag unset if IRQ + .endm /* currently don't need an disable_fiq macro */ .macro disable_fiq .endm - - diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h index e3e8541ee63..63ca7412a46 100644 --- a/include/asm-arm/dma-mapping.h +++ b/include/asm-arm/dma-mapping.h @@ -47,7 +47,7 @@ static inline int dma_get_cache_alignment(void) static inline int dma_is_consistent(dma_addr_t handle) { - return 0; + return !!arch_is_coherent(); } /* @@ -145,7 +145,9 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr, size_t size, enum dma_data_direction dir) { - consistent_sync(cpu_addr, size, dir); + if (!arch_is_coherent()) + consistent_sync(cpu_addr, size, dir); + return virt_to_dma(dev, (unsigned long)cpu_addr); } #else @@ -255,7 +257,9 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, sg->dma_address = page_to_dma(dev, sg->page) + sg->offset; virt = page_address(sg->page) + sg->offset; - consistent_sync(virt, sg->length, dir); + + if (!arch_is_coherent()) + consistent_sync(virt, sg->length, dir); } return nents; @@ -310,14 +314,16 @@ static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size, enum dma_data_direction dir) { - consistent_sync((void *)dma_to_virt(dev, handle), size, dir); + if (!arch_is_coherent()) + consistent_sync((void *)dma_to_virt(dev, handle), size, dir); } static inline void dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size, enum dma_data_direction dir) { - consistent_sync((void *)dma_to_virt(dev, handle), size, dir); + if (!arch_is_coherent()) + consistent_sync((void *)dma_to_virt(dev, handle), size, dir); } #else extern void dma_sync_single_for_cpu(struct device*, dma_addr_t, size_t, enum dma_data_direction); @@ -347,7 +353,8 @@ dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents, for (i = 0; i < nents; i++, sg++) { char *virt = page_address(sg->page) + sg->offset; - consistent_sync(virt, sg->length, dir); + if (!arch_is_coherent()) + consistent_sync(virt, sg->length, dir); } } @@ -359,7 +366,8 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents, for (i = 0; i < nents; i++, sg++) { char *virt = page_address(sg->page) + sg->offset; - consistent_sync(virt, sg->length, dir); + if (!arch_is_coherent()) + consistent_sync(virt, sg->length, dir); } } #else diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index afa5c3ea077..2b3cf69b3ed 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h @@ -234,6 +234,14 @@ static inline __deprecated void *bus_to_virt(unsigned long x) #define virt_to_dma(dev, addr) (__arch_virt_to_dma(dev, addr)) #endif +/* + * Optional coherency support. Currently used only by selected + * Intel XSC3-based systems. + */ +#ifndef arch_is_coherent +#define arch_is_coherent() 0 +#endif + #endif #include <asm-generic/memory_model.h> diff --git a/include/asm-arm/pgtable-hwdef.h b/include/asm-arm/pgtable-hwdef.h index 1d033495cc7..1bc1f997bda 100644 --- a/include/asm-arm/pgtable-hwdef.h +++ b/include/asm-arm/pgtable-hwdef.h @@ -73,6 +73,7 @@ #define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) #define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ #define PTE_EXT_APX (1 << 9) /* v6 */ +#define PTE_EXT_COHERENT (1 << 9) /* XScale3 */ #define PTE_EXT_SHARED (1 << 10) /* v6 */ #define PTE_EXT_NG (1 << 11) /* v6 */ diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index e595ae24efe..e85c08d78dd 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -156,6 +156,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #define L_PTE_WRITE (1 << 5) #define L_PTE_EXEC (1 << 6) #define L_PTE_DIRTY (1 << 7) +#define L_PTE_COHERENT (1 << 9) /* I/O coherent (xsc3) */ #define L_PTE_SHARED (1 << 10) /* shared between CPUs (v6) */ #define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */ |