summaryrefslogtreecommitdiffstats
path: root/include/asm-blackfin/cache.h
diff options
context:
space:
mode:
authorDmitry Torokhov <dtor@insightbb.com>2007-05-08 01:31:11 -0400
committerDmitry Torokhov <dtor@insightbb.com>2007-05-08 01:31:11 -0400
commit334d0dd8b660557608142f0f77abc6812b48f08b (patch)
tree9393a9aa099d7d42deda5f9f5054796c0c769be7 /include/asm-blackfin/cache.h
parent3f07d8796262f6aee135c8dd9a91210da9f888e4 (diff)
parent5b94f675f57e4ff16c8fda09088d7480a84dcd91 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-blackfin/cache.h')
-rw-r--r--include/asm-blackfin/cache.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/include/asm-blackfin/cache.h b/include/asm-blackfin/cache.h
new file mode 100644
index 00000000000..023d72133b5
--- /dev/null
+++ b/include/asm-blackfin/cache.h
@@ -0,0 +1,29 @@
+/*
+ * include/asm-blackfin/cache.h
+ */
+#ifndef __ARCH_BLACKFIN_CACHE_H
+#define __ARCH_BLACKFIN_CACHE_H
+
+/*
+ * Bytes per L1 cache line
+ * Blackfin loads 32 bytes for cache
+ */
+#define L1_CACHE_SHIFT 5
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+#define SMP_CACHE_BYTES L1_CACHE_BYTES
+
+/*
+ * Put cacheline_aliged data to L1 data memory
+ */
+#ifdef CONFIG_CACHELINE_ALIGNED_L1
+#define __cacheline_aligned \
+ __attribute__((__aligned__(L1_CACHE_BYTES), \
+ __section__(".data_l1.cacheline_aligned")))
+#endif
+
+/*
+ * largest L1 which this arch supports
+ */
+#define L1_CACHE_SHIFT_MAX 5
+
+#endif