diff options
| author | Mike Frysinger <michael.frysinger@analog.com> | 2007-08-05 17:32:25 +0800 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-08-05 17:32:25 +0800 |
| commit | bc8c84c947ad65cd2850c43f96bea825e426f9eb (patch) | |
| tree | b0115bbd27e6158d753e4fc58633bcbb510b5c2c /include/asm-blackfin/mach-bf527/anomaly.h | |
| parent | fb51d566803413d2682ca718aef1c6f946fdab05 (diff) | |
Blackfin arch: update to latest anomaly sheets
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf527/anomaly.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf527/anomaly.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h new file mode 100644 index 00000000000..6112bc38282 --- /dev/null +++ b/include/asm-blackfin/mach-bf527/anomaly.h @@ -0,0 +1,39 @@ +/* + * File: include/asm-blackfin/mach-bf527/anomaly.h + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * Copyright (C) 2004-2007 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +/* This file shoule be up to date with: + * - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List + */ + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ + +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ +#define ANOMALY_05000074 (1) +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ +#define ANOMALY_05000119 (1) +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ +#define ANOMALY_05000122 (1) +/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +#define ANOMALY_05000245 (1) +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ +#define ANOMALY_05000265 (1) +/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ +#define ANOMALY_05000301 (1) +/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +#define ANOMALY_05000312 (1) +/* Incorrect Access of OTP_STATUS During otp_write() Function */ +#define ANOMALY_05000328 (1) +/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ +#define ANOMALY_05000337 (1) +/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */ +#define ANOMALY_05000342 (1) +/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ +#define ANOMALY_05000347 (1) + +#endif |