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authorDavid Woodhouse <dwmw2@infradead.org>2007-08-01 11:23:57 +0100
committerDavid Woodhouse <dwmw2@infradead.org>2007-08-01 11:23:57 +0100
commit440fdb53b4ae58602711b5b8c3a139ace2404dbb (patch)
treec6fb88d6ad537ec53aeecadc75a61ab6147d4c9c /include/asm-blackfin/mach-bf561/defBF561.h
parent8b2b403ce0f1a816b7a6a4f47c8798003b26c07a (diff)
parent8d4fbcfbe0a4bfc73e7f0297c59ae514e1f1436f (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-blackfin/mach-bf561/defBF561.h')
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 89150ecb909..0f2dc6e6335 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -52,6 +52,10 @@
#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
#define CHIPID 0xFFC00014 /* Chip ID Register */
+/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
+#define SWRST SICA_SWRST
+#define SYSCR SICA_SYSCR
+
/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define SICA_SWRST 0xFFC00100 /* Software Reset register */
#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */