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authorBryan Wu <bryan.wu@analog.com>2008-01-27 18:38:12 +0800
committerBryan Wu <bryan.wu@analog.com>2008-01-27 18:38:12 +0800
commit408dbc0da29913f99e56001db892eb653b47c13b (patch)
tree6a2e38f744e8fd6512739886aa459b1cb26cefdf /include/asm-blackfin
parentfc97551db9e4e9402ff2b5c94be8267b2e5f32f4 (diff)
[Blackfin] arch: remove old I2C BF54x porting.
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin')
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h33
1 files changed, 0 insertions, 33 deletions
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index aefab3f618c..19ddcd83c71 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -244,39 +244,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
-#define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
-#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val)
-#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL)
-#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val)
-#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-
/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
/* SPORT1 Registers */