diff options
author | Arnd Bergmann <arnd@arndb.de> | 2014-11-11 19:55:45 +0100 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2014-11-11 19:55:45 +0100 |
commit | 1c8d29696f0d79902962526d6c54ebfeb842c61d (patch) | |
tree | 047caddef4ee91e42002bc1234d273c6fbc54967 /include/asm-generic | |
parent | 3ba5acf368ae415cd14d026b7cfe29de942b65fc (diff) | |
parent | a8e0aead70b4af957e6b27b82fba849c6179b707 (diff) |
Merge branch 'io' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into asm-generic
* 'io' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux:
documentation: memory-barriers: clarify relaxed io accessor semantics
x86: io: implement dummy relaxed accessor macros for writes
tile: io: implement dummy relaxed accessor macros for writes
sparc: io: implement dummy relaxed accessor macros for writes
powerpc: io: implement dummy relaxed accessor macros for writes
parisc: io: implement dummy relaxed accessor macros for writes
mn10300: io: implement dummy relaxed accessor macros for writes
m68k: io: implement dummy relaxed accessor macros for writes
m32r: io: implement dummy relaxed accessor macros for writes
ia64: io: implement dummy relaxed accessor macros for writes
cris: io: implement dummy relaxed accessor macros for writes
frv: io: implement dummy relaxed accessor macros for writes
xtensa: io: remove dummy relaxed accessor macros for reads
s390: io: remove dummy relaxed accessor macros for reads
microblaze: io: remove dummy relaxed accessor macros
asm-generic: io: implement relaxed accessor macros as conditional wrappers
Conflicts:
include/asm-generic/io.h
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include/asm-generic')
-rw-r--r-- | include/asm-generic/io.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index 00483d769d8..9db042304df 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -175,6 +175,43 @@ static inline void writeq(u64 value, volatile void __iomem *addr) #endif /* CONFIG_64BIT */ /* + * {read,write}{b,w,l,q}_relaxed() are like the regular version, but + * are not guaranteed to provide ordering against spinlocks or memory + * accesses. + */ +#ifndef readb_relaxed +#define readb_relaxed readb +#endif + +#ifndef readw_relaxed +#define readw_relaxed readw +#endif + +#ifndef readl_relaxed +#define readl_relaxed readl +#endif + +#ifndef readq_relaxed +#define readq_relaxed readq +#endif + +#ifndef writeb_relaxed +#define writeb_relaxed writeb +#endif + +#ifndef writew_relaxed +#define writew_relaxed writew +#endif + +#ifndef writel_relaxed +#define writel_relaxed writel +#endif + +#ifndef writeq_relaxed +#define writeq_relaxed writeq +#endif + +/* * {read,write}s{b,w,l,q}() repeatedly access the same memory address in * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times). */ |