diff options
| author | Robin Holt <holt@sgi.com> | 2005-11-11 09:35:43 -0600 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2005-11-11 09:37:29 -0800 |
| commit | 837cd0bdf54dd954cd6aa43d250f75ab5db79617 (patch) | |
| tree | ef28b91f1ac8c1c9f4244da9be1f994306ef4070 /include/asm-ia64/pgalloc.h | |
| parent | d12eb7e11cf30c30f639b2093735af2ac177830b (diff) | |
[IA64] 4-level page tables
This patch introduces 4-level page tables to ia64. I have run
some benchmarks and found nothing interesting. Performance has
consistently fallen within the noise range.
It also introduces a config option (setting the default to 3
levels). The config option prevents having 4 level page
tables with 64k base page size.
Signed-off-by: Robin Holt <holt@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-ia64/pgalloc.h')
| -rw-r--r-- | include/asm-ia64/pgalloc.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/include/asm-ia64/pgalloc.h b/include/asm-ia64/pgalloc.h index a5f214554af..f2f23384647 100644 --- a/include/asm-ia64/pgalloc.h +++ b/include/asm-ia64/pgalloc.h @@ -86,6 +86,25 @@ static inline void pgd_free(pgd_t * pgd) pgtable_quicklist_free(pgd); } +#ifdef CONFIG_PGTABLE_4 +static inline void +pgd_populate(struct mm_struct *mm, pgd_t * pgd_entry, pud_t * pud) +{ + pgd_val(*pgd_entry) = __pa(pud); +} + +static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr) +{ + return pgtable_quicklist_alloc(); +} + +static inline void pud_free(pud_t * pud) +{ + pgtable_quicklist_free(pud); +} +#define __pud_free_tlb(tlb, pud) pud_free(pud) +#endif /* CONFIG_PGTABLE_4 */ + static inline void pud_populate(struct mm_struct *mm, pud_t * pud_entry, pmd_t * pmd) { |