diff options
| author | Fenghua Yu <fenghua.yu@intel.com> | 2008-04-04 11:05:59 -0700 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2008-04-04 11:05:59 -0700 |
| commit | 2046b94e7c4fce92eb8165c2c36c6478f4927178 (patch) | |
| tree | 0dbbdf17d64b521f2debcc8677368ceec8805d8c /include/asm-ia64/tlbflush.h | |
| parent | e315c121a858499d84dc88c499046b9f10bb61ec (diff) | |
[IA64] Multiple outstanding ptc.g instruction support
According to SDM2.2, Itanium supports multiple outstanding ptc.g instructions.
But current kernel function ia64_global_tlb_purge() uses a spinlock to serialize
ptc.g instructions issued by multiple processors. This serialization might have
scalability issue on a big SMP machine where many processors could purge TLB
in parallel.
The patch fixes this problem by issuing multiple ptc.g instructions in
ia64_global_tlb_purge(). It also adds support for the "PALO" table to get
a platform view of the max number of outstanding ptc.g instructions (which
may be different from the processor view found from PAL_VM_SUMMARY).
PALO specification can be found at: http://www.dig64.org/home/DIG64_PALO_R1_0.pdf
spinaphore implementation by Matthew Wilcox.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include/asm-ia64/tlbflush.h')
| -rw-r--r-- | include/asm-ia64/tlbflush.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-ia64/tlbflush.h b/include/asm-ia64/tlbflush.h index 7774a1cac0c..3be25dfed16 100644 --- a/include/asm-ia64/tlbflush.h +++ b/include/asm-ia64/tlbflush.h @@ -17,6 +17,7 @@ * Now for some TLB flushing routines. This is the kind of stuff that * can be very expensive, so try to avoid them whenever possible. */ +extern void setup_ptcg_sem(int max_purges, int from_palo); /* * Flush everything (kernel mapping may also have changed due to |