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authorIngo Molnar <mingo@elte.hu>2009-05-11 14:44:27 +0200
committerIngo Molnar <mingo@elte.hu>2009-05-11 14:44:31 +0200
commit41fb454ebe6024f5c1e3b3cbc0abc0da762e7b51 (patch)
tree51c50bcb67a5039448ddfa1869d7948cab1217e9 /include/asm-m32r/cachectl.h
parent19c1a6f5764d787113fa323ffb18be7991208f82 (diff)
parent091bf7624d1c90cec9e578a18529f615213ff847 (diff)
Merge commit 'v2.6.30-rc5' into core/iommu
Merge reason: core/iommu was on an .30-rc1 base, update it to .30-rc5 to refresh. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-m32r/cachectl.h')
-rw-r--r--include/asm-m32r/cachectl.h26
1 files changed, 0 insertions, 26 deletions
diff --git a/include/asm-m32r/cachectl.h b/include/asm-m32r/cachectl.h
deleted file mode 100644
index 2aab8f6fff4..00000000000
--- a/include/asm-m32r/cachectl.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * cachectl.h -- defines for M32R cache control system calls
- *
- * Copyright (C) 2003 by Kazuhiro Inaoka
- */
-#ifndef __ASM_M32R_CACHECTL
-#define __ASM_M32R_CACHECTL
-
-/*
- * Options for cacheflush system call
- *
- * cacheflush() is currently fluch_cache_all().
- */
-#define ICACHE (1<<0) /* flush instruction cache */
-#define DCACHE (1<<1) /* writeback and flush data cache */
-#define BCACHE (ICACHE|DCACHE) /* flush both caches */
-
-/*
- * Caching modes for the cachectl(2) call
- *
- * cachectl(2) is currently not supported and returns ENOSYS.
- */
-#define CACHEABLE 0 /* make pages cacheable */
-#define UNCACHEABLE 1 /* make pages uncacheable */
-
-#endif /* __ASM_M32R_CACHECTL */