diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2007-07-14 13:24:05 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-07-20 18:57:39 +0100 |
| commit | 17099b1142f6c0359fca60a3464dea8fb30badea (patch) | |
| tree | 26b9f3955dca84ccab594a76680c2a71e166768a /include/asm-mips/barrier.h | |
| parent | ed203dadcd1373e80e95b04075e1eefc554a914b (diff) | |
[MIPS] Make support for weakly ordered LL/SC a config option.
None of weakly ordered processor supported in tree need this but it seems
like this could change ...
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/barrier.h')
| -rw-r--r-- | include/asm-mips/barrier.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/asm-mips/barrier.h b/include/asm-mips/barrier.h index ed82631b001..9d8cfbb5e79 100644 --- a/include/asm-mips/barrier.h +++ b/include/asm-mips/barrier.h @@ -121,6 +121,11 @@ #else #define __WEAK_ORDERING_MB " \n" #endif +#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP) +#define __WEAK_LLSC_MB " sync \n" +#else +#define __WEAK_LLSC_MB " \n" +#endif #define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") #define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory") @@ -129,4 +134,8 @@ #define set_mb(var, value) \ do { var = value; smp_mb(); } while (0) +#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") +#define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") +#define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") + #endif /* __ASM_BARRIER_H */ |