diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2006-03-13 16:16:29 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-03-18 16:59:26 +0000 |
| commit | a3c4946db4fe64cb21b66a09e89890678aac6d65 (patch) | |
| tree | 3b63d5e765af3eedbc1cda84135f1b702a43a6f2 /include/asm-mips/cpu-info.h | |
| parent | 3a2f735700332621274aca752be3b6f839fa47e7 (diff) | |
[MIPS] SB1: Fix interrupt disable hazard.
The SB1 core has a three cycle interrupt disable hazard but we were
wrongly treating it as fully interlocked.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cpu-info.h')
0 files changed, 0 insertions, 0 deletions