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| author | Steve French <sfrench@us.ibm.com> | 2007-11-25 09:53:27 +0000 |
|---|---|---|
| committer | Steve French <sfrench@us.ibm.com> | 2007-11-25 09:53:27 +0000 |
| commit | 058250a0d5886b4d96a195ecc7e3a75e2df5e4b1 (patch) | |
| tree | fb67e8f5258c6aa11d4e8c39650e23de7556b38d /include/asm-mips/cpu-info.h | |
| parent | cea218054ad277d6c126890213afde07b4eb1602 (diff) | |
| parent | 2ffbb8377c7a0713baf6644e285adc27a5654582 (diff) | |
Merge branch 'master' of /pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-mips/cpu-info.h')
| -rw-r--r-- | include/asm-mips/cpu-info.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index 94f1c817236..ed5c02c6afb 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -54,6 +54,7 @@ struct cpuinfo_mips { struct cache_desc dcache; /* Primary D or combined I/D cache */ struct cache_desc scache; /* Secondary cache */ struct cache_desc tcache; /* Tertiary/split secondary cache */ + int srsets; /* Shadow register sets */ #if defined(CONFIG_MIPS_MT_SMTC) /* * In the MIPS MT "SMTC" model, each TC is considered |